SONIX SN32F107, User Manual

Page: 59 / 184

SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 59
Version 1.9
22:20 WDTPRE[2:0]
WDT clock source prescale value
000: WDT_PCLK = WDT clock source / 1
001: WDT_PCLK = WDT clock source / 2
010: WDT_PCLK = WDT clock source / 4
011: WDT_PCLK = WDT clock source / 8
100: WDT_PCLK = WDT clock source / 16
101: WDT_PCLK = WDT clock source / 32
Other: Reserved
R/W 0
19:15 Reserved R 0
14:12 I2SPRE[2:0]
I2S clock source prescale value
000: HCLK / 1
001: HCLK / 2
010: HCLK / 4
011: HCLK / 8
100: HCLK / 16
Other: Reserved
R/W 0
11
Reserved R 0
10:8 I2C0PRE[2:0]
I2C0 clock source prescale value
000: HCLK / 1
001: HCLK / 2
010: HCLK / 4
011: HCLK / 8
100: HCLK / 16
Other: Reserved
R/W 0
7 Reserved R 0
6:4 UART1PRE[2:0]
UART1 clock source prescale value
000: HCLK / 1
001: HCLK / 2
010: HCLK / 4
011: HCLK / 8
100: HCLK / 16
Other: Reserved
R/W 0
3 Reserved R 0
2:0 UART0PRE[2:0]
UART0 clock source prescale value
000: HCLK / 1
001: HCLK / 2
010: HCLK / 4
011: HCLK / 8
100: HCLK / 16
Other: Reserved
R/W 0
3.4.4 Peripheral Reset register (SYS1_PRST)
Address Offset: 0x0C
All bits are cleared by HW automatically after setting as “1”.
Bit Name Description Attribute Reset
31:27 Reserved R 0
26 CODECADRST
Codec ADC reset
0: No effect
1: Reset Codec ADC
R/W 0
25 CODECDARST
Codec DAC reset
0: No effect
1: Reset Codec DAC
R/W 0
24 WDTRST
WDT reset
0: No effect
1: Reset WDT
R/W 0
23 RTCRST
RTC reset
0: No effect
1: Reset RTC
R/W 0
22 I2SRST
I2S reset
0: No effect
1: Reset I2S
R/W 0