7
Configuration 1
Fig 1-1: Connecting the Auricon 4.4 to Unbalanced Inputs
It is possible to achieve an acceptable connection without using a balancing
amplifier or transformer, provided the cable distance is short, and the
following connection method is followed:
Fig 1-2: Connecting the Auricon 4.4 to Unbalanced Inputs Without a Transformer
In the diagram above, the non-phase output signal is left disconnected, this
is necessary to prevent damage to the Auricon 4.4 output amplifier.
The output level will be 6dB lower than expected due to the non-
connection of the non-phase signal.
Should there be a phase error in your system, simply disconnect the phase
output signal and connect the non-phase signal to the unbalanced input
instead.
Fig 1-3: Connecting the Auricon 4.4 to Unbalanced Outputs
Going the other way from unbalanced to balanced is easy if the signal
level is adequate. Simply connect the balanced input across the active
and earth of the unbalanced output. In most cases, though, the level at
the unbalanced output will be too low so you will need an amplifier. If this
is the case it is probably best to do the job properly and use a balancing
amplifier.
Finally, note that the shields on the audio cables should only be connected
at one end. In the world of balanced audio, the shields are simply that -
electrostatic screens - and should not be used for earth returns.
Functional Description
The balanced audio inputs are buffered, attenuated and filtered prior to
being coupled into the A/D converters. From the D/A converters, differential
line driver amplifiers provide a maximum output level of +24dBm and also
incorporate low pass filtering to attenuate the out-of-band noise produced
by the converters.
Digitized audio is passed in serial form between the converters and the
Xilinx Spartan 6 FPGA. The FPGA provides circular buffers as short term FIFO
storage to cover latency times between PCIe transfers, and also performs
the level adjustment and mixing functions. Card-initiated bus mastering is
used for audio data transfer through the FPGA’s integrated PCIe endpoint.
Unbalanced
Input
Balanced
Output
Shielded Twisted Pair
Unbalanced
Input
Balanced
Output
Shielded Single Core
+
+
-
x
Unbalanced
Output
Balanced
Input
Shielded Twisted Pair
