SolidRun i.MX8M Quad User Manual Download Page 16 | Manualshive

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SolidRun i.MX8M Quad User Manual Download Page 16

16

HDMI

The i.MX8 supports the HDMI interface including the signal termination. The following figure
describes the HDMI interface.

The HDMI main features are:

•

On board pull-up termination to support HDMI levels.

•

HDMI HPD support 5V level,

•

HDMI DDC doesn’t support PU, need to support on carrier

board.

•

Up to 4Kp60 video/graphics display over HDMI 2.0a with HDCP 2.2 encryption and audio
formats including Dolby Digital, DTS, TrueHD, LPCM.

For more details check the i.MX8 datasheet.

Please Note:

to support DPI, the pull-Up termination resistors are not

assembled.

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Summary of Contents for i.MX8M Quad

Page 1: ...SOM i MX 8M User Manual NXP i MX 8M based SOM Rev 1 0 EMBEDDED EDGE COMPUTING SolidRun Ltd 7 Hamada st Yokne am Illit 2069201 Israel www solid run com...

Page 2: ...by reason of negligence will be accepted by SolidRun Ltd its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document SolidRun Ltd...

Page 3: ...HY 10 WI FI 11AC B G N 2TX2R TYPE 1216 AND BT 5 0 10 MIPI CSI 2 CAMERA INTERFACE 11 i MX8 SOM External Interfaces 12 General 12 Supported Interfaces 12 Power and Reset 23 Reset 23 i MX8 SOM Integratio...

Page 4: ...pins number NXP i MX8M SoC supports dual quad lite and quad versions o Up to quad Cortex A53 and up to 1 5GHz o Cortex M4 subsystem processor supports real time tasks o Industry leading audio voice a...

Page 5: ...runs Android and Linux with different distribution variants use cases Description Block Diagram The following figure describes the i MX8 Blocks Diagram 10 100 1000 AR8031 GE PHY RGMII 32 Bits Up to 4...

Page 6: ...2 0a HDMI 1 4 interface 4 lanes MIPI DSI interface Two 4 lanes MIPI CSI 2 10 100 1000 Mbps Ethernet PHY supporting 1588 standard PPS output Wi Fi 11ac b g n 2Tx2R BT V4 1 LE M 2 Type 1216 based on Qu...

Page 7: ...uad Arm Cortex A53 core which operates at speeds of up to 1 5 GHz A general purpose Cortex M4 core processor is for low power processing The following figure describes the i MX8 SoC s main features Fo...

Page 8: ...t various low power modes clock and power gated operation Support Self Refresh mode eMMC NAND Flash Up to 64GB memory space 8 Bits data bus Support MMC standard up to version 5 0 Up to 1600 Mbps of da...

Page 9: ...SOM sconfigurations Micro SD Carrier Optional on Carrier board IMX 8 uSDHC 1 Implements 4 data bits Support SD SDIO standard up to version 3 0 Up to 400 Mbps of data transfer in SDR mode and up to 800...

Page 10: ...t interface for 1000BASE T 100BASE TX and 10BASE Te Atheros AR8031 PHY Supports 1588 PPS signal 25M clock supports Synchronous Ethernet WI FI 11AC B G N 2TX2R TYPE 1216 AND BT 5 0 The following figure...

Page 11: ...board to support BT over the M 2 module Global certification BT 5 0 The i MX8 SOM uses U BLOX s NINA B111 module The module is based on Nordic s nRF52832 BT SoC The module main features are Bluetooth...

Page 12: ...F40 is due to the following criteria Miniature 0 4m pitch Highly reliable manufacturer Availability worldwide distribution channels Excellent signal integrity supports 6Gbps o Please contact Hirose or...

Page 13: ...rts two USB 3 0 interfaces The following figure describes the USB interfaces C o n n e c RX_P N t DP DN o r The USB main features are USB 1 and USB 2 are directly connected to the connectors No HUB Th...

Page 14: ...nnel 1 Implements all three CSI 2 MIPI layers Scalable data lane support 1 to 4 Data Lanes Supports high speed mode 80Mbps 1 5Gbps per lane providing 4K 30fpscapability for the 4 lanes Virtual Channel...

Page 15: ...gure describes the audio interface RXD TXD T RXC T RXFS MCL RXD TXD T RXC T RXFS MCLK SPDIF OUT The Audio main features are SAI1 supports 8TX and 8 RX channels SAI2 and SAI3 supports RX and TX SPDIF O...

Page 16: ...rmination to support HDMI levels HDMI HPD support 5V level HDMI DDC doesn t support PU need to support on carrier board Up to 4Kp60 video graphics display over HDMI 2 0a with HDCP 2 2 encryption and a...

Page 17: ...s TX RX CTS and RTS UART 4 support TX and RX It has an assembly options o On SOM BT module o Free UART on carrier board High speed TIA EIA 232 F compatible up to Mbit s 9 bit or Multidrop mode RS 485...

Page 18: ...annel 1 are available as GPIO I2C i MX8 supports up to four I2c Interfaces The following figure describes the I2C interfaces EEPROM PMIC 1K Camera FPC IMX 8 0x50 I2C1 I2C2 I2C3 The I2C main features a...

Page 19: ...eved For more details check the i MX8 datasheet uSD The uSD supports the following features i MX8 uSDHC 1 Implements 4 data bits Support SD SDIO standard up to version 3 0 Up to 400 Mbps of data trans...

Page 20: ...O 27 30 GND GND 31 3V3 UART3_RXD gpio5 IO 26 32 PCIE1_TXP_C 33 GND GND 34 PCIE1_TXN_C 35 36 GND GND 37 3V3 UART3_CTS gpio5 IO 9 38 PCIE1_RXP_C 39 3V3 UART3_RTS gpio5 IO 10 40 PCIE1_RXN_C 41 3V3 SAI1_T...

Page 21: ...V3 SAI1_MCLK gpio4 IO 20 37 HDMI_CLKP 38 3V3 CLKO2 gpio1 IO 15 39 HDMI_CLKN 40 41 GND GND 42 GND GND 43 3V3 HDMI_CEC 44 Tanya gpio5 IO 21 45 5V HDMI_DDC_SCL 46 SAI1_RXD7 BT_CFG7 gpio4 IO 9 47 5V HDMI_...

Page 22: ..._CLK gpio2 IO 13 39 3V3 AUD_nMUTE gpio1 IO 8 40 3V3 SD2_CMD gpio2 IO 14 41 3V3 CLKO_25MHz gpio3 IO 11 42 3V3 SD2_DATA0 gpio2 IO 15 43 5V USB1_VBUS 44 3V3 SD2_DATA1 gpio2 IO 16 45 3V3 ECSPI2_MISO gpio5...

Page 23: ...tem and SOM power Power up sequence is supported by the PMIC configuration Reset The i MX8 POR signal is activated by the PMIC output The following figure describes the reset architecture C O SYS_RST...

Page 24: ...ng to the power sequence rules See IMX 8 datasheet for details Booting Options Fuses Booting The IMX 8 can boot from its internal fuses map Booting from the fuses is enabled when the BOOT_MODE 1 0 is...

Page 25: ...llowing table describes how the booting signals need to be set to support the different booting options Notes NAND booting is not an option on the IMX 8 SOM SPI NOR is an option on the carrier board N...

Page 26: ...O 5 Enable the WI FI RF Active High WL_nPERST gpio4 IO 21 Reset the WI FI module Active Low REF_CLK_32K gpio3 IO 3 32K clock for the WI FI module N I U UBLOX_RSTN gpio5 IO 1 Reset the BT module Active...

Page 27: ...WiFi and Ethernet is 1Gbps note 1 Android Nenamark2 benchmark TBD Performance governor HDMI is on usb sata wifi and Ethernet are off Full load Android Nenamark2 benchmark 4 processors running 100 dd...

Page 28: ...gram CuBox i design does not use the mechanical holes since the mating strength of two Hirose DF40 pairs and the internal heat spreader is satisfactory for the design requirements In case 1 5mm mating...

Page 29: ...29 Ordering Information Please refer to the SolidRun website for more information regarding part numbers and the procedure for placing an order http www solid run com...

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