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Ultra Fast USB 2.0 Memory Stick Flash Media Controller

Datasheet

SMSC USB2242/USB2242i

23

Revision 1.0 (05-27-08)

DATASHEET

Chapter 10 GPIO Usage

Table 10.1  USB2242/USB2242i GPIO Usage (ROM Rev 0x00)

NAME

ACTIVE LEVEL

SYMBOL

DESCRIPTION AND NOTE

GPIO1

H

LED1

LED indicator

GPIO2

H

RXD / SDA

Receive Port of Debugger / Serial 
EEPROM Data

GPIO4

USER

GPIO

User defined

GPIO7

H

TXD / SCK / MS_SKT_SEL

Transmit Port of Debugger / Serial 
EEPROM Clock / Memory Stick Socket 
(1 = 8 bit; 0 = 4 bit)

GPIO10

L

CRD_PWR

Card Power Control

GPIO12

L

MS_INS

Memory Stick Card Insertion

GPIO14

USER

GPIO

User defined

GPIO15

USER

GPIO

User defined

Summary of Contents for USB2242

Page 1: ...Memory Stick Pro HG Duo Format Specification 1 01 Memory Stick MS Duo HS MS MS Pro HG MS Pro Extended configuration options Socket switch polarities etc Media Activity LED GPIO configuration and pola...

Page 2: ...ctions to deviate from published specifications Anomaly sheets are available upon request SMSC products are not designed intended authorized or warranted for use in any life support or other applicati...

Page 3: ...4 Pin Configuration 9 Chapter 5 Pin Descriptions 10 5 1 Pin Descriptions 10 5 2 Buffer Type Descriptions 13 Chapter 6 Pin Reset State Table 14 6 1 36 Pin Reset States 15 Chapter 7 DC Parameters 16 7...

Page 4: ...USB2242 USB2242i Block Diagram 7 Figure 4 1 USB2242 USB2242i 36 Pin QFN Diagram 9 Figure 6 1 Pin Reset States 14 Figure 6 2 Legend for Pin Reset States Table 14 Figure 7 1 Supply Rise Time Model 17 F...

Page 5: ...DATASHEET List of Tables Table 3 1 USB2242 2242i 36 Pin QFN Package 8 Table 5 2 USB2242 2242i 36 Pin QFN Pin Descriptions 10 Table 5 3 USB2242 USB2242i Buffer Type Descriptions 13 Table 6 1 USB2242 US...

Page 6: ...costs or to pay damages shall not apply to any of the devices made the subject of this document or any software programs related to any of such devices or to any combinations involving any of them wi...

Page 7: ...2242 USB2242i Block Diagram SIE CTL FMDU CTL 8051 PROCESSOR SFR RAM RAM USB Host AUTO_ CBW PROC PHY FMI XDATA BRIDGE BUS ARBITER BUS INTFC BUS INTFC BUS INTFC EP0 TX EP0 RX EP2 TX EP2 RX EP1 RX EP1 TX...

Page 8: ...e 3 1 USB2242 2242i 36 Pin QFN Package MS INTERFACE 11 PINS MS_D0 MS_D1 MS_D2 MS_D3 MS_D4 MS_D5 MS_D6 MS_D7 MS_BS MS_SCLK GPIO12 MS_INS USB INTERFACE 7 PINS USB USB RBIAS XTAL1 CLKIN XTAL2 VDDA33 VDD1...

Page 9: ...MSC USB2242 2242i Top View QFN 36 Indicates pins on the bottom of the device 26 MS_D3 25 GPIO15 24 NC 23 GPIO12 MS_INS 22 VDD33 21 GPIO10 CRD_PWR 20 19 GPIO2 RXD SDA 27 18 17 16 15 14 13 12 11 10 28 2...

Page 10: ...Pin Descriptions NAME SYMBOL 36 PIN QFN BUFFER TYPE DESCRIPTION MEMORY STICK INTERFACE MS System Data In Out MS_D 7 0 8 7 4 5 23 20 10 11 I O12PD These pins are the bi directional data signals for th...

Page 11: ...VDD18PLL 34 This pin is the 1 8V Power for the PLL 1 8V Filtered analog power for internal PLL This pin must have a 1 0 F or greater 20 ESR 0 1 capacitor to VSS MISC General Purpose I O GPIO1 LED1 1...

Page 12: ...either 100mA or 200mA General Purpose I O GPIO14 19 I O12 This pin may be used either as input edge sensitive interrupt input or output General Purpose I O GPIO15 26 I O12 This pin may be used either...

Page 13: ...weak pull up resistor IS Input with Schmitt trigger I O12 Input Output buffer with 12mA sink and 12mA source I O200 Input Output buffer 12mA with FET disabled 100 200mA source only when the FET is en...

Page 14: ...v Time t RESET RESET Hardware Initialization Firmware Operational VDD33 VSS LEGEND yes hardware enables function hardware disables function z hardware disables output driver pu hardware enables pullu...

Page 15: ...z MS_D5 hw hw yes 30 MS_SCLK SD_WP 0 MS_SCLK hw hw 25 NC none z none z 23 MS_D3 none z MS_D3 hw pd yes 20 MS_D2 none z MS_D2 hw pd yes 9 MS_BS none z MS_BS hw hw 10 MS_D1 none z MS_D1 hw hw yes 11 MS_...

Page 16: ...bit voltage spikes on their outputs when the AC power is switched on or off In addition voltage transients on the AC power line may appear on the DC output When this possibility exists it is suggested...

Page 17: ...ust support a 5 tolerance PARAMETER SYMBOL MIN MAX UNITS COMMENTS Operating Temperature Commercial Part Industrial Part TA TA 0 40 70 85 C C 3 3V supply voltage VDD33 VDDA33 3 0 3 6 V Note 7 3 3 3V su...

Page 18: ...TTL Levels IS Type Input Buffer Low Input Level High Input Level Hysteresis VILI VIHI VHYSI 2 0 420 0 8 V V mV TTL Levels ICLK Input Buffer Low Input Level High Input Level Input Leakage VILCK VIHCK I...

Page 19: ...board implementation Firmware will default to I O12 I O12PU I O12PD Type Buffer Low Output Level High Output Level Output Leakage Pull Down Pull Up VOL VOH IOL PD PU VDD33 0 4 10 72 58 0 4 10 V V A A...

Page 20: ...ote 7 9 The 3 3V supply should be at least at 75 of its operating condition before the 1 8V supply is allowed to ramp up 7 4 Capacitance TA 25 C fc 1MHz VDD VDDP 1 8V Table 7 1 Pin Capacitance PARAMET...

Page 21: ...scillator Clock Crystal Parallel Resonant Fundamental Mode 24 MHz 100ppm External Clock 50 Duty cycle 10 24 MHz 100ppm Jitter 100ps rms Figure 8 1 Typical Crystal Circuit Note CB equals total board tr...

Page 22: ...ra Fast USB 2 0 Memory Stick Flash Media Controller Datasheet Revision 1 0 05 27 08 22 SMSC USB2242 USB2242i DATASHEET Chapter 9 Package Outline Figure 9 1 USB2242 USB2242i 36 QFN 6x6mm Body 0 5mm Pit...

Page 23: ...TIVE LEVEL SYMBOL DESCRIPTION AND NOTE GPIO1 H LED1 LED indicator GPIO2 H RXD SDA Receive Port of Debugger Serial EEPROM Data GPIO4 USER GPIO User defined GPIO7 H TXD SCK MS_SKT_SEL Transmit Port of D...

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