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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

Revision 1.4 (08-19-08)

220

SMSC LAN9311/LAN9311i

DATASHEET

14.2.5.19

1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO)

This read/write register combined with

1588 Clock Target Reload High-DWORD Register

(1588_CLOCK_TARGET_RELOAD_HI)

form the 64-bit 1588 Clock Target Reload value. The 1588

Clock Target Reload is the value that is reloaded or added to the 1588 Clock Compare value when a
clock compare event occurs. Whether this value is reloaded or added is determined by the

bit of the

1588 Configuration Register (1588_CONFIG)

. Refer to

Chapter 11, "IEEE

1588 Hardware Time Stamp Unit," on page 155

for additional information.

Note:

Both this register and the

1588 Clock Target Reload High-DWORD Register

(1588_CLOCK_TARGET_RELOAD_HI)

must be written for either to be affected.

Offset:

188h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Clock Target Reload Low (CLOCK_TARGET_RELOAD_LO)

This field contains the low 32-bits of the 64-bit 1588 Clock Target Reload
value that is reloaded to the 1588 Clock Compare value. Alternatively, these
32-bits are added to the 1588 Clock Compare value when configured
accordingly.

R/W

00000000h

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Summary of Contents for LAN9311

Page 1: ...s Switch Management Port mirroring monitoring sniffing ingress and or egress traffic on any ports or port pairs Fully compliant statistics MIB gathering counters Control registers configurable on the...

Page 2: ...the date of your order the Terms of Sale Agreement The product may contain design defects or errors known as anomalies which may cause the product s functions to deviate from published specifications...

Page 3: ...QFP Pin Diagram 26 3 1 2 128 XVTQFP Pin Diagram 27 3 2 Pin Descriptions 28 Chapter 4 Clocking Resets and Power Management 36 4 1 Clocks 36 4 2 Resets 36 4 2 1 Chip Level Resets 37 4 2 1 1 Power On Res...

Page 4: ...4 3 1 Port Default Priority 69 6 4 3 2 IP Precedence Based Priority 69 6 4 3 3 DIFFSERV Based Priority 69 6 4 3 4 VLAN Priority 69 6 4 4 VLAN Support 70 6 4 5 Spanning Tree Support 70 6 4 6 Ingress Fl...

Page 5: ...own 95 7 2 10 PHY Resets 95 7 2 10 1 PHY Software Reset via RESET_CTL 95 7 2 10 2 PHY Software Reset via PHY_BASIC_CTRL_x 96 7 2 10 3 PHY Power Down Reset 96 7 2 11 LEDs 96 7 2 12 Required Ethernet Ma...

Page 6: ...se TX MIL FIFO Usage 128 9 8 4 TX Status Format 128 9 8 5 Calculating Actual TX Data FIFO Usage 129 9 8 6 Transmit Examples 129 9 8 6 1 TX Example 1 129 9 8 6 2 TX Example 2 131 9 8 7 Transmitter Erro...

Page 7: ...apter 13 GPIO LED Controller 163 13 1 Functional Overview 163 13 2 GPIO Operation 163 13 2 1 GPIO IEEE 1588 Timestamping 164 13 2 1 1 IEEE 1588 GPIO Inputs 164 13 2 1 2 IEEE 1588 GPIO Outputs 164 13 2...

Page 8: ...ister 1588_AUX_MAC_LO 222 14 2 5 22 1588 Configuration Register 1588_CONFIG 223 14 2 5 23 1588 Interrupt Status and Enable Register 1588_INT_STS_EN 227 14 2 5 24 1588 Command Register 1588_CMD 229 14...

Page 9: ...t x MAC Receive Broadcast Count Register MAC_RX_BRDCST_CNT_x 337 14 5 2 15 Port x MAC Receive Pause Frame Count Register MAC_RX_PAUSE_CNT_x 338 14 5 2 16 Port x MAC Receive Fragment Error Count Regist...

Page 10: ...ine Port 2 Learn Discard Count Register SWE_LRN_DISCRD_CNT_2 409 14 5 3 39 Switch Engine Interrupt Mask Register SWE_IMR 410 14 5 3 40 Switch Engine Interrupt Pending Register SWE_IPR 411 14 5 4 Buffe...

Page 11: ...EET 15 5 7 RX Data FIFO Direct PIO Burst Read Cycle Timing 451 15 5 8 PIO Write Cycle Timing 452 15 5 9 TX Data FIFO Direct PIO Write Cycle Timing 453 15 5 10 Microwire Timing 454 15 6 Clock Circuit 4...

Page 12: ...8 2 Big Endian Byte Ordering 101 Figure 8 3 Functional Timing for PIO Read Operation 107 Figure 8 4 Functional Timing for PIO Burst Read Operation 108 Figure 8 5 Functional Timing for RX Data FIFO Dir...

Page 13: ...ycle Timing 448 Figure 15 5 PIO Burst Read Cycle Timing 449 Figure 15 6 RX Data FIFO Direct PIO Read Cycle Timing 450 Figure 15 7 RX Data FIFO Direct PIO Burst Read Cycle Timing 451 Figure 15 8 PIO Wr...

Page 14: ...2 Read After Read Timing Rules 106 Table 9 1 Address Filtering Modes 116 Table 9 2 Wake Up Frame Filter Register Structure 118 Table 9 3 Filter i Byte Mask Bit Definitions 118 Table 9 4 Filter i Comm...

Page 15: ...13Metering Color Table Register Descriptions 397 Table 15 1 Supply and Current 10BASE T Full Duplex 443 Table 15 2 Supply and Current 100BASE TX Full Duplex 443 Table 15 3 I O Buffer Characteristics 4...

Page 16: ...d of an Ethernet frame used for error detection and correction FIFO First In First Out buffer FSM Finite State Machine GPIO General Purpose I O HBI Host Bus Interface The physical bus connecting the L...

Page 17: ...ique Identifier Outbound Refers to data output from the LAN9311 LAN9311i to the host PIO cycle Program I O cycle An SRAM like read or write cycle on the HBI PISO Parallel In Serial Out PLL Phase Locke...

Page 18: ...description internal pull ups are always enabled Note Internal pull up resistors prevent unconnected inputs from floating Do not rely on internal resistors to drive signals external to the LAN9311 LA...

Page 19: ...effect WAC Write Anything to Clear writing anything clears the value RC Read to Clear Contents is cleared after the read Writes have no effect LL Latch Low Clear on read of register LH Latch High Cle...

Page 20: ...AN9311i switch fabric to the host bus interface All ports support automatic or manual full duplex flow control or half duplex backpressure forced collision flow control Automatic 32 bit CRC generation...

Page 21: ...Registers 10 100 PHY Registers Switch Registers CSRs IEEE 1588 Time Stamp IEEE 1588 Time Stamp Switch Fabric GPIO LED Controller Dynamic QoS 4 Queues Dynamic QoS 4 Queues Dynamic QoS 4 Queues Switch E...

Page 22: ...r Reset bit 15 in the Port x PHY Basic Control Register PHY_BASIC_CONTROL_x Resets the Port 2 PHY Port 1 PHY Reset PHY1_RST bit 1 in the Reset Control Register RESET_CTL or Reset bit 15 in the Port x...

Page 23: ...ng of the switch fabric 32K of buffer RAM allows for the storage of multiple packets while forwarding operations are completed Each port is allocated 1a cluster of 4 dynamic QoS queues which allow eac...

Page 24: ...h the system register bus and the EEPROM Loader Multiple types I2C Microwire and sizes of external EEPROMs are supported Configuration of the EEPROM type and size are accomplished via the eeprom_type_...

Page 25: ...is connected to the host microprocessor microcontroller via the asynchronous 16 bit interface allowing access to the LAN9311 LAN9311i system configuration and status registers The LAN9311 LAN9311i uti...

Page 26: ...D4 VDD33IO D6 D5 D8 D7 VDD33IO EEDI EE_SDA NC NC nP1LED0 GPIO0 VDD33IO nP1LED2 GPIO2 nP1LED1 GPIO1 VDD18CORE nP1LED3 GPIO3 nP2LED0 GPIO4 VDD33IO nP2LED2 GPIO6 nP2LED1 GPIO5 GPIO8 nP2LED3 GPIO7 VSS VD...

Page 27: ...D1 VDD18CORE D3 D4 VDD33IO D6 D5 D8 D7 VDD33IO EEDI EE_SDA NC NC nP1LED0 GPIO0 VDD33IO nP1LED2 GPIO2 nP1LED1 GPIO1 VDD18CORE nP1LED3 GPIO3 nP2LED0 GPIO4 VDD33IO nP2LED2 GPIO6 nP2LED1 GPIO5 GPIO8 nP2LE...

Page 28: ...9 8 bits General Purpose I O Data GPIO 3 0 IS O12 OD12 PU General Purpose I O Data When configured as GPIO via the LED Configuration Register LED_CFG these general purpose signals are fully programmab...

Page 29: ...sh pull outputs open drain outputs or Schmitt triggered inputs by writing the General Purpose I O Configuration Register GPIO_CFG and General Purpose I O Data Direction Register GPIO_DATA_DIR The pull...

Page 30: ...This pin must be connected directly to the VDD18TX2 pin for proper operation Refer to the LAN9311 LAN9311i application note for additional connection information Table 3 4 Host Bus Interface Pins PIN...

Page 31: ...EEPROM mode EEPROM_TYPE 0 this pin is the Microwire EEPROM serial data input EEPROM I2C Serial Data Input Output EE_SDA IS OD8 EEPROM I2 C Serial Data Input Output EE_SDA In I2C EEPROM mode EEPROM_TY...

Page 32: ...ote In I2C mode EEPROM_TYPE 1 this pin is not used and is driven low EEPROM Size Strap 0 EEPROM_SIZE_0 IS Note 3 3 EEPROM Size Strap 0 Configures the low bit of the EEPROM size range as specified in S...

Page 33: ...D12 O12 PU Note 3 7 General Purpose I O Data These general purpose signals are fully programmable as either push pull outputs open drain outputs or Schmitt triggered inputs by writing the General Purp...

Page 34: ...wer Supply This pin must be connected to VDD18CORE for proper operation Refer to the LAN9311 LAN9311i application note for additional connection information 105 Crystal Input XI ICLK Crystal Input Ext...

Page 35: ...P package only 18 48 80 97 112 113 128 Note 3 8 Common Ground VSS P Common Ground Table 3 10 No Connect Pins PIN NAME SYMBOL BUFFER TYPE DESCRIPTION 1 2 4 6 8 12 15 17 19 20 22 24 76 94 95 102 103 109...

Page 36: ...162 for additional details Note Crystal specifications are provided in Table 15 15 LAN9311 LAN9311iCrystal Specifications on page 455 4 2 Resets The LAN9311 LAN9311i provides multiple hardware and so...

Page 37: ...eption of the Hardware Configuration Register HW_CFG Power Management Control Register PMT_CTRL Byte Order Test Register BYTE_TEST and Reset Control Register RESET_CTL read access to any internal reso...

Page 38: ...e entire chip Configuration straps are not latched upon multi module resets A multi module reset is initiated by assertion of the following Digital Reset DIGITAL_RST Soft Reset SRST Chip level reset c...

Page 39: ...m a PHY power down mode This reset differs in that the PHY power down mode reset does not reload or reset any of the PHY registers Refer to Section 7 2 9 PHY Power Down Modes on page 94 for additional...

Page 40: ...n unconnected If a particular configuration strap is connected to a load an external pull up or pull down resistor should be used to augment the internal resistor to ensure that it reaches the require...

Page 41: ...bit in the Port x PHY Special Control Status Indication Register PHY_SPECIAL_CONTROL_STAT_IND_x is cleared When configured low Auto MDIX is disabled When configured high Auto MDIX is enabled Note If...

Page 42: ...ected This strap also affects the default value of the following bits PHY_DUPLEX bit of the Port x PHY Basic Control Register PHY_BASIC_CONTROL_x 10BASE T Full Duplex bit 6 of the Port x PHY Auto Nego...

Page 43: ...PECIAL_CONTROL_STAT_IND_x is cleared When configured low Auto MDIX is disabled When configured high Auto MDIX is enabled Note If AMDIXCTL is set this strap had no effect AUTO_MDIX_2 manual_mdix_strap_...

Page 44: ...ected This strap also affects the default value of the following bits PHY_DUPLEX bit of the Port x PHY Basic Control Register PHY_BASIC_CONTROL_x 10BASE T Full Duplex bit 6 of the Port x PHY Auto Nego...

Page 45: ...0 Host MAC Backpressure Enable Strap Configures the default value for the Port 0 Backpressure Enable BP_EN_MII bit of the Port 0 Host MAC Manual Flow Control Register MANUAL_FC_MII When configured low...

Page 46: ...he results together to generate the PME_INT status bit in the Interrupt Status Register INT_STS The PME_INT status bit is then masked with the PME_EN bit and conditioned before becoming the PME output...

Page 47: ...the IRQ interrupt output pin as described in Section 5 2 3 Ethernet PHY Interrupts on page 52 Refer to Section 7 2 9 2 PHY Energy Detect Power Down on page 95 for details on the operation and configur...

Page 48: ...WUEN bit for wake up frames and the MPEN bit for magic packets detection of wake up frames or magic packets causes the WUFR and MPR bits of the HMAC_WUCSR register to set respectively If either of th...

Page 49: ...e Register INT_EN and Interrupt Configuration Register IRQ_CFG The Interrupt Status Register INT_STS and Interrupt Enable Register INT_EN aggregate and enable disable all interrupts from the various L...

Page 50: ...of INT_STS register PHY_INTERRUPT_SOURCE_1 PHY_INTERRUPT_MASK_1 Port 1 PHY Interrupt Registers Bit 26 PHY_INT1 of INT_STS register SW_IMR SW_IPR Switch Fabric Interrupt Registers Bit 28 SWITCH_INT of...

Page 51: ...nt occurred in the Switch Engine Interrupt Pending Register SWE_IPR In turn the Switch Engine Interrupt Pending Register SWE_IPR and Switch Engine Interrupt Mask Register SWE_IMR provide status and en...

Page 52: ...N must be set and IRQ output must be enabled via bit 8 IRQ_EN of the Interrupt Configuration Register IRQ_CFG For additional details on the Ethernet PHY interrupts refer to Section 7 2 8 1 PHY Interru...

Page 53: ...t conditions These include energy detect on the Port 1 2 PHYs and Wake On LAN wake up frame or magic packet detection by the Host MAC In order for a Power Management interrupt event to trigger the ext...

Page 54: ...o generate an interrupt and is designed for general software usage 5 2 9 Device Ready Interrupt A device ready interrupt is provided in the top level Interrupt Status Register INT_STS and Interrupt En...

Page 55: ...fabric which provide basic 10 100 Ethernet functionality for each switch fabric port Switch Engine SWE This block is the core of the switch fabric and provides VLAN layer 2 switching for all three sw...

Page 56: ...by writing the desired data into the Switch Fabric CSR Interface Data Register SWITCH_CSR_DATA The completion of the write cycle is indicated by the clearing of the CSR_BUSY bit at which time the add...

Page 57: ...crement AUTO_DEC bit set the CSR_ADDRESS field written with the desired register address and the R_nW bit set The completion of a read cycle is indicated by the clearing of the CSR_BUSY bit at which t...

Page 58: ...al Flow Control Register MANUAL_FC_2 or Port 0 Host MAC Manual Flow Control Register MANUAL_FC_MII Table 6 1 details the switch fabric flow control enable logic When in half duplex mode the transmit f...

Page 59: ...ation Advertisement Register PHY_AN_ADV_x and Port x PHY Auto Negotiation Link Partner Base Page Ability Register PHY_AN_LP_BASE_ABILITY_x For the Virtual PHY these are the local partner swapped outpu...

Page 60: ...limiter SFD The receive MAC checks the FCS the MAC Control Type and the byte count against the drop conditions The packet is stored in the RX FIFO as it is received The receive MAC determines the vali...

Page 61: ...ectly Accessible Switch Control and Status Registers on page 309 and Section 14 5 2 3 through Section 14 5 2 22 for detailed descriptions of these counters Total undersized packets Section 14 5 2 3 on...

Page 62: ...The FIFO logic manages the re transmission for normal collision conditions or discards the frames for late or excessive collisions When in full duplex mode the transmit MAC uses the flow control algo...

Page 63: ...ides packet metering for input rate control It also implements port mirroring broadcast throttling and multicast pruning and filtering Packet priorities are supported based on the IPv4 TOS bits and IP...

Page 64: ...cast Pruning The destination port that is returned as a result of a destination MAC address lookup may be a single port or any combination of ports The latter is used to setup multicast address groups...

Page 65: ...d Data 0 Register SWE_ALR_RD_DAT_0 and Switch Engine ALR Read Data 1 Register SWE_ALR_RD_DAT_1 Note The entries read are not necessarily in the same order as they were learned or manually added The fo...

Page 66: ...on Red is set and the packet is colored Red it is discarded If the destination address was not found in the ALR table an unknown or a broadcast and the Broadcast Buffer Level is exceeded the packet is...

Page 67: ...ity Regeneration table the port default The last four options listed are sent through the Traffic Class table which maps the selected priority to one of the four output queues The static value from th...

Page 68: ...configuration bits Figure 6 5 Switch Engine Transmit Queue Calculation Queue ALR Priority DA Highest Priority ALR Static Bit Y Y Resolved Priority Priority Regen VLAN Priority N Packet is IPv4 v6 Use...

Page 69: ...IPv4 TOS octet or the IPv6 Traffic Class octet and is used as an index into the DIFFSERV table The output of the DIFFSERV table is then used as the priority This priority is then passed through the T...

Page 70: ...ions are used at egress on ports defined as hybrid ports Refer to Section 14 5 3 8 on page 377 through Section 14 5 3 11 on page 380 for detailed VLAN register descriptions 6 4 5 Spanning Tree Support...

Page 71: ...ream First the Committed Burst bucket is incremented up to the maximum set by the CBS Once the Committed Burst bucket is full the Excess Burst bucket is incremented up to the maximum set by the EBS Th...

Page 72: ...the maximum value of the token buckets Refer to Section 14 5 3 25 on page 395 through Section 14 5 3 29 on page 400 for detailed register descriptions 6 4 6 1 Ingress Flow Calculation Based on the fl...

Page 73: ...fault Table 3b 3b 2b 6b 3b Packet is Tagged VL Higher Priority Packet is IPv4 Packet is IP Use Precedence Use IP IPv4 TOS IPv6 TC flow priority Source Port VLAN Priority IPv4 Precedence 3b 3b VLAN Ena...

Page 74: ...nabled in the Switch Engine Global Ingress Configuration Register SWE_GLOBAL_INGRSS_CFG IGMP multicast packets are trapped and redirected to the MLD IGMP snoop port typically set to the port to which...

Page 75: ...t 1 it is forwarded to both Port 1 and Port 0 When transmit mirroring is enabled packets that are forwarded to a port designated as a mirrored port are also transmitted by the sniffer port For example...

Page 76: ...le for a normally tagged maximum size incoming packet to become 1526 bytes in length In order for the Host MAC to receive this length packet without indicating a length error the Host MAC VLAN2 Tag Re...

Page 77: ...ister BM_BCST_LVL and if the configured drop level is reached or exceeded subsequent packets are dropped 6 5 2 Random Early Discard RED Based on the ingress flow monitoring detailed in Section 6 4 6 I...

Page 78: ...limiting occurs before the Transmit Priority Queue Servicing such that a lower priority queue will be serviced if a higher priority queue is being rate limited The egress limiting is enabled per prior...

Page 79: ...ress port number The entry in the VLAN table is either the VLAN from the received packet or the ingress ports default VID When a received packet is non tagged a new VLAN tag is added if two conditions...

Page 80: ...t Y Non tagged Y Add Tag VID Default VID ingress_port Priority Default Priority ingress_port Y Send Packet Untouched N Priority Tagged Default VID ingress_port Un tag Bit Y Strip Tag N Normal Tagged R...

Page 81: ...that contains the number of packets dropped due solely to ingress rate limit discarding Red and random Yellow dropping This count value can be subtracted from the drop counter as described above to o...

Page 82: ...and can be configured indirectly via the Host MAC or directly via the memory mapped Virtual PHY registers Refer to Section 14 4 Ethernet PHY Control and Status Registers for details on the Ethernet PH...

Page 83: ...Wherever a lowercase x has been appended to a port or signal name it can be replaced with 1 or 2 to indicate the Port 1 or Port 2 PHY respectively All references to PHY in this section can be used in...

Page 84: ...it data passes from the MII block to the 4B 5B Encoder This block encodes the data from 4 bit nibbles to 5 bit symbols known as code groups according to Table 7 2 Each 4 bit data nibble is mapped to 1...

Page 85: ...I Receive Error RXER Sent for rising MII Transmitter Enable signal TXEN 10001 K Second nibble of SSD translated to 0101 following J else MII Receive Error RXER Sent for rising MII Transmitter Enable s...

Page 86: ...presents a code bit 0 7 2 1 5 100M Transmit Driver The MLT 3 data is then passed to the analog transmitter which drives the differential MLT 3 signal on output pins TXPx and TXNx where x is replaced w...

Page 87: ...used by the physical channel magnetics connectors and CAT 5 cable The equalizer can restore the signal for any good quality CAT 5 cable between 1m and 150m If the DC content of the signal is such that...

Page 88: ...t data nibbles according to the 4B 5B table shown in Table 7 2 The translated data is presented on the internal MII RXD 3 0 signal lines to the switch fabric MAC The SSD J K is translated to 0101 0101...

Page 89: ...rtner The manchester encoded data is sent to the analog transmitter where it is shaped and filtered before being driven out as a differential signal across the TXPx and TXNx outputs where x is replace...

Page 90: ...ng configuration information between two link partners and automatically selecting the highest performance mode of operation supported by both sides Auto negotiation is fully defined in clause 28 of t...

Page 91: ...d by an FLP burst is known as a Link Code Word These are defined fully in IEEE 802 3 clause 28 In summary the PHY advertises 802 3 compliance in its selector field the first 5 bits of the Link Code Wo...

Page 92: ...gacy link partners If a link is formed via parallel detection then bit 0 in the Port x PHY Auto Negotiation Expansion Register PHY_AN_EXP_x is cleared to indicate that the link partner is not capable...

Page 93: ...ign The Auto MDIX function can be disabled through bit 15 AMDIXCTRL of the Port x PHY Special Control Status Indication Register PHY_SPECIAL_CONTROL_STAT_IND_x When AMDIXCTRL is cleared Auto MDIX can...

Page 94: ...ers Refer to Section 14 4 2 Port 1 2 PHY Registers on page 287 for a list of all supported registers and register descriptions Non supported registers will be read as FFFFh 7 2 8 1 PHY Interrupts The...

Page 95: ...erts the INT7 interrupt bit 7 of the Port x PHY Interrupt Source Flags Register PHY_INTERRUPT_SOURCE_x The first and possibly second packet to activate ENERGYON may be lost When bit 13 EDPWRDOWN of th...

Page 96: ...nterface MDIO to the Host MAC per the IEEE 802 3 clause 22 so that an unmodified driver can be supported as if the Host MAC was attached to a single port PHY This functionality is designed to allow ea...

Page 97: ...ation process is re run The emulated link partner always advertises all four abilities 100BASE X full duplex 100BASE X half duplex 10BASE T full duplex and 10BASE T half duplex in the Virtual PHY Auto...

Page 98: ...settings may also be manually set via the Port 0 Host MAC Manual Flow Control Register MANUAL_FC_MII This register allows the switch fabric port 0 flow control settings to be manually set when auto n...

Page 99: ...rs are accessible to the host via the Host Bus Interface and allow direct and indirect access to all the LAN9311 LAN9311i functions For a full list of all System CSR s and their descriptions refer to...

Page 100: ...er this is not a fatal error The LAN9311 LAN9311i will reset its read counters and restart a new cycle on the next read Note Some registers are readable as 16 bit registers In this case if desired onl...

Page 101: ...ATASHEET Figure 8 1 Little Endian Byte Ordering Figure 8 2 Big Endian Byte Ordering 16 BIT LITTLE ENDIAN END_SEL 0 0 1 2 3 0 1 2 3 0 7 8 15 0 7 8 15 16 23 31 24 A 1 0 A 1 1 MSB LSB HOST DATA BUS INTER...

Page 102: ...ack Write Read Cycles It is important to note that there are specific restrictions on the timing of back to back host write read operations These restrictions concern reading the host control register...

Page 103: ...tatus FIFO PEEK 0 0 TX Status FIFO 0 0 TX Status FIFO PEEK 0 0 ID_REV 0 0 IRQ_CFG 135 3 INT_STS 90 2 INT_EN 45 1 BYTE_TEST 0 0 FIFO_INT 45 1 RX_CFG 45 1 TX_CFG 45 1 HW_CFG 45 1 RX_DP_CTRL 45 1 RX_FIFO...

Page 104: ...0 0 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_MII 0 0 1588_SRC_UUID_LO_RX_CAPTURE_MII 0 0 1588_CLOCK_HI_TX_CAPTURE_MII 0 0 1588_CLOCK_LO_TX_CAPTURE_MII 0 0 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_MII 0 0 1588_SR...

Page 105: ...LED_CFG 45 1 VPHY_BASIC_CTRL 45 1 VPHY_BASIC_STATUS 45 1 VPHY_ID_MSB 45 1 VPHY_ID_LSB 45 1 VPHY_AN_ADV 45 1 VPHY_AN_LP_BASE_ABILITY 45 1 VPHY_AN_EXP 45 1 VPHY_SPECIAL_CONTROL_STATUS 45 1 GPIO_CFG 45...

Page 106: ...being read Performing dummy reads of the Byte Order Test Register BYTE_TEST register is a convenient way to guarantee that the minimum wait time restriction is met Table 8 2 below also shows the numb...

Page 107: ...iming Values on page 448 The cycle ends when either or both nCS and nRD are de asserted They may be asserted and de asserted in any order Read data is valid as indicated in the functional timing diagr...

Page 108: ...en either or both nCS and nRD are de asserted They may be asserted and de asserted in any order Read data is valid as indicated in the functional timing diagram in Figure 8 4 Note A 1 must toggle duri...

Page 109: ...ess lines An RX Data FIFO direct PIO read cycle begins when both nCS and nRD are asserted Either or both of these control signals must de assert between cycles for the period specified in Table 15 10...

Page 110: ...read cycles RX Data FIFO direct PIO burst reads can be performed using chip select nCS or read enable nRD An RX Data FIFO direct PIO burst read begins when both nCS and nRD are asserted Either or bot...

Page 111: ...must de assert between cycles for the period specified in Table 15 12 PIO Write Cycle Timing Values on page 452 They may be asserted and de asserted in any order Either or both of these control signal...

Page 112: ...The TX Data FIFO direct PIO write cycle is illustrated in the functional timing diagram in Figure 8 8 Note Address lines A 2 1 are still used and address lines A 9 3 are ignored Please refer to Secti...

Page 113: ...Management Interface bus This allows the Host MAC access to the PHY s internal registers via the Host MAC MII Access Register HMAC_MII_ACC and Host MAC MII Data Register HMAC_MII_DATA The Host MAC int...

Page 114: ...of the control frame is not affected by the current state of the Pause timer value that may be set due to a recently received control frame 9 2 2 Half Duplex Flow Control Backpressure In half duplex...

Page 115: ...se refer to the Section 14 3 1 Host MAC Control Register HMAC_CR on page 272 for more information on this register If the frame fails the filter the Host MAC does not receive the packet The host has t...

Page 116: ...H or HMAC_HASHL while the other five bits determine the bit within the register A value of 00000 selects Bit 0 of the HMAC_HASHL register and a value of 11111 selects Bit 31 of the HMAC_HASHH register...

Page 117: ...are reset or soft reset the Host MAC loads the first value written to the HMAC_WUFF register to the first DWORD in the wake up frame filter filter 0 byte mask The second value written to this register...

Page 118: ...lter 1 Command Reserved Filter 0 Command Filter 3 Offset Filter 2 Offset Filter 1Offset Filter 0 Offset Filter 1 CRC 16 Filter 0 CRC 16 Filter 3 CRC 16 Filter 2 CRC 16 Table 9 3 Filter i Byte Mask Bit...

Page 119: ...agic Packet requirements Once the address requirement has been met the Host MAC checks the received frame for the pattern 48 hFF_FF_FF_FF_FF_FF after the destination and source address field The Host...

Page 120: ...icast qualification is also loaded into the Switch Fabric MAC address registers for pause packet flow control Switch Fabric MAC Address Low Register SWITCH_MAC_ADDRL and Switch Fabric MAC Address High...

Page 121: ...port locations as they all function identically and contain the same data This alias port addressing is implemented to allow hosts to burst through sequential addresses The TX and RX Status FIFOs can...

Page 122: ...ld in the Hardware Configuration Register HW_CFG The TX_FIF_SZ field selects the total allocation for the TX data path including the TX Status FIFO size The TX Status FIFO size is fixed at 512 Bytes 1...

Page 123: ...field can be used by the LAN software driver for any application Packet Tags is only one application example The Packet Length field in the TX command specifies the number of bytes in the associated p...

Page 124: ...the buffer has been fully loaded into the TX FIFO contained in the LAN9311 LAN9311i and transmitted This feature is enabled through the TX command Interrupt on Completion field Upon completion of tra...

Page 125: ...This must be taken into account when calculating the actual TX Data FIFO usage Please refer to Section 9 8 5 Calculating Actual TX Data FIFO Usage for a detailed explanation on calculating the actual...

Page 126: ...arantee future compatibility 20 16 Data Start Offset bytes This field specifies the offset of the first byte of TX data The offset value can be anywhere from 0 bytes to a 31 byte offset 15 14 Reserved...

Page 127: ...fers i e those with First Segment Last Segment 0 must be greater than or equal to 4 bytes in length The final buffer of any transmit packet can be any length The MIL operates in store and forward mode...

Page 128: ...ach packet transmitted Data transmission is suspended if the TX Status FIFO becomes full Data transmission will resume when the host reads the TX status and there is room in the FIFO for more TX Statu...

Page 129: ...ill be transmitted This packet is divided into three buffers The three buffers are as follows Buffer 0 7 Byte Data Start Offset 79 Bytes of payload data 16 Byte Buffer End Alignment Buffer 1 0 Byte Da...

Page 130: ...ommand A 0 31 TX Command B 10 Byte End Offset Padding 15 Byte Payload Buffer End Alignment 1 Data Start Offset 0 First Segment 0 Last Segment 0 Buffer Size 15 Packet Length 111 TX Command A 0 31 TX Co...

Page 131: ...his example and also shows how data is passed to the TX Data FIFO Note that the packet resides in a single TX Buffer therefore both the FS and LS bits are set in TX command A Figure 9 6 TX Example 2 T...

Page 132: ...controller will assert the Transmitter Error TXE flag Host overrun of the TX Data FIFO Overrun of the TX Status FIFO unless TXSAO is enabled 9 8 8 Stopping and Starting the Transmitter To halt the tra...

Page 133: ...vent that the end of the packet does not align with the host burst boundary This feature is necessary when the LAN9311 LAN9311i is operating in a system that always performs multi DWORD bursts In such...

Page 134: ...LAN9311 LAN9311i DATASHEET Figure 9 7 Host Receive Routine Using Interrupts Figure 9 8 Host Receive Routine Using Polling Not Last Packet Idle Read RX Status DWORD init Read RX Packet Last Packet RX...

Page 135: ...a fast forward operation 9 9 1 2 Force Receiver Discard Receiver Dump In addition to the Receive data Fast Forward feature LAN9311 LAN9311i also implements a receiver dump feature This feature allows...

Page 136: ...t indicates that the frame length exceeds the maximum Ethernet specification of 1518 bytes This is only a frame too long indication and will not cause the frame reception to be truncated 6 Collision S...

Page 137: ...errupt Status Register INT_STS Once stopped the host can optionally clear the RX Status and RX Data FIFOs The host must re enable the receiver by setting the RXEN bit 9 9 5 Receiver Errors If the Rece...

Page 138: ...10 2 I2C Microwire Master EEPROM Controller Based on the configuration strap eeprom_type_strap the I2C Microwire EEPROM controller supports either Microwire or I2C compatible EEPROMs The I2C Microwir...

Page 139: ...he operation is a WRITE the EPC_ADDRESS field in the EEPROM Command Register E2P_CMD must also be set to the desired location The command is executed when the EPC_BUSY bit of the EEPROM Command Regist...

Page 140: ...also expired the clock will rise and the cycle will continue In the event that the slave device holds the clock low for more than 30mS the current command sequence is aborted and the EPC_TIMEOUT bit...

Page 141: ...while EE_SCL is high The bus is considered to be busy following a start condition and is considered free 4 7uS 1 3uS for 100KHz and 400KHz operation respectively following a stop condition The bus sta...

Page 142: ...de is 1010b For single byte addressing EEPROMs the chip block select bits are used for address bits 10 9 and 8 For double byte addressing EEPROMs the chip block select bits are set low The direction b...

Page 143: ...nowledge followed by 8 bits of data If the EEPROM slave fails to send an acknowledge then the sequence is aborted and the EPC_TIMEOUT bit in the EEPROM Command Register E2P_CMD is set The I2C master t...

Page 144: ...ROM to determine when the byte write is finished A start condition is sent followed by a control byte with a control code of 1010b chip block select bits low and the R W bit low If the EEPROM is finis...

Page 145: ...detail the Microwire command set including the number of clock cycles required for 7 9 and 11 address bits respectively These commands are detailed in the following sections as well as in Section 14...

Page 146: ...A4 A3 A2 A1 A0 D7 D0 RDY BSY 20 WRAL 1 00 0 1 X X X X X X X D7 D0 RDY BSY 20 Table 10 6 Microwire Command Set for 11 Address Bits INST START BIT OPCODE ADDRESS DATA TO EEPROM DATA FROM EEPROM OF CLOC...

Page 147: ...a bulk erase of the entire EEPROM The EPC_TIMEOUT bit of the EEPROM Command Register E2P_CMD is set if the EEPROM does not respond within 30mS 10 2 3 4 EWDS Erase Write Disable After this command is...

Page 148: ...until power is cycled Note The EEPROM will power up in the erase write disabled state Any erase or write operations will fail until an EWEN command is issued 10 2 3 6 READ Read Location This command...

Page 149: ...ROM Command Register E2P_CMD The EPC_TIMEOUT bit of the EEPROM Command Register E2P_CMD is set if the EEPROM does not respond within 30mS 10 2 3 8 WRAL Write All If erase write operations are enabled...

Page 150: ...ection of EEPROM contents is discussed in detail in the following sections 10 2 4 1 EEPROM Loader Operation Upon a pin reset nRST power on reset POR digital reset DIGITAL_RST bit in the Reset Control...

Page 151: ...AC and switch MAC Address Registers Read Byte 7 11 Byte 7 A5h Y Write Bytes 8 11 into Configuration Strap registers Update PHY registers Update VPHY registers Update LED_CFG MANUAL_FC_1 MANUAL_FC_2 an...

Page 152: ...r HMAC_ADDRL During this time the EPC_BUSY bit in the EEPROM Command Register E2P_CMD is set Note The switch MAC address registers are not reloaded due to this condition 10 2 4 4 Soft Straps The 7th b...

Page 153: ...e new defaults as detailed in Section 14 2 8 8 Virtual PHY Special Control Status Register VPHY_SPECIAL_CONTROL_STATUS on page 258 The Virtual PHY Basic Control Register VPHY_BASIC_CTRL is written wit...

Page 154: ...Register PMI_ACCESS are cleared before performing any register write The EEPROM Loader checks that the EEPROM address space is not exceeded If so it will stop and set the EEPROM Loader Address Overfl...

Page 155: ...ocol PTP used by master and slave clock devices to pass time information in order to achieve clock synchronization Five network message types are defined Sync Delay_Req Follow_Up Delay_Resp Management...

Page 156: ...and time stamp related GPIO event generation Figure 11 1 IEEE 1588 Block Diagram 10 100 PHY Ethernet 10 100 PHY MII Ethernet IEEE 1588 Time Stamp MII To Host MAC IEEE 1588 Time Stamp IEEE 1588 Time S...

Page 157: ...as data from the PHY from the outside world and transmit is defined as data to the PHY This is consistent with the point of view of where the partner clock resides LAN9311 LAN9311i receives packets f...

Page 158: ...nce ID Source UUID High WORD Transmit Capture Register 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x and Port x 1588 Source UUID Low DWORD Transmit Capture Register 1588_SRC_UUID_LO_TX_CAPTURE_x The correspond...

Page 159: ...ddress it is further qualified as a Sync or Delay_Req message type On Ethernet PTP uses UDP messages Within the UDP payload is the PTP control byte offset 32 starting at 0 This byte determines the mes...

Page 160: ...isrupt linear time If the clock must be adjusted during operation of the 1588 protocol it is preferred to adjust the Addend value effectively speeding up or slowing down the clock until the correct ti...

Page 161: ...d Reload Add Registers are 64 bits they require two 32 bit write cycles one to each half before the registers are affected The writes may be in any order 11 5 IEEE 1588 GPIOs In addition to time stamp...

Page 162: ...he GPT_LOAD field at any time e g before or after the TIMER_EN bit is asserted Once enabled the GPT counts down until it reaches 0000h or until a new pre load value is written to the GPT_LOAD field At...

Page 163: ...rupt Status and Enable Register GPIO_INT_STS_EN All GPIO interrupts are configured to low logic level triggering GPIO_INT_POL 11 0 cleared in General Purpose I O Configuration Register GPIO_CFG Note G...

Page 164: ...nts occur when the value loaded into the 1588 Clock Target High DWORD Register 1588_CLOCK_TARGET_HI and 1588 Clock Target Low DWORD Register 1588_CLOCK_TARGET_LO matches the current IEEE 1588 clock va...

Page 165: ...re configured as LED outputs by setting the corresponding LED_EN bit in the LED Configuration Register LED_CFG When configured as a LED the pin is an open drain active low output and the GPIO related...

Page 166: ...be held high if the port does not have a valid link 100Link Activity A steady low output indicates the port has a valid link and the speed is 100Mbps The signal is pulsed high for 80mS to indicate TX...

Page 167: ...309 Figure 14 1 contains an overall base register memory map of the LAN9311 LAN9311i This memory map is not drawn to scale and should be used for general reference only Note Register bit type definiti...

Page 168: ...ocations as they all function identically and contain the same data This alias port addressing is implemented to allow hosts to burst through sequential addresses 14 1 2 TX RX Status FIFO s The TX and...

Page 169: ...4 Section 14 2 8 Virtual PHY on page 246 Section 14 2 9 Miscellaneous on page 260 Table 14 1 System Control and Status Registers ADDRESS OFFSET SYMBOL REGISTER NAME 050h ID_REV Chip ID and Revision Re...

Page 170: ...ce UUID Low DWORD Receive Capture Register Section 14 2 5 4 110h 1588_CLOCK_HI_TX_CAPTURE_1 Port 1 1588 Clock High DWORD Transmit Capture Register Section 14 2 5 5 114h 1588_CLOCK_LO_TX_CAPTURE_1 Port...

Page 171: ...APTURE_GPIO_8 GPIO 8 1588 Clock High DWORD Capture Register Section 14 2 5 9 164h 1588_CLOCK_LO_CAPTURE_GPIO_8 GPIO 8 1588 Clock Low DWORD Capture Register Section 14 2 5 10 168h 1588_CLOCK_HI_CAPTURE...

Page 172: ...ection 14 2 8 4 1D0h VPHY_AN_ADV Virtual PHY Auto Negotiation Advertisement Register Section 14 2 8 5 1D4h VPHY_AN_LP_BASE_ABILITY Virtual PHY Auto Negotiation Link Partner Base Page Ability Register...

Page 173: ...l Clear INT_DEAS_CLR Writing a 1 to this register clears the de assertion counter in the Interrupt Controller thus causing a new de assertion interval to begin regardless of whether or not the Interru...

Page 174: ...t the IRQ output is active high When the IRQ is configured as an open drain output via the IRQ_TYPE bit this bit is ignored and the interrupt is always active low 0 IRQ active low output 1 IRQ active...

Page 175: ...errupt Event SWITCH_INT This bit indicates an interrupt event from the Switch Fabric This bit should be used in conjunction with the Switch Global Interrupt Pending Register SW_IPR to determine the so...

Page 176: ...r has encountered an error Please refer to Section 9 9 5 Receiver Errors on page 137 for a description of the conditions that will cause an RXE R WC 0b 13 Transmitter Error TXE When generated indicate...

Page 177: ...Status FIFO Full Interrupt RSFF This interrupt is generated when the RX Status FIFO is full R WC 0b 3 RX Status FIFO Level Interrupt RSFL This interrupt is generated when the RX Status FIFO reaches th...

Page 178: ...t 2 PHY Interrupt Event Enable PHY_INT2_EN R W 0b 26 Port 1 PHY Interrupt Event Enable PHY_INT1_EN R W 0b 25 TX Stopped Interrupt Enable TXSTOP_INT_EN R W 0b 24 RX Stopped Interrupt Enable RXSTOP_INT_...

Page 179: ...SMSC LAN9311 LAN9311i 179 Revision 1 4 08 19 08 DATASHEET 5 RESERVED This bit must be written with 0b for proper operation R W 0b 4 RX Status FIFO Full Interrupt Enable RSFF_EN R W 0b 3 RX Status FIFO...

Page 180: ...O Available Interrupt TDFA will be generated in the Interrupt Status Register INT_STS R W 48h 23 16 TX Status Level The value in this field sets the level in number of DWORD s at which the TX Status F...

Page 181: ...ained on the last data transfer of a buffer The LAN9311 LAN9311i will add extra DWORD s of data up to the alignment specified in the table below The host is responsible for removing these extra DWORD...

Page 182: ...d data will be shifted by the number of bytes specified in this field An offset of 0 31 bytes is a valid number of offset bytes Note The two LSBs of this field D 9 8 must not be modified while the RX...

Page 183: ...e cleared to zero WO SC 0b 13 3 RESERVED RO 2 TX Status Allow Overrun TXSAO When this bit is cleared Host MAC data transmission is suspended if the TX Status FIFO becomes full Setting this bit high al...

Page 184: ...DESCRIPTION TYPE DEFAULT 31 RX Data FIFO Fast Forward RX_FFWD Writing a 1 to this bit causes the RX Data FIFO to fast forward to the start of the next frame This bit will remain high until the RX Dat...

Page 185: ...S DESCRIPTION TYPE DEFAULT 31 24 RESERVED RO 23 16 RX Status FIFO Used Space RXSUSED This field indicates the amount of space in DWORD s currently used in the RX Status FIFO RO 0b 15 0 RX Data FIFO Us...

Page 186: ...FO and the used space in the TX Status FIFO Offset 080h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 24 RESERVED RO 23 16 TX Status FIFO Used Space TXSUSED This field indicates the amount of space in...

Page 187: ...e frames that have been dropped by the Host MAC Offset 0A0h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 RX Dropped Frame Counter RX_DFC This counter is incremented every time a receive frame is dr...

Page 188: ...N TYPE DEFAULT 31 CSR Busy When a 1 is written into this bit the read or write operation is performed to the specified Host MAC CSR This bit will remain set until the operation is complete In the case...

Page 189: ...1 For more information on the Host MAC refer to Chapter 9 Host MAC on page 113 Offset 0A8h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Host MAC CSR Data This field contains the value read from or...

Page 190: ...ched The pause time transmitted in this frame is programmed in the FCPT field of the Host MAC Flow Control Register HMAC_FLOW in the Host MAC CSR space During half duplex operation each incoming frame...

Page 191: ...l on Address Decode Disabled 1 Flow Control on Address Decode Enabled R W 0b 0 Flow Control on Any Frame FCANY When this bit is set the Host MAC will assert back pressure or transmit a pause frame whe...

Page 192: ...face Datasheet Revision 1 4 08 19 08 192 SMSC LAN9311 LAN9311i DATASHEET 9h 300uS 302 2uS Ah 350uS 352 2uS Bh 400uS 402 2uS Ch 450uS 452 2uS Dh 500uS 502 2uS Eh 550uS 552 2uS Fh 600uS 602 2uS Table 14...

Page 193: ...he configured level high low will set the corresponding GPIO_INT bit in the General Purpose I O Interrupt Status and Enable Register GPIO_INT_STS_EN 0 Sets low logic level trigger on corresponding GPI...

Page 194: ...ed as a push pull driver As an open drain driver the output pin is driven low when the corresponding data register is cleared and is not driven when the corresponding data register is set As an open d...

Page 195: ...red as an input 1 GPIO pin is configured as an output R W 0h 15 12 RESERVED RO 11 0 GPIO Data 11 0 GPIOD 11 0 When a GPIO pin is enabled as an output the value written to this field is output on the c...

Page 196: ...er Bit 12 GPIO_EN of the Interrupt Enable Register INT_EN must also be set in order for an actual system level interrupt to occur Refer to Chapter 5 System Interrupts on page 49 for additional informa...

Page 197: ...the configuration strap LED_en_strap 7 0 Configuration strap values are latched on power on reset or nRST de assertion Some configuration straps can be overridden by values from the EEPROM Loader Refe...

Page 198: ...his bit the operation specified in the EPC_COMMAND field of this register is performed at the specified EEPROM address This bit will remain set until the selected operation is complete In the case of...

Page 199: ...write operations will fail until an EWEN command is issued WRITE Write Location If erase write operations are enabled in the EEPROM this command will cause the contents of the EEPROM Data Register E2P...

Page 200: ...rted EPC_COMMAND is attempted This bit is cleared when written high Note When in Microwire mode if an EEPROM device is not connected an internal pull down on the EEDI pin will keep the EEDI signal low...

Page 201: ...EEPROM Data Register E2P_DATA This read write register is used in conjunction with the EEPROM Command Register E2P_CMD to perform read and write operations with the serial EEPROM Offset 1B8h Size 32 b...

Page 202: ...of all the 1588 related registers can be seen in Table 14 1 For more information on the IEEE 1588 refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 155 14 2 5 1 Port x 1588 Clock High DWO...

Page 203: ...1588 Configuration Register 1588_CONFIG Note There are multiple instantiations of this register one for each port of the LAN9311 LAN9311i Refer to Section 14 2 5 for additional information Note For P...

Page 204: ...NFIG Note There are multiple instantiations of this register one for each port of the LAN9311 LAN9311i Refer to Section 14 2 5 for additional information Note For Port 0 Host MAC receive is defined as...

Page 205: ...t in the 1588 Configuration Register 1588_CONFIG Note There are multiple instantiations of this register one for each port of the LAN9311 LAN9311i Refer to Section 14 2 5 for additional information No...

Page 206: ...588 Configuration Register 1588_CONFIG Note There are multiple instantiations of this register one for each port of the LAN9311 LAN9311i Refer to Section 14 2 5 for additional information Note For Por...

Page 207: ...588 Configuration Register 1588_CONFIG Note There are multiple instantiations of this register one for each port of the LAN9311 LAN9311i Refer to Section 14 2 5 for additional information Note For Por...

Page 208: ...ONFIG Note There are multiple instantiations of this register one for each port of the LAN9311 LAN9311i Refer to Section 14 2 5 for additional information Note For Port 0 Host MAC receive is defined a...

Page 209: ...in the 1588 Configuration Register 1588_CONFIG Note There are multiple instantiations of this register one for each port of the LAN9311 LAN9311i Refer to Section 14 2 5 for additional information Not...

Page 210: ...D Capture Register 1588_CLOCK_HI_CAPTURE_GPIO_8 This read only register combined with the GPIO 8 1588 Clock Low DWORD Capture Register 1588_CLOCK_LO_CAPTURE_GPIO_8 form the 64 bit GPIO 8 timestamp cap...

Page 211: ...D Capture Register 1588_CLOCK_LO_CAPTURE_GPIO_8 This read only register combined with the GPIO 8 1588 Clock High DWORD Capture Register 1588_CLOCK_HI_CAPTURE_GPIO_8 form the 64 bit GPIO 8 timestamp ca...

Page 212: ...D Capture Register 1588_CLOCK_HI_CAPTURE_GPIO_9 This read only register combined with the GPIO 9 1588 Clock Low DWORD Capture Register 1588_CLOCK_LO_CAPTURE_GPIO_9 form the 64 bit GPIO 9 timestamp cap...

Page 213: ...D Capture Register 1588_CLOCK_LO_CAPTURE_GPIO_9 This read only register combined with the GPIO 9 1588 Clock High DWORD Capture Register 1588_CLOCK_HI_CAPTURE_GPIO_9 form the 64 bit GPIO 9 timestamp ca...

Page 214: ...y of 100MHz which can be adjusted via the 1588 Clock Addend Register 1588_CLOCK_ADDEND accordingly Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 155 for additional information Note Bo...

Page 215: ...cy of 100MHz which can be adjusted via the 1588 Clock Addend Register 1588_CLOCK_ADDEND accordingly Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 155 for additional information Note B...

Page 216: ...e for adjusting the 64 bit 1588 Clock frequency Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 155 for details on how to properly use this register Offset 178h Size 32 bits BITS DESCRI...

Page 217: ...value The 1588 Clock Target value is compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 155 f...

Page 218: ...value The 1588 Clock Target value is compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 155...

Page 219: ...the 1588 Clock Compare value when a clock compare event occurs and the Reload Add RELOAD_ADD bit of the 1588 Configuration Register 1588_CONFIG is set Refer to Chapter 11 IEEE 1588 Hardware Time Stam...

Page 220: ...hether this value is reloaded or added is determined by the Reload Add RELOAD_ADD bit of the 1588 Configuration Register 1588_CONFIG Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 155...

Page 221: ...Auxiliary user defined MAC address The Auxiliary MAC address can be enabled for each port of the LAN9311 LAN9311i via their respective User Defined MAC Address Enable bit in the 1588 Configuration Re...

Page 222: ...e 48 bit Auxiliary user defined MAC address The Auxiliary MAC address can be enabled for each port of the LAN9311 LAN9311i via their respective User Defined MAC Address Enable bit in the 1588 Configur...

Page 223: ...00 5E 00 01 83 as a PTP address on Port 2 R W 0b 27 Alternate MAC Address 3 Enable Port 2 MAC_ALT3_EN_2 This bit enables disables the alternate MAC address 3 on Port 2 0 Disables alternate MAC addres...

Page 224: ..._MAC_HI and 1588_AUX_MAC_LO registers 0 Disables auxiliary MAC address on Port 1 1 Enables auxiliary MAC address as a PTP address on Port 1 R W 0b 17 Lock Enable RX Port 1 LOCK_RX_1 This bit enables d...

Page 225: ...Disables auxiliary MAC address on Port 0 1 Enables auxiliary MAC address as a PTP address on Port 0 R W 0b 9 Lock Enable RX Port 0 Host MAC LOCK_RX_MII This bit enables disables the RX lock This lock...

Page 226: ...GPIO_EVENT_8 These bits determine the output on GPIO 8 when a clock target compare event occurs 00 100ns pulse output 01 Toggle output 10 1588_TIMER_INT bit value in the 1588_INT_STS_EN register outpu...

Page 227: ...1588 Port 1 TX Interrupt Enable 1588_PORT1_TX_EN R W 0b 20 1588 Port 0 Host MAC RX Interrupt Enable 1588_MII_RX_EN R W 0b 19 1588 Port 0 Host MAC TX Interrupt Enable 1588_MII_TX_EN R W 0b 18 GPIO9 158...

Page 228: ...be recognized as interrupt inputs R WC 0b 1 1588 GPIO8 Interrupt 1588_GPIO8_INT This interrupt indicates that an event on GPIO8 occurred and the 1588 clock was captured These interrupts are configured...

Page 229: ...nt IEEE 1588 clock values from the 1588 Clock High DWORD Register 1588_CLOCK_HI and 1588 Clock Low DWORD Register 1588_CLOCK_LO Refer to section Section 11 3 IEEE 1588 Clock on page 160 for additional...

Page 230: ...trol This register also provides read back of the currently enabled flow control settings whether set manually or Auto Negotiated Refer to Section 6 2 3 Flow Control Enable Logic on page 58 for additi...

Page 231: ...values this register is updated with the new values See Section 4 2 4 Configuration Straps on page 40 for more information Note 14 7 The default value of this field is determined by the manual_FC_stra...

Page 232: ...Port 2 0 Flow control receive is currently disabled 1 Flow control receive is currently enabled RO Note 14 9 3 Port 2 Current Transmit Flow Control Enable CUR_TX_FC_2 This bit indicates the actual tra...

Page 233: ...EEPROM Loader re writes the values this register is updated with the new values Refer to Section 6 2 3 Flow Control Enable Logic on page 58 for additional information Note 14 10 The default value of...

Page 234: ...be disabled when using this feature MANUAL_FC_MII should be set TX_FC_MII RX_FC_MII and BP_EN_MII should be cleared FCANY FCADD FCBRD and FCMULT in the AFC_CFG register should be cleared R W 0b 6 Port...

Page 235: ...his register is updated with the new values See Section 4 2 4 Configuration Straps on page 40 for more information Note 14 15 The default value of this field is determined by the manual_FC_strap_mii c...

Page 236: ...ers on page 309 for details on the registers indirectly accessible via this register Offset 1ACh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Switch CSR Data CSR_DATA This field contains the value...

Page 237: ...he specified Switch Engine CSR 0 Write 1 Read R W 0b 29 Auto Increment AUTO_INC This bit enables disables the auto increment feature When this bit is set a write to the Switch Fabric CSR Interface Dat...

Page 238: ...ter data bits 31 24 CSR_BE 2 corresponds to register data bits 23 16 CSR_BE 1 corresponds to register data bits 15 8 CSR_BE 0 corresponds to register data bits 7 0 Typically all four byte enables shou...

Page 239: ...least significant byte of this register bits 7 0 is loaded from address 05h of the EEPROM The second byte bits 15 8 is loaded from address 06h of the EEPROM These EEPROM values are also loaded into t...

Page 240: ...The least significant byte of this register bits 7 0 is loaded from address 01h of the EEPROM The most significant byte bits 31 24 is loaded from address 04h of the EEPROM These EEPROM values are als...

Page 241: ...ter SWITCH_CSR_CMD is mapped via Table 14 3 For more information on this method of writing to the Switch Fabric CSR s refer to Section 6 2 3 Flow Control Enable Logic on page 58 Note This set of regis...

Page 242: ...PORT_INGRESS_CFG 1841h 25Ch SWE_ADMT_ONLY_VLAN 1842h 260h SWE_PORT_STATE 1843h 264h SWE_PRI_TO_QUE 1845h 268h SWE_PORT_MIRROR 1846h 26Ch SWE_INGRESS_PORT_TYP 1847h 270h SWE_BCST_THROT 1848h 274h SWE_A...

Page 243: ...B0h BM_EGRSS_PORT_TYPE 1C0Ch 2B4h BM_EGRSS_RATE_00_01 1C0Dh 2B8h BM_EGRSS_RATE_02_03 1C0Eh 2BCh BM_EGRSS_RATE_10_11 1C0Fh 2C0h BM_EGRSS_RATE_12_13 1C10h 2C4h BM_EGRSS_RATE_20_21 1C11h 2C8h BM_EGRSS_RA...

Page 244: ...to Section 10 2 4 EEPROM Loader on page 150 for additional information 14 2 7 1 PHY Management Interface Data Register PMI_DATA This register is used in conjunction with the PHY Management Interface...

Page 245: ...M Loader and NOT by the Host bus Refer to Section 10 2 4 EEPROM Loader on page 150 for additional information Offset 0A8h EEPROM Loader Access Only Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RES...

Page 246: ...PHY functionality and operation information see Section 7 3 Virtual PHY on page 96 Note All Virtual PHY registers follow the IEEE 802 3 clause 22 2 4 specified MII management register set All function...

Page 247: ...t sent to the switch fabric Instead they are looped back onto the receive path 0 Loopback mode disabled normal operation 1 Loopback mode enabled R W 0b 13 Speed Select LSB VPHY_SPEED_SEL_LSB This bit...

Page 248: ...he register is 16 bits wide 7 Collision Test VPHY_COL_TEST This bit enables disables the collision test mode When set the collision signal to the Host MAC is active during transmission from the Host M...

Page 249: ...e to perform 100BASE X half duplex RO 1b 12 10BASE T Full Duplex This bit displays the status of 10BASE T full duplex compatibility 0 PHY not able to perform 10BASE T full duplex 1 PHY able to perform...

Page 250: ...EE 802 3 specification 6 MF Preamble Suppression This bit indicates whether the Virtual PHY accepts management frames with the preamble suppressed 0 Management frames with preamble suppressed not acce...

Page 251: ...ned in the Virtual PHY Identification LSB Register VPHY_ID_LSB Note 14 23 The reserved bits 31 16 are used to pad the register to 32 bits so that each register is on a DWORD boundary When accessed ser...

Page 252: ...egister to 32 bits so that each register is on a DWORD boundary When accessed serially through the MII management protocol the register is 16 bits wide Note 14 26 IEEE allows a value of zero in each o...

Page 253: ...RO 0b Note 14 29 12 RESERVED RO 11 Asymmetric Pause This bit determines the advertised asymmetric pause capability 0 No Asymmetric PAUSE toward link partner advertised 1 Asymmetric PAUSE toward link...

Page 254: ...0 The Pause bit defaults to 1 if the manual_FC_strap_mii strap is low and 0 if the manual_FC_strap_mii strap is high Configuration strap values are latched upon the de assertion of a chip level reset...

Page 255: ...ates whether the link code word has been received from the partner and is always 1 0 Link code word not yet received from partner 1 Link code word received from partner RO 1b Note 14 34 13 Remote Faul...

Page 256: ...T half duplex For more information on the Virtual PHY auto negotiation see Section 7 3 1 Virtual PHY Auto Negotiation on page 96 7 100BASE X Half Duplex This bit indicates the emulated link partner PH...

Page 257: ...y Offset Index decimal 1D8h 6 Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED See Note 14 37 RO 15 5 RESERVED RO 4 Parallel Detection Fault This bit indicates whether a Parallel Detection Fa...

Page 258: ...ation Register MAC_RX_CFG_x must be set for this port Otherwise the switch fabric will ignore receive activity when transmitting in half duplex mode This mode works even if the Isolate bit of the Virt...

Page 259: ...ts the Speed Select LSB VPHY_SPEED_SEL_LSB and Duplex Mode VPHY_DUPLEX bit settings of the VPHY_BASIC_CTRL register Refer to Section 7 3 1 Virtual PHY Auto Negotiation on page 96 for information on th...

Page 260: ...tions such as the Chip ID revision byte order testing power management hardware configuration general purpose timer and free running counter 14 2 9 1 Chip ID and Revision ID_REV This read only registe...

Page 261: ...on on byte ordering Note This register can be read while the LAN9311 LAN9311i is in the reset or not ready states Note Either half of this register can be read without the need to read the other half...

Page 262: ...an interrupt if enabled Note With the exception of the HW_CFG PMT_CTRL BYTE_TEST and RESET_CTL registers read access to any internal resources is forbidden while the READY bit is cleared Writes to an...

Page 263: ...ta FIFO is used for both TX data and TX commands The RX Status and Data FIFOs consume the remaining space which is equal to 16KB minus TX_FIF_SIZ See section Section 9 7 3 FIFO Memory Allocation Confi...

Page 264: ...it it is required that the event in the PHY be cleared as well The event sources are described in Section 4 3 Power Management on page 46 R WC 0b 15 Energy Detect Enable Port 2 ED_EN2 When set the PME...

Page 265: ...be cleared as well The event sources are described in Section 4 3 Power Management on page 46 R WC 0b 4 RESERVED RO 3 PME Indication PME_IND The PME signal can be configured as a pulsed output or a st...

Page 266: ...ost processor may interrogate this field as an indication that the LAN9311 LAN9311i has stabilized and is fully active This bit can cause an interrupt if enabled Note With the exception of the HW_CFG...

Page 267: ...Count Register GPT_CNT Refer to Section 12 1 General Purpose Timer on page 162 for additional information Offset 08Ch Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 30 RESERVED RO 29 General Purpose Ti...

Page 268: ...general purpose timer GPT value The register should be used in conjunction with the General Purpose Timer Configuration Register GPT_CFG to configure and monitor the GPT Refer to Section 12 1 General...

Page 269: ...ion Offset 09Ch Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Free Running Counter FR_CNT This field reflects the current value of the free running 32 bit counter At reset the counter starts at zero...

Page 270: ...is not accessible via the EEPROM Loader R W SC 0b 1 Port 1 PHY Reset PHY1_RST Setting this bit resets the Port 1 PHY The internal logic automatically holds the PHY reset for a minimum of 102uS When t...

Page 271: ...ese registers allow access to the 10 100 Ethernet PHY registers and the switch engine via Port 0 Table 14 6 Host MAC Adressable Registers INDEX SYMBOL REGISTER NAME 00h RESERVED Reserved for Future Us...

Page 272: ...uplex Mode bit is set R W 0b 22 RESERVED RO 21 Loopback operation Mode LOOPBK Selects the loop back operation modes for the Host MAC This field is only valid for full duplex mode In internal loopback...

Page 273: ...n the IA addresses are perfect address filtered according to the MAC Address register Refer to Section 9 4 3 Hash Perfect Filtering on page 116 for additional information R W 0b 12 RESERVED RO 11 Disa...

Page 274: ...e LFSR counter to a predetermined value as in the table below Thus if the value of K 10 the Host MAC will look at the BOLMT if it is 00b then use the lower ten bits of the LFSR counter for the wait co...

Page 275: ...econd byte bits 15 8 is loaded from address 06h of the EEPROM Section 9 6 Host MAC Address on page 120 details the byte ordering of the HMAC_ADDRL and HMAC_ADDRH registers with respect to the receptio...

Page 276: ...st significant byte of this register is loaded from address 04h of the EEPROM Section 9 6 Host MAC Address on page 120 details the byte ordering of the HMAC_ADDRL and HMAC_ADDRH registers with respect...

Page 277: ...ulticast Hash Table Hi register If the corresponding bit is 1 then the multicast frame is accepted Otherwise it is rejected If the Pass All Multicast MCPAS bit of the Host MAC Control Register HMAC_CR...

Page 278: ...ticast Hash Table Low Register HMAC_HASHL This read write register defines the lower 32 bits of the Multicast Hash Table Please refer to the Host MAC Multicast Hash Table High Register HMAC_HASHH and...

Page 279: ...egister Index MIIRINDA These bits select the desired MII register in the PHY R W 00000b 5 2 RESERVED RO 1 MII Write MIIWnR Setting this bit tells the PHY that this will be a write operation using the...

Page 280: ...to access the internal PHY registers This register contains either the data to be written to the PHY register specified in the HMAC_MII_ACC Register or the read data from the PHY register whose index...

Page 281: ...he PAUSE TIME field in the control frame This field must be initialized before full duplex automatic flow control is enabled R W 0000h 15 3 RESERVED RO 2 Pass Control Frames FCPASS When set the Host M...

Page 282: ...t must be set During a transfer of control frame this bit continues to be set signifying that a frame transmission is in progress After the PAUSE control frame s transmission is complete the Host MAC...

Page 283: ...ame length is increased from 1518 bytes to 1522 bytes Refer to Section 9 3 Virtual Local Area Network VLAN Support on page 114 for additional information Offset 9h Size 32 bits BITS DESCRIPTION TYPE D...

Page 284: ...Network VLAN Support on page 114 for additional information Offset Ah Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 0 VLAN2 Tag Identifier VTI2 This field contains the VLAN Tag used...

Page 285: ...ke Up Frame Filter WFF The Wake up frame filter is configured through this register using an indexing mechanism After power on reset digital reset or soft reset the Host MAC loads the first value writ...

Page 286: ...ED RO 9 Global Unicast Enable GUE When set the Host MAC wakes up from power saving mode on receipt of a global unicast frame This is accomplished by enabling global unicasts as a wakeup frame qualifie...

Page 287: ...ster index numbers is also included in Table 14 4 Note When serially accessed the Virtual PHY registers are only 16 bits wide as is standard for MII management of PHY s 14 4 2 Port 1 2 PHY Registers T...

Page 288: ...ster Section 14 4 2 9 27 PHY_SPECIAL_CONTROL_STAT_IND_x Port x PHY Special Control Status Indication Register Section 14 4 2 10 29 PHY_INTERRUPT_SOURCE_x Port x PHY Interrupt Source Flags Register Sec...

Page 289: ...wn Transmit bit in the Port x MAC Receive Configuration Register MAC_RX_CFG_x must be set for the specified port Otherwise the switch fabric will ignore receive activity when transmitting in half dupl...

Page 290: ...etermined by the logical AND of the negation of the Auto Negotiation strap autoneg_strap_1 for Port 1 PHY autoneg_strap_2 for Port 2 PHY and the duplex select strap duplex_strap_1 for Port 1 PHY duple...

Page 291: ...splays the status of 10BASE T full duplex compatibility 0 PHY not able to perform 10BASE T full duplex 1 PHY able to perform 10BASE T full duplex RO 1b 11 10BASE T Half Duplex This bit displays the st...

Page 292: ...of the PHY s auto negotiation 0 PHY is unable to perform auto negotiation 1 PHY is able to perform auto negotiation RO 1b 2 Link Status This bit indicates the status of the link 0 Link is down 1 Link...

Page 293: ...er PHY_ID_MSB_x This read write register contains the MSB of the Organizationally Unique Identifier OUI for the Port x PHY The LSB of the PHY OUI is contained in the Port x PHY Identification LSB Regi...

Page 294: ...r OUI for the Port x PHY The MSB of the PHY OUI is contained in the Port x PHY Identification MSB Register PHY_ID_MSB_x Index decimal 3 Size 16 bits BITS DESCRIPTION TYPE DEFAULT 15 10 PHY ID This fie...

Page 295: ...ility 0 No Asymmetric PAUSE toward link partner advertised 1 Asymmetric PAUSE toward link partner advertised R W 0b Note 14 53 10 Symmetric Pause This bit determines the advertised symmetric pause cap...

Page 296: ...ault behavior of this bit Configuration strap values are latched upon the de assertion of a chip level reset as described in Section 4 2 4 Configuration Straps on page 40 Refer to Section 4 2 4 Config...

Page 297: ...ith 16 Bit Non PCI CPU Interface Datasheet SMSC LAN9311 LAN9311i 297 Revision 1 4 08 19 08 DATASHEET 1 1 1 Table 14 9 10BASE T Half Duplex Advertisement Bit Default Value autoneg_strap_x speed_strap_x...

Page 298: ...d from partner RO 0b 13 Remote Fault This bit indicates whether a remote fault has been detected 0 No remote fault 1 Remote fault detected RO 0b 12 RESERVED RO 11 Asymmetric Pause This bit indicates t...

Page 299: ...T full duplex capability 0 10BASE T full duplex ability not supported 1 10BASE T full duplex ability supported RO 0b 5 10BASE T Half Duplex This bit indicates the link partner PHY 10BASE T half duple...

Page 300: ...ected via the Parallel Detection function RO LH 0b 3 Link Partner Next Page Able This bit indicates whether the link partner has next page ability 0 Link partner does not contain next page capability...

Page 301: ...S DESCRIPTION TYPE DEFAULT 15 14 RESERVED RO 13 Energy Detect Power Down EDPWRDOWN This bit controls the Energy Detect Power Down mode 0 Energy Detect Power Down is disabled 1 Energy Detect Power Down...

Page 302: ...d upon the de assertion of a chip level reset as described in Section 4 2 4 Configuration Straps on page 40 Refer to Section 4 2 4 Configuration Straps on page 40 for configuration strap definitions N...

Page 303: ...ed Auto negotiation enabled CRS is active during Transmit Receive 1100 0100 101 Repeater mode Auto negotiation enabled 100BASE TX Half Duplex is advertised CRS is active during Receive 1100 0100 110 P...

Page 304: ...aps on page 40 for configuration strap definitions 0 Port x Auto MDIX determined by strap inputs 1 Port x Auto MDIX determined by bits 14 and 13 R W NASR Note 14 61 0b 14 Auto MDIX Enable AMDIXEN When...

Page 305: ...MSC LAN9311 LAN9311i 305 Revision 1 4 08 19 08 DATASHEET Table 14 11 Auto MDIX Enable and Auto MDIX State Bit Functionality Auto MDIX Enable Bit 14 Auto MDIX State Bit 13 MODE 0 0 Manual mode no cross...

Page 306: ...atus Register PHY_MODE_CONTROL_STATUS_x has been set 0 Not source of interrupt 1 ENERGYON generated RO LH 0b 6 INT6 This interrupt source bit indicates Auto Negotiation is complete 0 Not source of int...

Page 307: ...ation interrupt 0 Interrupt source is masked 1 Interrupt source is enabled R W 0b 5 INT5_MASK This interrupt mask bit enables masks the remote fault interrupt 0 Interrupt source is masked 1 Interrupt...

Page 308: ...PE DEFAULT 15 13 RESERVED RO 12 Autodone This bit indicates the status of the Auto Negotiation on the Port x PHY 0 Auto Negotiation is not completed is disabled or is not active 1 Auto Negotiation is...

Page 309: ...L_FC_MII located in the system CSR address space Table 14 12 lists the Switch CSRs and their corresponding addresses in order The switch fabric registers can be categorized into the following sub sect...

Page 310: ..._JABB_CNT_MII Port 0 MAC Receive Jabber Error Count Register Section 14 5 2 17 041Fh MAC_RX_ALIGN_CNT_MII Port 0 MAC Receive Alignment Error Count Register Section 14 5 2 18 0420h MAC_RX_PKTLEN_CNT_MI...

Page 311: ...er Section 14 5 2 37 045Fh MAC_TX_LATECOL_MII Port 0 MAC Transmit Late Collision Count Register Section 14 5 2 38 0460h MAC_TX_EXCOL_CNT_MII Port 0 MAC Transmit Excessive Collision Count Register Sect...

Page 312: ...nt Register Section 14 5 2 14 081Ch MAC_RX_PAUSE_CNT_1 Port 1 MAC Receive Pause Frame Count Register Section 14 5 2 15 081Dh MAC_RX_FRAG_CNT_1 Port 1 MAC Receive Fragment Error Count Register Section...

Page 313: ...t Packet Length Count Register Section 14 5 2 35 085Dh MAC_TX_BRDCST_CNT_1 Port 1 MAC Transmit Broadcast Count Register Section 14 5 2 36 085Eh MAC_TX_MULCST_CNT_1 Port 1 MAC Transmit Multicast Count...

Page 314: ...12 0C1Ah MAC_RX_MULCST_CNT_2 Port 2 MAC Receive Multicast Count Register Section 14 5 2 13 0C1Bh MAC_RX_BRDCST_CNT_2 Port 2 MAC Receive Broadcast Count Register Section 14 5 2 14 0C1Ch MAC_RX_PAUSE_C...

Page 315: ...5Ah MAC_TX_UNDSZE_CNT_2 Port 2 MAC Transmit Undersize Count Register Section 14 5 2 34 0C5Bh RESERVED Reserved for Future Use 0C5Ch MAC_TX_PKTLEN_CNT_2 Port 2 MAC Transmit Packet Length Count Register...

Page 316: ...ne VLAN Read Data Register Section 14 5 3 10 180Fh RESERVED Reserved for Future Use 1810h SWE_VLAN_CMD_STS Switch Engine VLAN Command Status Register Section 14 5 3 11 1811h SWE_DIFFSERV_TBL_CMD Switc...

Page 317: ...ion 14 5 3 31 1852h SWE_FILTERED_CNT_2 Switch Engine Port 2 Ingress Filtered Count Register Section 14 5 3 32 1853h 1854h RESERVED Reserved for Future Use 1855h SWE_INGRESS_REGEN_TBL_MII Switch Engine...

Page 318: ...anager Port 0 Egress Rate Priority Queue 0 1 Register Section 14 5 4 14 1C0Eh BM_EGRSS_RATE_02_03 Buffer Manager Port 0 Egress Rate Priority Queue 2 3 Register Section 14 5 4 15 1C0Fh BM_EGRSS_RATE_10...

Page 319: ...4 08 19 08 DATASHEET 1C20h BM_IMR Buffer Manager Interrupt Mask Register Section 14 5 4 26 1C21h BM_IPR Buffer Manager Interrupt Pending Register Section 14 5 4 27 1C22h FFFFh RESERVED Reserved for F...

Page 320: ...of the switch fabric A list of the general switch CSRs and their corresponding register numbers is included in Table 14 12 14 5 1 1 Switch Device ID Register SW_DEV_ID This read only register contain...

Page 321: ...et Register SW_RESET This register contains the switch fabric global reset Refer to Section 4 2 Resets on page 36 for more information Register 0001h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 1 RE...

Page 322: ...ch fabric interrupts due to the Buffer Manager via the Buffer Manager Interrupt Pending Register BM_IPR The status bits in the SW_IPR register are not affected R W 1b 5 Switch Engine Interrupt Mask SW...

Page 323: ...rmation Register 0005h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 7 RESERVED RO 6 Buffer Manager Interrupt BM Set when any unmasked bit in the Buffer Manager Interrupt Pending Register BM_IPR is tr...

Page 324: ...ve been consolidated A lowercase x has been appended to the end of each switch port register name in this section where x should be replaced with MII 1 or 2 for the Port 0 Port 1 or Port 2 registers r...

Page 325: ...ve Own Transmit When set the switch port will receive its own transmission if it is looped back from the PHY Normally this function is only used in Half Duplex PHY loopback R W 0b 4 RESERVED RO 3 Jumb...

Page 326: ...his register provides a counter of undersized packets received by the port The counter is cleared upon being read Register Port0 0410h Size 32 bits Port1 0810h Port2 0C10h BITS DESCRIPTION TYPE DEFAUL...

Page 327: ...red upon being read Note A bad packet is defined as a packet that has an FCS or Symbol error For this counter a packet that is not an integral number of bytes is rounded down to the nearest byte Regis...

Page 328: ...is cleared upon being read Note A bad packet is defined as a packet that has an FCS or Symbol error For this counter a packet that is not an integral number of bytes is rounded down to the nearest byt...

Page 329: ...is cleared upon being read Note A bad packet is defined as a packet that has an FCS or Symbol error For this counter a packet that is not an integral number of bytes is rounded down to the nearest by...

Page 330: ...is cleared upon being read Note A bad packet is defined as a packet that has an FCS or Symbol error For this counter a packet that is not an integral number of bytes is rounded down to the nearest byt...

Page 331: ...is cleared upon being read Note A bad packet is defined as a packet that has an FCS or Symbol error For this counter a packet that is not an integral number of bytes is rounded down to the nearest by...

Page 332: ...packet with the maximum number of bytes that is not an integral number of bytes e g a 1518 1 2 byte packet is counted Register Port0 0416h Size 32 bits Port1 0816h Port2 0C16h BITS DESCRIPTION TYPE D...

Page 333: ...is not an integral number of bytes e g a 1518 1 2 byte packet is not considered oversize Register Port0 0417h Size 32 bits Port1 0817h Port2 0C17h BITS DESCRIPTION TYPE DEFAULT 31 0 RX Oversize Count...

Page 334: ...packets that are or proper length and are free of errors The counter is cleared upon being read Note A bad packet is one that has a FCS or Symbol error Register Port0 0418h Size 32 bits Port1 0818h Po...

Page 335: ...9h Size 32 bits Port1 0819h Port2 0C19h BITS DESCRIPTION TYPE DEFAULT 31 0 RX CRC Count of packets that have between 64 and the maximum allowable number of bytes and have a bad FCS but do not have an...

Page 336: ...ion address The counter is cleared upon being read Note A bad packet is one that has a FCS or Symbol error Register Port0 041Ah Size 32 bits Port1 081Ah Port2 0C1Ah BITS DESCRIPTION TYPE DEFAULT 31 0...

Page 337: ...s with a broadcast destination address The counter is cleared upon being read Note A bad packet is one that has a FCS or Symbol error Register Port0 041Bh Size 32 bits Port1 081Bh Port2 0C1Bh BITS DES...

Page 338: ...e frame packets The counter is cleared upon being read Note A bad packet is one that has a FCS or Symbol error Register Port0 041Ch Size 32 bits Port1 081Ch Port2 0C1Ch BITS DESCRIPTION TYPE DEFAULT 3...

Page 339: ...gister provides a counter of received packets of less than 64 bytes and a FCS error The counter is cleared upon being read Register Port0 041Dh Size 32 bits Port1 081Dh Port2 0C1Dh BITS DESCRIPTION TY...

Page 340: ...n integral number of bytes e g a 1518 1 2 byte packet and contains a FCS error is not considered jabber and is not counted here Register Port0 041Eh Size 32 bits Port1 081Eh Port2 0C1Eh BITS DESCRIPTI...

Page 341: ...ytes e g a 1518 1 2 byte packet and a FCS error is considered an alignment error and is counted Register Port0 041Fh Size 32 bits Port1 081Fh Port2 0C1Fh BITS DESCRIPTION TYPE DEFAULT 31 0 RX Alignmen...

Page 342: ...bytes Jumbo2K 1 If this occurs the byte count recorded is 1518 1522 or 2048 respectively The Jumbo2K bit is located in the Port x MAC Receive Configuration Register MAC_RX_CFG_x Note A bad packet is...

Page 343: ...r of total bytes received in good packets The counter is cleared upon being read Note A bad packet is one that has an FCS or Symbol error Register Port0 0421h Size 32 bits Port1 0821h Port2 0C21h BITS...

Page 344: ...BOL_CNT_x This register provides a counter of received packets with a symbol error The counter is cleared upon being read Register Port0 0422h Size 32 bits Port1 0822h Port2 0C22h BITS DESCRIPTION TYP...

Page 345: ...ackets with a type field of 8808h The counter is cleared upon being read Note A bad packet is one that has an FCS or Symbol error Register Port0 0423h Size 32 bits Port1 0823h Port2 0C23h BITS DESCRIP...

Page 346: ...of the Port x MAC Receive Packet Length Count Register MAC_RX_PKTLEN_CNT_x Port x MAC Transmit Packet Length Count Register MAC_TX_PKTLEN_CNT_x and Port x MAC Receive Good Packet Length Count Registe...

Page 347: ...ort0 0441h Size 32 bits Port1 0841h Port2 0C41h BITS DESCRIPTION TYPE DEFAULT 31 18 RESERVED RO 17 16 Backoff Reset RX TX Half duplex only Determines when the truncated binary exponential backoff atte...

Page 348: ...ister Port0 0451h Size 32 bits Port1 0851h Port2 0C51h BITS DESCRIPTION TYPE DEFAULT 31 0 TX Deferred Count of packets that were available for transmission but were deferred on the first transmit atte...

Page 349: ...MAC_TX_PAUSE_CNT_x This register provides a counter of transmitted pause packets The counter is cleared upon being read Register Port0 0452h Size 32 bits Port1 0852h Port2 0C52h BITS DESCRIPTION TYPE...

Page 350: ...register provides a counter of successful transmissions The counter is cleared upon being read Register Port0 0453h Size 32 bits Port1 0853h Port2 0C53h BITS DESCRIPTION TYPE DEFAULT 31 0 TX OK Count...

Page 351: ...CNT_x This register provides a counter of 64 byte packets transmitted by the port The counter is cleared upon being read Register Port0 0454h Size 32 bits Port1 0854h Port2 0C54h BITS DESCRIPTION TYPE...

Page 352: ...s register provides a counter of transmitted packets between the size of 65 to 127 bytes The counter is cleared upon being read Register Port0 0455h Size 32 bits Port1 0855h Port2 0C55h BITS DESCRIPTI...

Page 353: ...s register provides a counter of transmitted packets between the size of 128 to 255 bytes The counter is cleared upon being read Register Port0 0456h Size 32 bits Port1 0856h Port2 0C56h BITS DESCRIPT...

Page 354: ...register provides a counter of transmitted packets between the size of 256 to 511 bytes The counter is cleared upon being read Register Port0 0457h Size 32 bits Port1 0857h Port2 0C57h BITS DESCRIPTI...

Page 355: ...register provides a counter of transmitted packets between the size of 512 to 1023 bytes The counter is cleared upon being read Register Port0 0458h Size 32 bits Port1 0858h Port2 0C58h BITS DESCRIPT...

Page 356: ...provides a counter of transmitted packets between the size of 1024 to the maximum allowable number bytes The counter is cleared upon being read Register Port0 0459h Size 32 bits Port1 0859h Port2 0C59...

Page 357: ...undersized packets transmitted by the port The counter is cleared upon being read Register Port0 045Ah Size 32 bits Port1 085Ah Port2 0C5Ah BITS DESCRIPTION TYPE DEFAULT 31 0 TX Undersize Count of pa...

Page 358: ...rovides a counter of total bytes transmitted The counter is cleared upon being read Register Port0 045Ch Size 32 bits Port1 085Ch Port2 0C5Ch BITS DESCRIPTION TYPE DEFAULT 31 0 TX Bytes Count of total...

Page 359: ...TX_BRDCST_CNT_x This register provides a counter of transmitted broadcast packets The counter is cleared upon being read Register Port0 045Dh Size 32 bits Port1 085Dh Port2 0C5Dh BITS DESCRIPTION TYPE...

Page 360: ...is register provides a counter of transmitted multicast packets The counter is cleared upon being read Register Port0 045Eh Size 32 bits Port1 085Eh Port2 0C5Eh BITS DESCRIPTION TYPE DEFAULT 31 0 TX M...

Page 361: ...ransmitted packets which experienced a late collision The counter is cleared upon being read Register Port0 045Fh Size 32 bits Port1 085Fh Port2 0C5Fh BITS DESCRIPTION TYPE DEFAULT 31 0 TX Late Collis...

Page 362: ...transmitted packets which experienced 16 collisions The counter is cleared upon being read Register Port0 0460h Size 32 bits Port1 0860h Port2 0C60h BITS DESCRIPTION TYPE DEFAULT 31 0 TX Excessive Co...

Page 363: ...mitted packets which experienced exactly 1 collision The counter is cleared upon being read Register Port0 0461h Size 32 bits Port1 0861h Port2 0C61h BITS DESCRIPTION TYPE DEFAULT 31 0 TX Excessive Co...

Page 364: ...packets which experienced between 2 and 15 collisions The counter is cleared upon being read Register Port0 0462h Size 32 bits Port1 0862h Port2 0C62h BITS DESCRIPTION TYPE DEFAULT 31 0 TX Excessive C...

Page 365: ...counter of total collisions including late collisions The counter is cleared upon being read Register Port0 0463h Size 32 bits Port1 0863h Port2 0C63h BITS DESCRIPTION TYPE DEFAULT 31 0 TX Total Colli...

Page 366: ...asked via this register An interrupt is masked by setting the corresponding bit of this register Clearing a bit will unmask the interrupt Refer to Chapter 5 System Interrupts on page 49 for more infor...

Page 367: ...x interrupts A set bit indicates an interrupt has been triggered All interrupts in this register may be masked via the Port x MAC Interrupt Pending Register MAC_IPR_x register Refer to Chapter 5 Syste...

Page 368: ...ister The Make Pending bit in the Switch Engine ALR Command Status Register SWE_ALR_CMD_STS register indicates when the command is finished Refer to Chapter 6 Switch Fabric on page 55 for more informa...

Page 369: ...ta 1 Register SWE_ALR_WR_DAT_1 and contains the first 32 bits of ALR data to be manually written via the Make Entry command in the Switch Engine ALR Command Register SWE_ALR_CMD Register 1801h Size 32...

Page 370: ...a destination address that matches the MAC address in the SWE_ALR_WR_DAT_1 and SWE_ALR_WR_DAT_0 registers will be forwarded regardless of the port state of the ingress or egress port s This is typical...

Page 371: ...ntains the last 16 bits of the ALR entry that will be written into the ALR table They correspond to the last 16 bits of the MAC address Bit 15 holds the MSB of the last byte the last bit on the wire T...

Page 372: ...t 32 bits of the ALR entry and is loaded via the Get First Entry or Get Next Entry commands in the Switch Engine ALR Command Register SWE_ALR_CMD This register is only valid when either of the Valid o...

Page 373: ...his bit stays cleared when the top of the ALR table is reached without finding an entry RO 0b 23 End of Table This bit indicates that the end of the ALR table has been reached and further Get Next Ent...

Page 374: ...ddress These field contains the last 16 bits of the ALR entry They correspond to the last 16 bits of the MAC address Bit 15 holds the MSB of the last byte the last bit on the wire The first 32 bits of...

Page 375: ...lized Register 1808h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 2 RESERVED RO 1 ALR Init Done When set indicates that the ALR table has finished being initialized by the reset process The initializ...

Page 376: ...SMSC LAN9311 LAN9311i DATASHEET 14 5 3 7 Switch Engine ALR Configuration Register SWE_ALR_CFG This register controls the ALR aging timer duration Register 1809h Size 32 bits BITS DESCRIPTION TYPE DEFA...

Page 377: ...Data Register SWE_VLAN_RD_DATA can then be read For a write access the Switch Engine VLAN Write Data Register SWE_VLAN_WR_DATA register should be written first The Operation Pending bit in the Switch...

Page 378: ...rt 2 Indicates the configuration of Port 2 for this VLAN entry 1 Member Packets with a VID that matches this entry are allowed on ingress The port is a member of the broadcast domain on egress 0 Not a...

Page 379: ...able entry as follows RO 00000h BITS DESCRIPTION DEFAULT 17 Member Port 2 Indicates the configuration of Port 2 for this VLAN entry 1 Member Packets with a VID that matches this entry are allowed on i...

Page 380: ...11 Switch Engine VLAN Command Status Register SWE_VLAN_CMD_STS This register indicates the current VLAN command status Register 1810h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 1 RESERVED RO 0 Ope...

Page 381: ...ter SWE_DIFFSERV_TBL_CMD_STS indicates when the command is finished The Switch Engine DIFFSERV Table Read Data Register SWE_DIFFSERV_TBL_RD_DATA can then be read For a write access the Switch Engine D...

Page 382: ...RV_TBL_WR_DATA This register is used to write the DIFFSERV table The DIFFSERV table is not initialized upon reset on power up If DIFFSERV is enabled the full table should be initialized by the host Re...

Page 383: ...4 5 3 14 Switch Engine DIFFSERV Table Read Data Register SWE_DIFFSERV_TBL_RD_DATA This register is used to read the DIFFSERV table Register 1813h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 3 RESERV...

Page 384: ...Engine DIFFSERV Table Command Status Register SWE_DIFFSERV_TBL_CMD_STS This register indicates the current DIFFSERV command status Register 1814h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 1 RESERV...

Page 385: ...en set IPv4 IGMP packets are snooped and sent to the MLD IGMP snoop port R W 0b 6 SWE Counter Test When this bit is set the Switch Engine counters that normally clear to 0 when read will be set to 7FF...

Page 386: ...1i DATASHEET 1 VL Higher Priority When this bit is set and VLANs are enabled the priority from the VLAN tag has higher priority than the IP TOS SC field R W 1b 0 VLAN Enable When set VLAN ingress rule...

Page 387: ...pond to switch ports 2 1 0 respectively R W 111b 2 0 Enable Membership Checking When set VLAN membership is checked when a packet is received on the corresponding port The packet will be filtered if t...

Page 388: ...gress rule for allowing only VLAN tagged packets Register 1842h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 3 RESERVED RO 2 0 Admit Only VLAN When set untagged and priority tagged packets are filter...

Page 389: ...RVED RO 5 4 Port State Port 2 These bits specify the spanning tree port states for Port 2 00 Forwarding 01 Blocking 10 Learning 11 Listening R W 00b 3 2 Port State Port 1 These bits specify the spanni...

Page 390: ...e that is used for packets with a priority of 6 R W 11b 11 10 Priority 5 traffic Class These bits specify the egress queue that is used for packets with a priority of 5 R W 10b 9 8 Priority 4 traffic...

Page 391: ...Registers will still count these packets as filtered and the Switch Engine Interrupt Pending Register SWE_IPR will still register a drop interrupt R W 0b 7 5 Sniffer Port These bits specify the sniff...

Page 392: ...r 1847h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 6 RESERVED RO 5 4 Ingress Port Type Port 2 A setting of 11b enables the usage of the VLAN tag to specify the packet destination All other values d...

Page 393: ...rt 2 R W 0b 25 18 Broadcast Throttle Level Port 2 These bits specify the number of bytes x 64 allowed to be received per every 1 72mS interval R W 02h 17 Broadcast Throttle Enable Port 1 This bit enab...

Page 394: ...er is used to allow access to a VLAN even if the ingress port is not a member Register 1849h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 3 RESERVED RO 2 0 Admit Non Member When set a received packet...

Page 395: ...ble via the Switch Engine Ingress Rate Command Register SWE_INGRSS_RATE_CMD is used to configure the ingress rate metering coloring Register 184Ah Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 3 RESER...

Page 396: ...S DESCRIPTION TYPE DEFAULT 31 8 RESERVED RO 7 Ingress Rate RnW These bits specify a read 1 or write 0 command R W 0b 6 5 Type These bits select between the ingress rate metering color table registers...

Page 397: ...Burst token buckets are initialized to this default value If a lower value is programmed into this register the token buckets will need to be normally depleted below this value before this value has...

Page 398: ...tch Engine Ingress Rate Command Status Register SWE_INGRSS_RATE_CMD_STS This register indicates the current ingress rate command status Register 184Ch Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 1 R...

Page 399: ..._DATA This register is used to write the ingress rate table registers Register 184Dh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 0 Data This is the data to be written to the ingres...

Page 400: ...E_RD_DATA This register is used to read the ingress rate table registers Register 184Eh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 0 Data This is the read data from the ingress ra...

Page 401: ...at ingress on Port 0 Host MAC This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting which are counted separately Register...

Page 402: ...ered at ingress on Port 1 This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting which are counted separately Register 1851h...

Page 403: ...ered at ingress on Port 2 This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting which are counted separately Register 1852h...

Page 404: ...ION TYPE DEFAULT 31 24 RESERVED RO 23 21 Regen7 These bits specify the regenerated priority for received priority 7 R W 7h 20 18 Regen6 These bits specify the regenerated priority for received priorit...

Page 405: ...ON TYPE DEFAULT 31 24 RESERVED RO 23 21 Regen7 These bits specify the regenerated priority for received priority 7 R W 7h 20 18 Regen6 These bits specify the regenerated priority for received priority...

Page 406: ...ON TYPE DEFAULT 31 24 RESERVED RO 23 21 Regen7 These bits specify the regenerated priority for received priority 7 R W 7h 20 18 Regen6 These bits specify the regenerated priority for received priority...

Page 407: ...number of MAC addresses on Port 0 Host MAC that were not learned or were overwritten by a different address due to address table space limitations Register 1858h Size 32 bits BITS DESCRIPTION TYPE DEF...

Page 408: ...he number of MAC addresses on Port 1 that were not learned or were overwritten by a different address due to address table space limitations Register 1859h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 3...

Page 409: ...he number of MAC addresses on Port 2 that were not learned or were overwritten by a different address due to address table space limitations Register 185Ah Size 32 bits BITS DESCRIPTION TYPE DEFAULT 3...

Page 410: ...he Switch Engine Interrupt Pending Register SWE_IPR All Switch Engine interrupts are masked by setting the Interrupt Mask bit Clearing this bit will unmask the interrupts Refer to Chapter 5 System Int...

Page 411: ...ut the source port was not in the forwarding state 0011 The destination address was found in the ALR table but the destination port was not in the forwarding state 0100 The destination address was fou...

Page 412: ...n set bits 14 9 are valid RC 0b 7 4 Drop Reason A When bit 1 is set these bits indicate the reason a packet was dropped See the Drop Reason B description above for definitions of each value of this fi...

Page 413: ...FF_FFFC when read R W 0b 5 Fixed Priority Queue Servicing When set output queues are serviced with a fixed priority ordering When cleared output queues are serviced with a weighted round robin orderin...

Page 414: ...SCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 8 Drop Level Low These bits specify the buffer limit that can be used per ingress port during times when 2 or 3 ports are active Each buffer is 128 bytes No...

Page 415: ...kpressure is sent Register 1C02h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 8 Pause Level Low These bits specify the buffer usage level during times when 2 or 3 ports are active E...

Page 416: ...value of 1 is sent Register 1C03h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 8 Resume Level Low These bits specify the buffer usage level during times when 2 or 3 ports are active...

Page 417: ...Buffer Level Register BM_BCST_LVL This register configures the buffer usage limits for broadcasts multicasts and unknown unicasts Register 1C04h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 8 RESERV...

Page 418: ...Manager that were received on Port 0 Host MAC This count includes packets dropped due to buffer space limits and ingress rate limit discarding Red and random Yellow dropping Register 1C05h Size 32 bit...

Page 419: ...fer Manager that were received on Port 1 This count includes packets dropped due to buffer space limits and ingress rate limit discarding Red and random Yellow dropping Register 1C06h Size 32 bits BIT...

Page 420: ...fer Manager that were received on Port 2 This count includes packets dropped due to buffer space limits and ingress rate limit discarding Red and random Yellow dropping Register 1C07h Size 32 bits BIT...

Page 421: ...itialized by the reset process Note 14 63 The default value of this bit is 0 immediately following any switch fabric reset and then self sets to 1 once the ALR table is initialized Register 1C08h Size...

Page 422: ...card Table Write Data Register BM_RNDM_DSCRD_TBL_WDATA should be written before writing this register Register 1C09h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 5 RESERVED RO 4 Random Discard Weight...

Page 423: ...alized by the host Register 1C0Ah Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 10 RESERVED RO 9 0 Drop Probability These bits specify the discard probability of a packet that has been colored Yellow...

Page 424: ...10 RESERVED RO 9 0 Drop Probability These bits specify the discard probability of a packet that has been colored Yellow by the ingress metering The probability is given in 1 1024 s For example a setti...

Page 425: ...ress port The Change Tag bit also needs to be set The un tag bit in the VLAN table for the incoming VLAN ID also needs to be cleared otherwise the tag will be removed instead Priority tagged packets w...

Page 426: ...ve R W 0b 4 Change VLAN ID Port 0 Host MAC Identical to Change VLAN ID Port 2 definition above R W 0b 3 Change Priority Port 0 Host MAC Identical to Change Priority Port 2 definition above R W 0b 2 Ch...

Page 427: ...e the egress rate pacing Register 1C0Dh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 26 RESERVED RO 25 13 Egress Rate Port 0 Priority Queue 1 These bits specify the egress data rate for the Port 0 Ho...

Page 428: ...e the egress rate pacing Register 1C0Eh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 26 RESERVED RO 25 13 Egress Rate Port 0 Priority Queue 3 These bits specify the egress data rate for the Port 0 Ho...

Page 429: ...configure the egress rate pacing Register 1C0Fh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 26 RESERVED RO 25 13 Egress Rate Port 1 Priority Queue 1 These bits specify the egress data rate for the...

Page 430: ...configure the egress rate pacing Register 1C10h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 26 RESERVED RO 25 13 Egress Rate Port 1 Priority Queue 3 These bits specify the egress data rate for the...

Page 431: ...configure the egress rate pacing Register 1C11h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 26 RESERVED RO 25 13 Egress Rate Port 2 Priority Queue 1 These bits specify the egress data rate for the...

Page 432: ...configure the egress rate pacing Register 1C12h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 26 RESERVED RO 25 13 Egress Rate Port 2 Priority Queue 3 These bits specify the egress data rate for the...

Page 433: ...LAN_MII This register is used to specify the default VLAN ID and priority of Port 0 Host MAC Register 1C13h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 15 RESERVED RO 14 12 Default Priority These bi...

Page 434: ...r BM_VLAN_1 This register is used to specify the default VLAN ID and priority of Port 1 Register 1C14h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 15 RESERVED RO 14 12 Default Priority These bits sp...

Page 435: ...r BM_VLAN_2 This register is used to specify the default VLAN ID and priority of Port 2 Register 1C15h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 15 RESERVED RO 14 12 Default Priority These bits sp...

Page 436: ...r of packets received on Port 0 Host MAC that were dropped by the Buffer Manager due to ingress rate limit discarding Red and random Yellow dropping Register 1C16h Size 32 bits BITS DESCRIPTION TYPE D...

Page 437: ...he number of packets received on Port 1 that were dropped by the Buffer Manager due to ingress rate limit discarding Red and random Yellow dropping Register 1C17h Size 32 bits BITS DESCRIPTION TYPE DE...

Page 438: ...he number of packets received on Port 2 that were dropped by the Buffer Manager due to ingress rate limit discarding Red and random Yellow dropping Register 1C18h Size 32 bits BITS DESCRIPTION TYPE DE...

Page 439: ...e Buffer Manager Interrupt Pending Register BM_IPR All Buffer Manager interrupts are masked by setting the Interrupt Mask bit Clearing this bit will unmask the interrupts Refer to Chapter 5 System Int...

Page 440: ...t 7 is set these bits indicate the source port on which the packet was dropped 00 Port 0 01 Port 1 10 Port 2 11 RESERVED RC 00b 7 Status B Pending When set bits 13 8 are valid RC 0b BIT VALUES DESCRIP...

Page 441: ...et these bits indicate the reason a packet was dropped See the Drop Reason B description above for definitions of each value of this field RC 0h 2 1 Source port A When bit 0 is set these bits indicate...

Page 442: ...r is switched on or off In addition voltage transients on the AC power line may appear on the DC output If this possibility exists it is suggested that a clamp circuit be used Note 15 2 This rating do...

Page 443: ...supply voltage as well as external source sink current requirements Table 15 1 Supply and Current 10BASE T Full Duplex PARAMETER TYPICAL 3 3V MAXIMUM 3 6V UNIT Supply current at 3 3V VDD33A1 VDD33A2 V...

Page 444: ...5 10 1 18 1 6 420 3 6 1 35 1 8 485 10 3 V V V V mV uA pF Schmitt trigger Schmitt trigger Note 15 6 O8 Type Buffers Low Output Level High Output Level VOL VOH VDD33IO 0 4 0 4 V V IOL 8mA IOH 8mA OD8 Ty...

Page 445: ...Note The I2C timing adheres to the Philips I2 C Bus Specification Refer to the Philips I2 C Bus Specification for detailed I2C timing information 15 5 1 Equivalent Test Load Output timing specificatio...

Page 446: ...pecified Please refer to Section 4 2 Resets on page 36 for additional information Note Device configuration straps are latched as a result of nRST assertion Refer to Section 4 2 4 Configuration Straps...

Page 447: ...ents must be met Note Configuration straps must only be pulled high or low Configuration straps must not be driven as inputs Note Device configuration straps are also latched as a result of nRST asser...

Page 448: ...RD are de asserted These signals may be asserted and de asserted in any order Figure 15 4 PIO Read Cycle Timing Table 15 8 PIO Read Cycle Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS tcycle Read...

Page 449: ...d and de asserted in any order Note A 1 must toggle fresh data is supplied each time A 1 toggles Figure 15 5 PIO Burst Read Cycle Timing Table 15 9 PIO Burst Read Cycle Timing Values SYMBOL DESCRIPTIO...

Page 450: ...D are de asserted They may be asserted and de asserted in any order Figure 15 6 RX Data FIFO Direct PIO Read Cycle Timing Table 15 10 RX Data FIFO Direct PIO Read Cycle Timing Values SYMBOL DESCRIPTIO...

Page 451: ...asserted in any order Note A 1 must toggle fresh data is supplied each time A 1 toggles Figure 15 7 RX Data FIFO Direct PIO Burst Read Cycle Timing Table 15 11 RX Data FIFO Direct PIO Burst Read Cycl...

Page 452: ...ycle ends when either or both nCS and nWR are de asserted These signals may be asserted and de asserted in any order Figure 15 8 PIO Write Cycle Timing Table 15 12 PIO Write Cycle Timing Values SYMBOL...

Page 453: ...cycle ends when either or both nCS and nWR are de asserted They may be asserted and de asserted in any order Figure 15 9 TX Data FIFO Direct PIO Write Cycle Timing Table 15 13 TX Data FIFO Direct PIO...

Page 454: ...ycle time 1110 1130 nS tckh EECLK high time 550 570 nS tckl EECLK low time 550 570 nS tcshckh EECS high before rising edge of EECLK 1070 nS tcklcsl EECLK falling edge to EECS low 30 nS tdvckh EEDO val...

Page 455: ...ng Note 15 14 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802 3 as 50 PPM Note 15 15 This number includes the pad the bond wire and the lead frame PCB capacitance is n...

Page 456: ...VTQFP Package Definition Table 16 1 LAN9311 128 VTQFP Dimensions MIN NOMINAL MAX REMARKS A 1 20 Overall Package Height A1 0 05 0 15 Standoff A2 0 95 1 00 1 05 Body Thickness D E 15 80 16 00 16 20 X Y...

Page 457: ...the flat section of the lead foot between 0 10 and 0 25mm from the lead tip The base metal is exposed at the lead tip 3 Dimensions D1 and E1 do not include mold protrusions Maximum allowed protrusion...

Page 458: ...Managed Ethernet Switch with 16 Bit Non PCI CPU Interface Datasheet Revision 1 4 08 19 08 458 SMSC LAN9311 LAN9311i DATASHEET 16 2 128 XVTQFP Package Outline Figure 16 3 LAN9311 LAN9311i 128 XVTQFP Pa...

Page 459: ...nsions D2 and E2 represent the size of the exposed pad The exposed pad shall be coplanar with the bottom of the package within 0 05mm 5 The pin 1 identifier may vary but is always located within the z...

Page 460: ...e WUEN bit of the HMAC_WUCSR register a broadcast wake up frame will wake up the device despite the state of the Disable Broadcast Frames BCAST bit in the HMAC_CR register HMAC_WUCSR register Fixed er...

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