SMSC FlexPWR LAN8720 Specification Sheet Download Page 3

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Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support

Datasheet

SMSC LAN8720/LAN8720i

Revision 1.0 (05-28-09)

DATASHEET

Table of Contents

Chapter 1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1

General Terms and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.1

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1

Package Pin-out Diagram and Signal Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 3

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1

MAC Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2

LED Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3

Management Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4

General Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5

10/100 Line Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6

Analog Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.7

Power Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chapter 4

Architecture Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1

Top Level Functional Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2

100Base-TX Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2.1

100M Transmit Data Across the MII/RMII Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.2

4B/5B Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2.3

Scrambling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2.4

NRZI and MLT3 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2.5

100M Transmit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2.6

100M Phase Lock Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3

100Base-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.1

100M Receive Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3.2

Equalizer, Baseline Wander Correction and Clock and Data Recovery . . . . . . . . . . . . . 21

4.3.3

NRZI and MLT-3 Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.4

Descrambling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.5

Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.6

5B/4B Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.7

Receive Data Valid Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.8

Receiver Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3.9

100M Receive Data Across the MII/RMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4

10Base-T Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.1

10M Transmit Data Across the MII/RMII Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4.2

Manchester Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4.3

10M Transmit Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.5

10Base-T Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5.1

10M Receive Input and Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.5.2

Manchester Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.5.3

10M Receive Data Across the MII/RMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.5.4

Jabber Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.6

MAC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.6.1

RMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.7

Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.7.1

REF_CLK In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.7.2

REF_CLK OUT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Summary of Contents for FlexPWR LAN8720

Page 1: ...uters Digital Video Recorders IP and Video Phones Wireless Access Points Digital Televisions Digital Media Adaptors Servers Gaming Consoles POE Applications Key Benefits High Performance 10 100 Ethern...

Page 2: ...e Agreement The product may contain design defects or errors known as anomalies which may cause the product s functions to deviate from published specifications Anomaly sheets are available upon reque...

Page 3: ...I RMII Interface 18 4 2 2 4B 5B Encoding 19 4 2 3 Scrambling 20 4 2 4 NRZI and MLT3 Encoding 20 4 2 5 100M Transmit Driver 20 4 2 6 100M Phase Lock Loop PLL 21 4 3 100Base TX Receive 21 4 3 1 100M Rec...

Page 4: ...nk Integrity Test 50 5 3 5 Power Down modes 50 5 3 6 Reset 51 5 3 7 LED Description 51 5 3 8 Loopback Operation 51 5 3 9 Configuration Signals 53 Chapter 6 AC Electrical Characteristics 55 6 1 Serial...

Page 5: ...Small Footprint RMII 10 100 Ethernet Transceiver with HP Auto MDIX Support Datasheet SMSC LAN8720 LAN8720i 5 Revision 1 0 05 28 09 DATASHEET Chapter 9 Package Outline 76 Chapter 10 Revision History 79...

Page 6: ...ure 5 1 Near end Loopback Block Diagram 52 Figure 5 2 Far Loopback Block Diagram 52 Figure 5 3 Connector Loopback Block Diagram 53 Figure 6 1 SMI Timing Diagram 55 Figure 6 2 100M RMII Receive Timing...

Page 7: ...able 5 13 Register 25 Vendor Specific 38 Table 5 14 Symbol Error Counter Register 26 Vendor Specific 38 Table 5 15 Special Control Status Indications Register 27 Vendor Specific 39 Table 5 16 Special...

Page 8: ...ues 50MHz REF_CLK OUT 63 Table 6 10 RMII CLKIN REF_CLK Timing Values 63 Table 6 11 Reset Timing Values 64 Table 6 12 LAN8720 LAN8720i Crystal Specifications 65 Table 7 1 Maximum Conditions 66 Table 7...

Page 9: ...implements Auto Negotiation to automatically determine the best possible speed and duplex mode of operation HP Auto MDIX support allows using a direct connect LAN cable or a cross over path cable The...

Page 10: ...to disable the linear regulator to optimize system designs that have a 1 2V power supply available This allows for the use of a high efficiency external regulator for lower system power dissipation 1...

Page 11: ...ualizer Analog to Digital 100M PLL Squelch Filters 10M PLL Receive Section Central Bias HP Auto MDIX Management Control SMI RMII Logic TXP TXN TXD 1 0 TXEN RXD 1 0 RXER CRS_DV MDC MDIO LED1 LED2 LED C...

Page 12: ...e Pin out Diagram and Signal Table Figure 2 1 LAN8720 LAN8720i 24 QFN Pin Assignments TOP VIEW VDD2A LED2 nINTSEL LED1 REGOFF XTAL2 XTAL1 CLKIN RXD1 MODE1 RXD0 MDE0 VDDIO RXER PHYAD0 TXD1 MDC TXEN nRS...

Page 13: ...9 DATASHEET Table 2 1 LAN8720 LAN8720i 24 PIN QFN Pinout PIN NO PIN NAME PIN NO PIN NAME 1 VDD2A 13 MDC 2 LED2 nINTSEL 14 nINT REFCLKO 3 LED1 REGOFF 15 nRST 4 XTAL2 16 TXEN 5 XTAL1 CLKIN 17 TXD0 6 VDD...

Page 14: ...ent unconnected inputs from floating and must not be relied upon to drive signals external to LAN8720 LAN8720i When connected to a load that must be pulled high or low an external resistor must be add...

Page 15: ...presently being transferred from the PHY The RXER signal is optional in RMII Mode This signal is mux d with PHYAD0 See Section 5 3 9 1 for information on the ADDRESS options CRS_DV MODE2 11 IOPU RMII...

Page 16: ...NAME 24 QFN PIN TYPE DESCRIPTION MDIO 12 IOD8 Management Data Input OUTPUT Serial management data input output MDC 13 I8 Management Clock Serial management clock Table 3 5 General Signals 24 QFN SIGN...

Page 17: ...k resistor to ground connected as described in the Analog Layout Guidelines The nominal voltage is 1 2V and therefore the resistor will dissipate approximately 1mW of power Table 3 8 Power Signals 24...

Page 18: ...h major block is explained below 4 2 1 100M Transmit Data Across the MII RMII Interface For MII the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate valid data The...

Page 19: ...clearing bit 6 of register 31 When the encoding is bypassed the 5th transmit data bit is equivalent to TXER Note that encoding can be bypassed only when the MAC interface is configured to operate in...

Page 20: ...represents a code bit 1 and the logic output remaining at the same level represents a code bit 0 4 2 5 100M Transmit Driver The MLT3 data is then passed to the analog transmitter which drives the dif...

Page 21: ...P section compensates for phase and amplitude distortion caused by the physical channel consisting of magnetics connectors and CAT 5 cable The equalizer can restore the signal for any good quality CAT...

Page 22: ...the start of a packet Once the code word alignment is determined it is stored and utilized until the next start of frame 4 3 6 5B 4B Decoding The 5 bit code groups are translated into 4 bit data nibb...

Page 23: ...o received signal it is derived from the system reference clock XTAL1 CLKIN When tracking the received data RXCLK has a maximum jitter of 0 8ns provided that the jitter of the input clock XTAL1 CLKIN...

Page 24: ...ere it is shaped and filtered before being driven out as a differential signal across the TXP and TXN outputs 4 5 10Base T Receive The 10Base T receiver gets the Manchester encoded analog signal from...

Page 25: ...ounts increase The management interface MDIO MDC is identical to MII The RMII interface has the following characteristics It is capable of supporting 10Mb s and 100Mb s data rates A single clock refer...

Page 26: ...per receive signal decoding takes place 4 7 Reference Clock The LAN8720 is designed to operate in one of two available modes as shown in Table 4 2 During start up the LAN8720 monitors the LED2 nINTSEL...

Page 27: ...would normally be required for 50MHz The MAC must be capable of operating with an external clock to take advantage of this feature as shown in Figure 4 5 The LAN8720 is a small size low pin count dev...

Page 28: ...n be used to generate the REF_CLK to the MAC as shown in Figure 4 6 It is important to note that in this specific Figure 4 5 LAN8720 sources REF_CLK from a 25MHz crystal LAN8720 10 100 PHY 24 QFN RMII...

Page 29: ...s and automatically selecting the highest performance mode of operation supported by both sides Auto negotiation is fully defined in clause 28 of the IEEE 802 3 specification Once auto negotiation has...

Page 30: ...ability according to the bits set in register 4 of the SMI registers There are 4 possible matches of the technology abilities In the order of priority these are 100M Full Duplex Highest priority 100M...

Page 31: ...ations Once the break_link_timer is done in the Auto negotiation state machine approximately 1200ms the auto negotiation will re start The Link Partner will have also dropped the link due to lack of a...

Page 32: ...istor If the LED pin is pulled high by the internal pull up resistor to select a logical high for nINTSEL then the LED output will be active low If the LED pin is pulled low by an external pull down r...

Page 33: ...or REGOFF then the LED output will be active low If the LED pin is pulled low by the internal pull down resistor to select a logical low for REGOFF the LED output will then be an active high output To...

Page 34: ...e 802 3 standard as well as vendor specific registers 16 to 31 allowed by the specification Non supported registers 7 to 15 will be read as hexadecimal FFFF At the system level there are 2 signals MDI...

Page 35: ...4 11 MDIO Timing and Frame Structure WRITE Cycle MDC MDI0 Read Cycle 32 1 s 0 1 1 0 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 D1 D15 D14 D0 Preamble Start of Frame OP Code PHY Address Register Address Turn Aroun...

Page 36: ...ic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100Base T4 100Base TX Full Duplex 100Base TX Half Duplex 10Base T Full Duplex 10Base T Half Duplex Reserved A N Complete Remote Fault A N Ability Link Status J...

Page 37: ...bility Register Register 5 Extended 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Next Page Acknowledge Remote Fault Reserved Pause 100Base T4 100Base TX Full Duplex 100Base TX 10Base T Full Duplex 10Base T I...

Page 38: ...ARLOOPBACK RSVD ALTINT RSVD PHYADBP Force Good Link Status ENERGYON RSVD Table 5 11 Special Modes Register 18 Vendor Specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MIIMODE Reserved MODE PHYAD...

Page 39: ...ntrol Register 28 Vendor Specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Table 5 17 Interrupt Source Flags Register 29 Vendor Specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INT7 INT6...

Page 40: ...ster Basic 2 PHY Identifier 1 Extended 3 PHY Identifier 2 Extended 4 Auto Negotiation Advertisement Register Extended 5 Auto Negotiation Link Partner Ability Register Extended 6 Auto Negotiation Expan...

Page 41: ...0 normal operation RW 0 0 10 Isolate 1 electrical isolation of transceiver from MII 0 normal operation RW 0 0 9 Restart Auto Negotiate 1 restart auto negotiate process 0 normal operation Bit is self c...

Page 42: ...18th bits of the Organizationally Unique Identifier OUI respectively OUI 00800Fh RW 0007h Table 5 24 Register 3 PHY Identifier 2 ADDRESS NAME DESCRIPTION MODE DEFAULT 3 15 10 PHY ID Number Assigned to...

Page 43: ...t Page 1 Next Page capable 0 no Next Page ability This Phy does not support next page ability RO 0 5 14 Acknowledge 1 link code word received from partner 0 link code word not yet received RO 0 5 13 R...

Page 44: ...AME DESCRIPTION MODE DEFAULT 16 15 10 Reserved RO 0 16 9 6 Silicon Revision Four bit silicon revision identifier RO 0001 16 5 0 Reserved RO 0 Table 5 29 Register 17 Mode Control Status ADDRESS NAME DE...

Page 45: ...d Write as 0 ignore on read RW 0 18 14 Reserved Write as 1 ignore on read RW NASR 1 18 13 8 Reserved Write as 0 ignore on read RW NASR 000000 18 7 5 MODE Transceiver Mode of operation Refer to Section...

Page 46: ...e as 0 Ignore on read RW 000000 27 4 XPOL Polarity state of the 10Base T 0 Normal polarity 1 Reversed polarity RO 0 27 3 0 Reserved Reserved RO XXXXb Table 5 33 Register 28 Special Internal Testabilit...

Page 47: ...egotiation done indication 0 Auto negotiation is not done or disabled or not active 1 Auto negotiation is done Note This is a duplicate of register 1 5 however reads to register 31 do not clear status...

Page 48: ...will be asserted When the corresponding Event to De Assert nINT is true then the nINT will be de asserted Note 5 1 If the mask bit is enabled and nINT has been de asserted while ENERGYON is still high...

Page 49: ...is plugged in ENERGYON 17 1 goes active and nINT will be asserted low To de assert the nINT interrupt output either 1 Clear the ENERGYON bit 17 1 by removing the cable then writing a 1 to register 29...

Page 50: ...able this pulse by setting bit 11 in register 27 5 3 3 Isolate Mode The LAN8720 data paths may be electrically isolated from the MII by setting register 0 bit 10 to a logic one In isolation mode the t...

Page 51: ...are not cleared by Software reset and these are marked NASR in the register tables The SMI registers are not reset by the power down modes described in Section 5 3 5 For the first 16us after coming ou...

Page 52: ...regardless of the state of TXEN 5 3 8 2 Far Loopback Far loopback is a special test mode for MDI analog loopback as indicated by the blue arrows in Figure 5 3 The far loopback mode is enabled by setti...

Page 53: ...sing hardware configuration to either the value 0 or 1 The user can configure the PHY address using Software Configuration if an address greater than 1 is required The PHY address can be written after...

Page 54: ...1 100Base TX Full Duplex Auto negotiation disabled CRS is active during Receive 1001 N A 100 100Base TX Half Duplex is advertised Auto negotiation enabled CRS is active during Transmit Receive 1100 01...

Page 55: ...rial Management Interface SMI Timing The Serial Management Interface is used for status and control as described in Section 4 14 Figure 6 1 SMI Timing Diagram Table 6 1 SMI Timing Values PARAMETER DES...

Page 56: ...be provided to the LAN8720 CLKIN pin For more information on REF_CLK IN Mode see Section 4 7 1 6 2 1 RMII 100Base T TX RX Timings 50MHz REF_CLK IN 6 2 1 1 100M RMII Receive Timing 50MHz REF_CLK IN Fi...

Page 57: ...K IN Figure 6 3 100M RMII Transmit Timing Diagram 50MHz REF_CLK IN Table 6 3 100M RMII Transmit Timing Values 50MHz REF_CLK IN PARAMETER DESCRIPTION MIN TYP MAX UNITS NOTES T8 1 Transmit signals requi...

Page 58: ...F_CLK IN 6 2 2 1 10M RMII Receive Timing 50MHz REF_CLK IN Figure 6 4 10M RMII Receive Timing Diagram 50MHz REF_CLK IN Table 6 4 10M RMII Receive Timing Values 50MHz REF_CLK IN PARAMETER DESCRIPTION MI...

Page 59: ...IN Figure 6 5 10M RMII Transmit Timing Diagram 50MHz REF_CLK IN Table 6 5 10M RMII Transmit Timing Values 50MHz REF_CLK IN PARAMETER DESCRIPTION MIN TYP MAX UNITS NOTES T10 1 Transmit signals require...

Page 60: ...tor must be provided to the LAN8720 For more information on 50MHz REF_CLK OUT mode see Section 4 7 2 6 3 1 RMII 100Base T TX RX Timings 50MHz REF_CLK OUT 6 3 1 1 100M RMII Receive Timing 50MHz REF_CLK...

Page 61: ...T Figure 6 7 100M RMII Transmit Timing Diagram 50MHz REF_CLK OUT Table 6 7 100M RMII Transmit Timing Values 50MHz REF_CLK OUT PARAMETER DESCRIPTION MIN TYP MAX UNITS NOTES T12 1 Transmit signals requi...

Page 62: ...CLK OUT 6 3 2 1 10M RMII Receive Timing 50MHz REF_CLK OUT Figure 6 8 10M RMII Receive Timing Diagram 50MHz REF_CLK OUT Table 6 8 10M RMII Receive Timing Values 50MHz REF_CLK OUT PARAMETER DESCRIPTION...

Page 63: ...ransmit Timing Values 50MHz REF_CLK OUT PARAMETER DESCRIPTION MIN TYP MAX UNITS NOTES T14 1 Transmit signals required setup to rising edge of REFCLKO 7 ns T14 2 Transmit signals required hold after ri...

Page 64: ...ble 6 11 Reset Timing Values PARAMETER DESCRIPTION MIN TYP MAX UNITS NOTES T11 1 Reset Pulse Width 100 us T11 2 Configuration input setup to nRST rising 200 ns T11 3 Configuration input hold after nRS...

Page 65: ...te 6 5 85o C for extended commercial version 85o C for industrial version Note 6 6 This number includes the pad the bond wire and the lead frame PCB capacitance is not included in this value The XTAL1...

Page 66: ...have Table 7 1 Maximum Conditions PARAMETER CONDITIONS MIN TYP MAX UNITS COMMENT VDD1A VDD2A VDDIO Power pins to all other pins 0 5 3 6 V Digital IO To VSS ground 0 5 3 6 V Table 7 6 VSS VSS to all o...

Page 67: ...strike Both air discharge and contact discharge test techniques for applying stress conditions are defined by the IEC61000 4 2 ESD document AIR DISCHARGE To perform this test a charged electrode is mo...

Page 68: ...tion on 50MHz REF_CLK OUT mode see Section 4 7 2 Table 7 4 Power Consumption Device Only REF_CLK IN MODE POWER PIN GROUP VDDA3 3 POWER PINS MA VDDCR POWER PIN MA VDDIO POWER PIN MA TOTAL CURRENT MA TO...

Page 69: ...lexPWR features activated VDDIO 1 8V and internal regulator disabled Note 7 4 Current measurements do not include power applied to the magnetics or the optional external LEDs 10BASE T W TRAFFIC Max 9...

Page 70: ...Interface Signals NAME VIH V VIL V IOH IOL VOL V VOH V TXD0 0 68 VDDIO 0 4 VDDIO TXD1 0 68 VDDIO 0 4 VDDIO TXEN 0 68 VDDIO 0 4 VDDIO TXCLK 8 mA 8 mA 0 4 VDDIO 0 4 RXD0 MODE0 8 mA 8 mA 0 4 VDDIO 0 4 RX...

Page 71: ...VIL V IOH IOL VOL V VOH V LED1 REGOFF 0 63 VDD2A 0 39 VDD2A 12 mA 12 mA 0 4 VDD2A 0 4 LED2 nINTSEL 0 63 VDD2A 0 39 VDD2A 12 mA 12 mA 0 4 VDD2A 0 4 Table 7 9 Configuration Inputs NAME VIH V VIL V IOH I...

Page 72: ...2 100Base TX Transceiver Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Peak Differential Output Voltage High VPPH 950 1050 mVpk Note 7 6 Peak Differential Output Voltage Low VPPL 950 1050 m...

Page 73: ...tion Notes 8 1 Application Diagram The LAN8720 requires few external components The voltage on the magnetics center tap can range from 2 5 3 3V 8 1 1 RMII Diagram Figure 8 1 Simplified Application Dia...

Page 74: ...stem Diagram for Power Figure 8 5 Copper Interface Diagram LAN8720 24 QFN RBIAS 24 VSS 19 12k VDD1A nRST 15 CBYPASS 1 CBYPASS VDD2A VDDIO CBYPASS CF VDDDIO Supply 1 8 3 3V Analog Supply 3 3V C 9 Power...

Page 75: ...tasheet SMSC LAN8720 LAN8720i 75 Revision 1 0 05 28 09 DATASHEET 8 2 Magnetics Selection For a list of magnetics selected to operate with the SMSC LAN8720 please refer to the Application note AN 8 13...

Page 76: ...onal but must be located within the zone indicated 4 Coplanarity zone applies to exposed pad and terminals Figure 9 1 LAN8720 LAN8720i EZK 24 QFN Package Outline 4 x 4 x 0 9 mm Body Lead Free Table 9...

Page 77: ...Small Footprint RMII 10 100 Ethernet Transceiver with HP Auto MDIX Support Datasheet SMSC LAN8720 LAN8720i 77 Revision 1 0 05 28 09 DATASHEET Figure 9 1 QFN 4x4 Taping Dimensions and Part Orientation...

Page 78: ...otprint RMII 10 100 Ethernet Transceiver with HP Auto MDIX Support Datasheet Revision 1 0 05 28 09 78 SMSC LAN8720 LAN8720i DATASHEET Note Standard reel size is 4000 pieces per reel Figure 9 2 Reel Di...

Page 79: ...t Datasheet SMSC LAN8720 LAN8720i 79 Revision 1 0 05 28 09 DATASHEET Chapter 10 Revision History Table 10 1 Customer Revision History REVISION LEVEL DATE SECTION FIGURE ENTRY CORRECTION Rev 1 0 05 28...

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