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SMSC FlexPWR LAN8710, Specification Sheet

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SMSC FlexPWR LAN8710 Specification Sheet Download Page 70

MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR

® 

 Technology in a Small Footprint

Datasheet

Revision 1.0 (04-15-09)

70

SMSC LAN8710/LAN8710i

DATASHEET

Note 7.3

These levels apply when a 0-3.3V Clock is driven into XTAL1/CLKIN and XTAL2 is floating.
The maximum input voltage on XTAL1/CLKIN is VDD2A + 0.4V.

Table 7.6  LAN Interface Signals

NAME

V

IH

V

IL

I

OH

 

I

OL

 

V

OL

V

OH

TXP

See 

Table 7.11, “100Base-TX Transceiver Characteristics,” on page 71

 and 

Table 7.12, 

“10BASE-T Transceiver Characteristics,” on page 72

.

TXN

RXP

RXN

Table 7.7  LED Signals

NAME

V

IH

 (V)

V

IL

 (V)

I

OH

 

I

OL

 

V

OL

 (V)

V

OH

 (V)

LED1/REGOFF

0.63 * VDD2A

0.39 * VDD2A

-12 mA

+12 mA

+0.4

VDD2A – +0.4

LED2/nINTSEL

0.63 * VDD2A

0.39 * VDD2A

-12 mA

+12 mA

+0.4

VDD2A – +0.4

Table 7.8  Configuration Inputs

NAME

V

IH

 (V)

V

IL

 (V)

I

OH

 

I

OL

 

V

OL

 (V)

V

OH

 (V)

RXD0/MODE0

0.63 * VDDIO

0.39 * VDDIO

-8 mA

+8 mA

+0.4

VDDIO – +0.4

RXD1/MODE1

0.63 * VDDIO

0.39 * VDDIO

-8 mA

+8 mA

+0.4

VDDIO – +0.4

RXD2/RMIISEL

0.63 * VDDIO

0.39 * VDDIO

-8 mA

+8 mA

+0.4

VDDIO – +0.4

RXD3/PHYAD2

0.63 * VDDIO

0.39 * VDDIO

-8 mA

+8 mA

+0.4

VDDIO – +0.4

RXER/RXD4/PHYAD0

0.63 * VDDIO

0.39 * VDDIO

-8 mA

+8 mA

+0.4

VDDIO – +0.4

RXCLK/PHYAD1

0.63 * VDDIO

0.39 * VDDIO

-8 mA

+8 mA

+0.4

VDDIO – +0.4

COL/CRS_DV/MODE2

0.63 * VDDIO

0.39 * VDDIO

-8 mA

+8 mA

+0.4

VDDIO – +0.4

Table 7.9  General Signals

NAME

V

IH

 (V)

V

IL

 (V)

I

OH

 

I

OL

 

V

OL

 (V)

V

OH

 (V)

nINT/TXER/TXD4

-8 mA

+8 mA

+0.4

VDDIO – +0.4

nRST

0.63 * VDDIO

0.39 * VDDIO

XTAL1/CLKIN (

Note 7.3

)

+1.40 V

0.39 * VDD2A

XTAL2

-

-

Summary of Contents for FlexPWR LAN8710

Page 1: ...Modems Routers DSL Modems Routers Digital Video Recorders IP and Video Phones Wireless Access Points Digital Televisions Digital Media Adaptors Servers Gaming Consoles POE Applications Key Benefits Hi...

Page 2: ...SC s standard Terms of Sale Agreement dated before the date of your order the Terms of Sale Agreement The product may contain design defects or errors known as anomalies which may cause the product s...

Page 3: ...Across the MII RMII Interface 19 4 2 2 4B 5B Encoding 20 4 2 3 Scrambling 21 4 2 4 NRZI and MLT3 Encoding 21 4 2 5 100M Transmit Driver 21 4 2 6 100M Phase Lock Loop PLL 22 4 3 100Base TX Receive 22 4...

Page 4: ...errupt System 48 5 3 Miscellaneous Functions 48 5 3 1 Carrier Sense 48 5 3 2 Collision Detect 49 5 3 3 Isolate Mode 49 5 3 4 Link Integrity Test 49 5 3 5 Power Down modes 49 5 3 6 Reset 50 5 3 7 LED D...

Page 5: ...ceiver with HP Auto MDIX and flexPWR Technology in a Small Footprint Datasheet SMSC LAN8710 LAN8710i 5 Revision 1 0 04 15 09 DATASHEET 8 1 3 Twisted Pair Interface Diagram 74 8 2 Magnetics Selection 7...

Page 6: ...gram 51 Figure 5 3 Connector Loopback Block Diagram 52 Figure 6 1 SMI Timing Diagram 55 Figure 6 2 100M MII Receive Timing Diagram 56 Figure 6 3 100M MII Transmit Timing Diagram 57 Figure 6 4 10M MII...

Page 7: ...fic 37 Table 5 13 Register 25 Vendor Specific 37 Table 5 14 Symbol Error Counter Register 26 Vendor Specific 37 Table 5 15 Special Control Status Indications Register 27 Vendor Specific 38 Table 5 16...

Page 8: ...REF_CLK IN 62 Table 6 9 10M RMII Transmit Timing Values 50MHz REF_CLK IN 63 Table 6 10 RMII CLKIN REF_CLK Timing Values 64 Table 6 11 Reset Timing Values 64 Table 6 12 LAN8710 LAN8710i Crystal Specifi...

Page 9: ...e pins are tolerant to 3 6V The LAN8710 LAN8710i implements Auto Negotiation to automatically determine the best possible speed and duplex mode of operation HP Auto MDIX support allows using a direct...

Page 10: ...ailable to disable the linear regulator to optimize system designs that have a 1 2V power supply available This allows for the use of a high efficiency external regulator for lower system power dissip...

Page 11: ...log to Digital 100M PLL Squelch Filters 10M PLL Receive Section Central Bias HP Auto MDIX Management Control SMI RMII MII Logic TXP TXN TXD 0 3 TXEN TXER TXCLK RXD 0 3 RXDV RXER RXCLK CRS COL CRS_DV M...

Page 12: ...gure 2 1 LAN8710 LAN8710i 32 QFN Pin Assignments TOP VIEW VDD2A LED2 nINTSEL LED1 REGOFF XTAL2 XTAL1 CLKIN VDDCR RXD3 PHYAD2 RXCLK PHYAD1 RXD2 RMIISEL RXD1 MODE1 RXD0 MDE0 VDDIO RXER RXD4 PHYAD0 CRS M...

Page 13: ...i 32 PIN QFN Pinout PIN NO PIN NAME PIN NO PIN NAME 1 VDD2A 17 MDC 2 LED2 nINTSEL 18 nINT TXER TXD4 3 LED1 REGOFF 19 nRST 4 XTAL2 20 TXCLK 5 XTAL1 CLKIN 21 TXEN 6 VDDCR 22 TXD0 7 RXCLK PHYAD1 23 TXD1...

Page 14: ...at must be pulled high or low an external resistor must be added Note The digital signals are not 5V tolerant They are variable voltage from 1 6V to 3 6V as shown in Table 7 1 3 1 MAC Interface Signal...

Page 15: ...O8 Transmit Clock Used to latch data from the MAC into the transceiver MII 100BT 25MHz MII 10BT 2 5MHz This signal is not used in RMII Mode RXD0 MODE0 11 IOPU RXD0 Receive Data 0 Bit 0 of the 4 data...

Page 16: ...MODE2 15 IOPU COL MII Mode Collision Detect Asserted to indicate detection of collision condition CRS_DV RMII Mode CRS_DV Carrier Sense Receive Data Valid Asserted to indicate when the receive medium...

Page 17: ...ation on pin nINT TXER TXD4 See Section 4 10 for additional information Table 3 4 Management Signals 32 QFN SIGNAL NAME 32 QFN PIN TYPE DESCRIPTION MDIO 16 IOD8 Management Data Input OUTPUT Serial man...

Page 18: ...or will dissipate approximately 1mW of power Table 3 8 Power Signals 32 QFN SIGNAL NAME 32 QFN PIN TYPE DESCRIPTION VDDIO 12 P 1 6V to 3 6V Variable I O Pad Power VDDCR 6 P 1 2V Core voltage 1 2V for...

Page 19: ...xplained below 4 2 1 100M Transmit Data Across the MII RMII Interface For MII the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate valid data The data is latched b...

Page 20: ...bypassed by clearing bit 6 of register 31 When the encoding is bypassed the 5th transmit data bit is equivalent to TXER Note that encoding can be bypassed only when the MAC interface is configured to...

Page 21: ...logic level represents a code bit 1 and the logic output remaining at the same level represents a code bit 0 4 2 5 100M Transmit Driver The MLT3 data is then passed to the analog transmitter which dr...

Page 22: ...for phase and amplitude distortion caused by the physical channel consisting of magnetics connectors and CAT 5 cable The equalizer can restore the signal for any good quality CAT 5 cable between 1m a...

Page 23: ...SSD pair at the start of a packet Once the code word alignment is determined it is stored and utilized until the next start of frame 4 3 6 5B 4B Decoding The 5 bit code groups are translated into 4 b...

Page 24: ...f there is no received signal it is derived from the system reference clock XTAL1 CLKIN When tracking the received data RXCLK has a maximum jitter of 0 8ns provided that the jitter of the input clock...

Page 25: ...ansmitter where it is shaped and filtered before being driven out as a differential signal across the TXP and TXN outputs 4 5 10Base T Receive The 10Base T receiver gets the Manchester encoded analog...

Page 26: ...received transmitted data is present on the 4 bit receive transmit bus The device must be configured in MII or RMII mode This is done by specific pin strapping configurations See Section 4 6 3 MII vs...

Page 27: ...id to be detected Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which presents the first di bit of a nibble onto RXD 1 0 i e CRS_DV is deasserted only o...

Page 28: ...on is to automatically configure the transceiver to the optimum link parameters based on the capabilities of its link partner Auto negotiation is a mechanism for exchanging configuration information b...

Page 29: ...ses which may be present or absent contain the data word being transmitted Presence of a data pulse represents a 1 while absence represents a 0 The data transmitted by an FLP burst is known as a Link...

Page 30: ...ed by signal loss This may occur because of a cable break or because of an interruption in the signal transmitted by the Link Partner Auto negotiation resumes in an attempt to determine the new link c...

Page 31: ...gulator a pullup strapping resistor is connected from LED1 REGOFF to VDD2A At power on after both VDDIO and VDD2A are within specification the transceiver will sample the LED1 REGOFF pin to determine...

Page 32: ...s float the pin to set nINTSEL high or pull down the pin with an external resistor to GND to set nINTSEL low See Figure 4 5 The LED2 nINTSEL pin is latched on the rising edge of the nRST The default s...

Page 33: ...s in the transceiver operation 4 14 Transceiver Management Control The Management Control module includes 3 blocks Serial Management Interface SMI Management Registers Set Interrupt 4 14 1 Serial Mana...

Page 34: ...ng edges is 400 ns These modest timing requirements allow this interface to be easily driven by the I O port of a microcontroller The data on the MDIO line is latched on the rising edge of the MDC The...

Page 35: ...gister 1 Basic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100Base T4 100Base TX Full Duplex 100Base TX Half Duplex 10Base T Full Duplex 10Base T Half Duplex Reserved A N Complete Remote Fault A N Ability L...

Page 36: ...Base Page Ability Register Register 5 Extended 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Next Page Acknowledge Remote Fault Reserved Pause 100Base T4 100Base TX Full Duplex 100Base TX 10Base T Full Duple...

Page 37: ...EN MDPREBP FARLOOPBACK RSVD ALTINT RSVD PHYADBP Force Good Link Status ENERGYON RSVD Table 5 11 Special Modes Register 18 Vendor Specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MIIMODE Reserve...

Page 38: ...stability Control Register 28 Vendor Specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Table 5 17 Interrupt Source Flags Register 29 Vendor Specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserve...

Page 39: ...Status Register Basic 2 PHY Identifier 1 Extended 3 PHY Identifier 2 Extended 4 Auto Negotiation Advertisement Register Extended 5 Auto Negotiation Link Partner Ability Register Extended 6 Auto Negot...

Page 40: ...r down mode 0 normal operation RW 0 0 10 Isolate 1 electrical isolation of transceiver from MII 0 normal operation RW 0 0 9 Restart Auto Negotiate 1 restart auto negotiate process 0 normal operation B...

Page 41: ...3rd through 18th bits of the Organizationally Unique Identifier OUI respectively OUI 00800Fh RW 0007h Table 5 24 Register 3 PHY Identifier 2 ADDRESS NAME DESCRIPTION MODE DEFAULT 3 15 10 PHY ID Number...

Page 42: ...ULT 5 15 Next Page 1 Next Page capable 0 no Next Page ability This Phy does not support next page ability RO 0 5 14 Acknowledge 1 link code word received from partner 0 link code word not yet received...

Page 43: ...on ADDRESS NAME DESCRIPTION MODE DEFAULT 16 15 10 Reserved RO 0 16 9 6 Silicon Revision Four bit silicon revision identifier RO 0001 16 5 0 Reserved RO 0 Table 5 29 Register 17 Mode Control Status ADD...

Page 44: ...0 18 14 MIIMODE MII Mode set the mode of the digital interface as described in Section 5 3 9 3 0 MII interface 1 RMII interface RW NASR X 18 13 8 Reserved Write as 0 ignore on read RW NASR 000000 18 7...

Page 45: ...eserved Write as 0 Ignore on read RW 000000 27 4 XPOL Polarity state of the 10Base T 0 Normal polarity 1 Reversed polarity RO 0 27 3 0 Reserved Reserved RO XXXXb Table 5 33 Register 28 Special Interna...

Page 46: ...odone Auto negotiation done indication 0 Auto negotiation is not done or disabled or not active 1 Auto negotiation is done Note This is a duplicate of register 1 5 however reads to register 31 do not...

Page 47: ...nINT output will be asserted When the corresponding Event to De Assert nINT is true then the nINT will be de asserted Note 5 1 If the mask bit is enabled and nINT has been de asserted while ENERGYON i...

Page 48: ...fter a cable is plugged in ENERGYON 17 1 goes active and nINT will be asserted low To de assert the nINT interrupt output either 1 Clear the ENERGYON bit 17 1 by removing the cable then writing a 1 to...

Page 49: ...user can disable this pulse by setting bit 11 in register 27 5 3 3 Isolate Mode The LAN8710 data paths may be electrically isolated from the MII by setting register 0 bit 10 to a logic one In isolatio...

Page 50: ...gister bits are not cleared by Software reset and these are marked NASR in the register tables The SMI registers are not reset by the power down modes described in Section 5 3 5 For the first 16us aft...

Page 51: ...s are powered down regardless of the state of TXEN 5 3 8 2 Far Loopback This special test mode is only available when operating in RMII mode When the the RXD2 RMIISEL pin is configured for MII mode th...

Page 52: ...tching address in the relevant bits When a match is recognized the transceiver responds to that particular frame The PHY address is also used to seed the scrambler In a multi Transceiver application t...

Page 53: ...de is MII with the internal pull down resistor To select RMII mode pull the RXD2 RMIISEL pin high with an external resistor to VDDIO Table 5 40 MODE 2 0 Bus MODE 2 0 MODE DEFINITIONS DEFAULT REGISTER...

Page 54: ...N8710i DATASHEET When the nRST pin is deasserted the register bit 18 14 MIIMODE is loaded according to the RXD2 RMIISEL pin The mode is then configured by the register bit value When a soft reset occu...

Page 55: ...e Phy 6 1 Serial Management Interface SMI Timing The Serial Management Interface is used for status and control as described in Section 4 14 Figure 6 1 SMI Timing Diagram Table 6 1 SMI Timing Values P...

Page 56: ...1 MII 100Base T TX RX Timings 6 2 1 1 100M MII Receive Timing Figure 6 2 100M MII Receive Timing Diagram Table 6 2 100M MII Receive Timing Values PARAMETER DESCRIPTION MIN TYP MAX UNITS NOTES T2 1 Re...

Page 57: ...100M MII Transmit Timing Figure 6 3 100M MII Transmit Timing Diagram Table 6 3 100M MII Transmit Timing Values PARAMETER DESCRIPTION MIN TYP MAX UNITS NOTES T3 1 Transmit signals required setup to TXC...

Page 58: ...e T TX RX Timings 6 2 2 1 10M MII Receive Timing Figure 6 4 10M MII Receive Timing Diagram Table 6 4 10M MII Receive Timing Values PARAMETER DESCRIPTION MIN TYP MAX UNITS NOTES T4 1 Receive signals se...

Page 59: ...2 10M MII Transmit Timing Figure 6 5 10M MII Transmit Timing Diagrams Table 6 5 10M MII Transmit Timing Values PARAMETER DESCRIPTION MIN TYP MAX UNITS NOTES T5 1 Transmit signals required setup to TX...

Page 60: ...RMII 100Base T TX RX Timings 50MHz REF_CLK IN 6 3 1 1 100M RMII Receive Timing 50MHz REF_CLK IN Figure 6 6 100M RMII Receive Timing Diagram 50MHz REF_CLK IN Table 6 6 100M RMII Receive Timing Values 5...

Page 61: ...50MHz REF_CLK IN Figure 6 7 100M RMII Transmit Timing Diagram 50MHz REF_CLK IN Table 6 7 100M RMII Transmit Timing Values 50MHz REF_CLK IN PARAMETER DESCRIPTION MIN TYP MAX UNITS NOTES T8 1 Transmit s...

Page 62: ...ngs 50MHz REF_CLK IN 6 3 2 1 10M RMII Receive Timing 50MHz REF_CLK IN Figure 6 8 10M RMII Receive Timing Diagram 50MHz REF_CLK IN Table 6 8 10M RMII Receive Timing Values 50MHz REF_CLK IN PARAMETER DE...

Page 63: ...0MHz REF_CLK IN Figure 6 9 10M RMII Transmit Timing Diagram 50MHz REF_CLK IN Table 6 9 10M RMII Transmit Timing Values 50MHz REF_CLK IN PARAMETER DESCRIPTION MIN TYP MAX UNITS NOTES T10 1 Transmit sig...

Page 64: ...MHz CLKIN Frequency Drift 50 ppm CLKIN Duty Cycle 40 60 CLKIN Jitter 150 psec p p not RMS Figure 6 10 Reset Timing Diagram Table 6 11 Reset Timing Values PARAMETER DESCRIPTION MIN TYP MAX UNITS NOTES...

Page 65: ...l version Note 6 5 85o C for extended commercial version 85o C for industrial version Note 6 6 This number includes the pad the bond wire and the lead frame PCB capacitance is not included in this val...

Page 66: ...s 0 5 3 6 V Digital IO To VSS ground 0 5 3 6 V Table 7 5 MII Bus Interface Signals on page 69 VSS VSS to all other pins 0 5 0 5 V Junction to Ambient JA Thermal vias per Layout Guidelines 48 3 C W Jun...

Page 67: ...ction In addition to defining the ESD tests IEC 61000 4 2 also categorizes the impact to equipment operation when the strike occurs ESD Result Classification The LAN8710 maintains an ESD Result Classi...

Page 68: ...flexPWR features activated VDDIO 1 8V and internal regulator disabled Note 7 2 Current measurements do not include power applied to the magnetics or the optional external LEDs Table 7 4 Power Consump...

Page 69: ...VDDIO 0 39 VDDIO TXD3 0 63 VDDIO 0 39 VDDIO TXEN 0 63 VDDIO 0 39 VDDIO TXCLK 8 mA 8 mA 0 4 VDDIO 0 4 RXD0 MODE0 8 mA 8 mA 0 4 VDDIO 0 4 RXD1 MODE1 8 mA 8 mA 0 4 VDDIO 0 4 RXD2 RMIISEL 8 mA 8 mA 0 4 V...

Page 70: ...V LED1 REGOFF 0 63 VDD2A 0 39 VDD2A 12 mA 12 mA 0 4 VDD2A 0 4 LED2 nINTSEL 0 63 VDD2A 0 39 VDD2A 12 mA 12 mA 0 4 VDD2A 0 4 Table 7 8 Configuration Inputs NAME VIH V VIL V IOH IOL VOL V VOH V RXD0 MODE...

Page 71: ...up RXD1 MODE1 Pull up RXD2 RMIISEL Pull down RXD3 PHYAD2 Pull down RXER RXD4 PHYAD0 Pull down RXCLK PHYAD1 Pull down COL CRS_DV MODE2 Pull up CRS Pull down LED1 REGOFF Pull down LED2 nINTSEL Pull up M...

Page 72: ...72 SMSC LAN8710 LAN8710i DATASHEET Note 7 7 Min max voltages guaranteed as measured with 100 resistive load Table 7 12 10BASE T Transceiver Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Tr...

Page 73: ...plication Notes 8 1 Application Diagram The LAN8710 requires few external components The voltage on the magnetics center tap can range from 2 5 3 3V 8 1 1 MII Diagram Figure 8 1 Simplified Application...

Page 74: ...Level System Diagram for Power Figure 8 4 Copper Interface Diagram LAN8710 32 QFN RBIAS 32 VSS 27 12 1k VDD1A nRST 19 CBYPASS 1 CBYPASS VDD2A VDDCR VDDIO CBYPASS CF VDDDIO Supply 1 8 3 3V Analog Suppl...

Page 75: ...Footprint Datasheet SMSC LAN8710 LAN8710i 75 Revision 1 0 04 15 09 DATASHEET 8 2 Magnetics Selection For a list of magnetics selected to operate with the SMSC LAN8710 please refer to the Application n...

Page 76: ...must be located within the zone indicated 4 Coplanarity zone applies to exposed pad and terminals Figure 9 1 LAN8710 LAN8710i EZK 32 Pin QFN Package Outline 5 x 5 x 0 9 mm Body Lead Free Table 9 1 32...

Page 77: ...100 Ethernet Transceiver with HP Auto MDIX and flexPWR Technology in a Small Footprint Datasheet SMSC LAN8710 LAN8710i 77 Revision 1 0 04 15 09 DATASHEET Figure 9 1 QFN 5x5 Taping Dimensions and Part...

Page 78: ...I 10 100 Ethernet Transceiver with HP Auto MDIX and flexPWR Technology in a Small Footprint Datasheet Revision 1 0 04 15 09 78 SMSC LAN8710 LAN8710i DATASHEET Figure 9 2 Reel Dimensions for 12mm Carri...

Page 79: ...ansceiver with HP Auto MDIX and flexPWR Technology in a Small Footprint Datasheet SMSC LAN8710 LAN8710i 79 Revision 1 0 04 15 09 DATASHEET Note Standard reel size is 4000 pieces per reel Figure 9 3 Ta...

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