Functional Description
ATCA-F125 (6873M Artwork) Installation and Use (6806800J94N)
71
On-die termination support when using DDR3
Supports auto refreshing
Registered DIMM support
+1.5V DDR3 compatible interface
4.3.1
Memory Interface
The memory bus is 64-bit wide with ECC protection. It connects the P2020 QorIQ
Integrated Processor directly to the DIMM memory sockets. The memory data bus runs at
a maximum frequency of 400MHz providing a total bandwidth of 6.4Gb/s.
4.3.2
Memory Sockets
Two 240-pin DDR3 DIMM sockets are provided on the ATCA-F125 to host up to 2 Gbyte of
memory on each DIMM socket using single or dual rank DDR3 registered DIMM memory
modules.
4.3.3
Memory Modules
The ATCA-F125 requires very low profile VLP DDR3 DIMM modules in order to fit within
the maximum component height profile of an ATCA blade. The ATCA-F125 board has been
tested and qualified to operate with a 2GB DDR3 VLP RDIMM from Smart Modular. The
operating system is currently limited to 2GB of DDR3 memory
The SPD-SROM (Serial Presents Detect) on each DIMM module provides all necessary
information (speed, size, type and the like) to the boot firmware. The SPD-SROM is read
through I2C Bus connected to the P2020 QorIQ Integrated Processor.
4.3.4
Persistent Memory
On the ATCA-F125, the persistent memory is part of the DDR memory subsystem. A
dedicated register is available in the FPGA to enable or disable persistent memory by
software. If persistent memory is enabled, the memory contents of the main memory stays
unchanged after any applied reset, except power-up reset. After power-up reset the
persistent memory feature is disabled.
A special procedure needs to be followed to use the persistent memory feature. This
procedure is automatically executed by the U-Boot during initialization.
1.
Set DDR_SDRAM_CFG_2[SR_IE] bit inside the memory controller of the P2020 QorIQ
Integrated Processor.
2.
Set these fields in the PIC of P2020 QorIQ Integrated Processor:
