10
analog input channel. Figure 2.6 shows the detailed notes. The shaded portion represents the
default factory settings.
2.8
Timed trigger
Timing trigger means that the DAQ card will trigger data acquisition in accordance with the set
fixed frequency.
Figure 2.7 illustrates the implementation principle of PCI-1255 timing trigger based on the
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19
1
Internal clock of 8MHz
2
82C54 counter 0 output as OUT 0
3
82C54 counter 1 output as OUT 1
4
82C54 counter 2 gated signal as GATE 2
5
82C54 counter 0 output as OUT 0
6
82C54 counter 1 gated signal as GATE 1
7
82C54 counter 2 output as OUT 2
8
Analog input external trigger signal as EXT_TRIG
9
82C54 counter 0 clock input as CLK 0
10
82C54 counter 1 clock input as CLK 1
11
82C54 counter 2 clock input as CLK 2
12
82C54 counter 2 output as OUT 2
13
Analog input external trigger signal as EXT_TRIG
14
82C54 counter 1 output OUT 1
15
82C54 counter 0 gated signal GATE 0
16
Digital input signal DI 0
17
40-pin IDC connector input as CLK-IN 0
18
40-pin IDC connector input as CLK-IN 1
19
40-pin IDC connector input as CLK-IN 2
Attention: All signals related to 82C54 on 37-pin D-type connector and 40-pin IDC
connector are connected through logic device 7414, so the signals on the
connector will be reversed with the signals marked on the 82C54 device manual.
Figure 2.6
、
JP3 in detail
