8.3 Performance Guidelines for Outputs
Whenever a number of high frequency, fast rise time, large amplitude signals are all close to one another there will be some amount
of crosstalk. The jitter generation of the Si5391/Si5391P is so low that crosstalk can become a significant portion of the final measured
output jitter. Some of the crosstalk will come from the Si5391/Si5391P, and some will be introduced by the PCB. It is difficult (and
possibly irrelevant) to allocate the jitter portions between these two sources since the Si5391/Si5391P must be attached to a board in
order to measure jitter.
For extra fine tuning and optimization in addition to following the usual PCB layout guidelines, crosstalk can be minimized by modifying
the arrangements of different output clocks. For example, consider the following lineup of output clocks in following table.
Table 8.2. Example of Output Clock Placement
Output
Not Recommended
(Frequency MHz)
Recommended
(Frequency MHz)
0
155.52
155.52
1
156.25
155.52
2
155.52
622.08
3
156.25
Not used
4
200
156.25
5
100
156.25
6
622.08
625
7
625
Not used
8
Not used
200
9
Not used
100
Using this example, a few guidelines are illustrated:
1. Avoid adjacent frequency values that are close. For example, a 155.52 MHz clock should not be placed next to a 156.25 MHz
clock. If the jitter integration bandwidth goes up to 20 MHz then keep adjacent frequencies at least 20 MHz apart.
2. Adjacent frequency values that are integer multiples of one another are allowed, and these outputs should be grouped together
when possible. Noting that because 155.52 MHz x 4 = 622.08 MHz, it is okay to place the pair of these frequency values close to
one another.
3. Unused outputs can be used to separate clock outputs that might otherwise interfere with one another.
If some outputs have tight jitter requirements while others are relatively loose, rearrange the clock outputs so that the critical outputs
are the least susceptible to crosstalk. These guidelines need to be followed by those applications that wish to achieve the highest
possible levels of jitter performance. Because CMOS outputs have large pk-pk swings, are single ended, and do not present a balanced
load to the VDDO supplies, they generate much more crosstalk than differential outputs. For this reason, CMOS outputs should be
avoided in jitter-sensitive applications. When CMOS clocks are unavoidable, even greater care must be taken with respect to the
above guidelines. For more information on these issues, see application note,
AN862: Optimizing Jitter Performance in Next Generation
Internet Infrastructure Systems
The ClockBuilder Pro Clock Placement Wizard is an easy way to reduce crosstalk for a given frequency plan. This feature can be
accessed on the “Define Output Clocks” page of ClockBuilder Pro in the lower left hand corner of the page. It is recommended to use
this tool after each project frequency plan change.
Si5391 Reference Manual • Outputs
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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Rev. 0.5 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • January 11, 2022
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