6.1 Programming the PLL
The PLL programming involves three distinct constraints:
1. The minimum and the maximum frequencies possible for the PFD (Phase Frequency Detector) at lock. That is set by the reference
frequency which is set the input divider P and the active input clock as selected by the IN SEL pins or registers.
2. The VCO frequency that is set by feedback divider (Mn/Md) and the PFD frequency also has a limited range that is unique to
Si5357.
3. The PLL closed loop transfer function characterized by its loop band width and peaking is set by programming the loop parame-
ters.
The table below lists the constraints for the PLL reference frequency and the VCO frequency. The PLL reference frequency
(
pllRefFreq
) and the VCO frequency (
vcoFreq
) are related by the equation below:
vcoFreq
=
pllRefFreq
× (
Mn
Md
)
For a given plan, the
pllRefFreq
can be readily solved as it is derived from the input clock frequency. The first step in this optimization
should be to derive a
pllRefFreq
that is within the 10-50 MHz limit. To get to this optimization, the “active” input to the PLL must be
selected from the XA/XB, CLKIN_1 input clocks using either the IMUX_SEL register field or the CLKIN_SEL pins {if CLKIN_SEL pins
are available in the custom part that you choose to re-program}.
PllRefFreq
is given by the InFreq (active clock input frequency) and P
as:
PllRefFreq
=
InFreq
P
Table 6.1. Constraints for PLL Reference Frequency and VCO Frequency
Field Name
Value
Description
pllMinRefFreq
10 MHz
The minimum reference frequency the PLL
can tolerate
pllMaxRefFreq
50 MHz
The maximum reference frequency the PLL
can tolerate
vcoCenterFreq
2.5 GHz
The center frequency of the VCO’s tuning
range
vcoMinFreq
2.375 GHz
The minimum frequency of the VCO’s tun-
ing range
vcoMaxFreq
2.625 GHz
The maximum frequency of the VCO’s tun-
ing range
List all required output frequencies, Fx, where x = 0,1,2,3,4,5. Note that there are only “six” unique frequencies possible in the Si5357
(even though there are 12 outputs. An output pair, OUT2X, OUT2X+1 have frequency Fx) and is shown in Table5. The integer
O-dividers are denoted by hsdiv. Each Oi divider maps to a hsdivi in the solver where i is an integer between 0 and 4. Similarly, the two
Multisynth N-dividers, Nj map to IDj and j = 0 or 1.The constraints for these divider values are listed in the table below.
Si5357 Reference Manual • Programming the Volatile Memory
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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Rev. 0.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021
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