3. Powerup and Initialization
The following figure shows the powerup and initialization sequence.
Power-Up
Serial interface
ready
RST
pin asserted
Hard Reset
bit asserted
Initialization
NVM download
Soft Reset
bit asserted
Figure 3.1. Power-Up and Initialization
3.1 Reset and Initialization
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data
from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this
initialization period is complete. No clocks will be generated until the initialization is done. There are two types of resets available. A
hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be
restored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit.
A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes.
Table 3.1. Reset Registers
Register Name
Hex Address [Bit Field]
Function
Si5341
Si5340
HARD_RST
001E[1]
001E[1]
Performs the same function as power cycling the device. All regis-
ters will be restored to their default values.
SOFT_RST
001C[0]
001C[0]
Performs a soft reset. Resets the device while it does not re-
download the register configuration from NVM.
The Si541/40 is fully configurable using the serial interface (I
2
C or SPI). At power up the device downloads its default register values
from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to
generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power
supply voltages applied to its VDD (1.8 V) and VDDA (3.3 V) pins.
3.1.1 Power Supply Sequencing
If the output clocks do not need to have a specific phase/delay relationship between them the timing of the power supplies coming up
to full voltage is irrelevant. However, if the phase/delay of any output clock to any other output clock is important, then the VDDO of the
relevant clock output must come up to full voltage before VDD and VDDA voltages are applied. See . Voltage can always be applied to
the VDDS pin regardless of any output clock alignment.
Si5341, Si5340 Rev D Family Reference Manual • Powerup and Initialization
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021
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