3.4 Inputs
The Si5332 requires an external 16-50 MHz crystal at its XIN/XOUT pins or the embedded 50 MHz crystal to operate in free-run mode,
or an external input clock (CLKIN_2/CLKIN_2# or CLKIN_3/CLKIN_3#) for synchronous operation. An external crystal is not required in
synchronous mode.
3.4.1 External Reference Input (XA/XB)
An external crystal (XTAL) is used in combination with the internal oscillator (OSC) on Si5332A/B/C/D to produce a low jitter reference
for the PLL when operating in the free-run mode. The Si5332 Reference Manual provides additional information on PCB layout
recommendations for the crystal to ensure optimum jitter performance. Refer to
Table 5.4 External Crystal Input Specification (A/B/C/D
for crystal specifications.
For free-running operation, the internal oscillator can operate from a low-frequency fundamental mode crystal (XTAL) with a resonant
frequency of 16 to 50 MHz. A crystal can easily be connected to pins XA and XB without external components, as shown in the figure
below. Internal loading capacitance (CL) values from 2.5 pf to 21.5 pf can be selected via register settings. Alternatively, an external CL
can be used along with the internal CL.
Osc
To synthesis stage
or output selectors
XTAL
XA
XB
Figure 3.4. External Reference Input (XA/XB)
The Si5332E/F/G/H/L options feature an embedded 50 MHz reference crystal that is used in the free run mode.
3.4.2 Input Clocks
An input clock is available to synchronize the PLL when operating in synchronous mode. This input can be configured as LVPECL,
LVDS or HCSL differential, or LVCMOS. The recommended input termination schemes are shown in the
. Differential signals must be AC coupled. Unused inputs can be disabled by register configuration.
3.4.3 Input Selection
The active clock input is selected by register control, or by defining two universal input pins as CLKIN_SEL[1:0] in ClockBuilder Pro.
A register bit determines input selection as pin or register selectable. If there is no clock signal on the selected input at power up, the
device will not generate output clocks.
In a typical application, the Si5332 reference input is configured immediately after power-up and initialization. If the device is switched
to another input more than ±1000 ppm offset from the initial input, the device must be recalibrated manually to the new frequency,
temporarily turning off the clock outputs. After the VCO is recalibrated, the device will resume producing clock outputs. If the selected
inputs are within ±1000 ppm, any phase error difference will propagate through the device at a rate determined by the PLL bandwidth.
Hitless switching and phase build-out are not supported by the Si5332.
Si5332 Data Sheet • Functional Description
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 16, 2021
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