Skanti TRP 5000, Instruction Manual

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5.4.5 /236\ VCO
The Loop Filter and Voltage Controlled Oscillator are located o n this
printed circuit board.
The Loop Filter consists of an active4th order low pass filter and an
integrator. The purpose of the Loop Filter is to remove the pulses from
the output of the Phase/Frequency Detector on board /237\ and allow only
the DC-information to pass on to the vari-cap diodes of the VCO. The VCO
is amplitude stabilised.
The selection of one of the three bands of the VGO is carried out by
means of a decoding circuit on /237\.
5.4.6 /237\ FREQUENCY DIVIDERS A
There are two divider chains, their associated buffer amplifiers, a
2182KHz pre-selection circuit, a lock detector, and a phase 1 frequency
detector located on this printed circuit board.
The Reference Divider divides the 1.4 MHz from the TCXO by 1400, thus
providing the 1KHz reference frequency for the Phase/Frequency Detector.
The Loop Divider chain consists of four programmable, decimal counters,
IC16, IC20, IC23, and IC26, which are loaded at the end of each counting
cycle with the data blocks supplied by the Memory /238\ or the 2182 kHz
Pre-selection circuit. The Side-step Control consists of a decimal
counter, IC6, a four bit comparator, IC10, and gating circuitry. A data
block, containing the information about the 100 Hz setting is fed to the
comparator. At the end of each counting cycle IC6 is incremented by one
and its outputs (B) are compared with the content of the data block (A).
As long as B is less than A the division ratio of the four programmable
counters are equal to the BCD 9’s complement of their four associate d
data blocks. When B becomes equal to or greater than A the division
ratio is incremented by one. This change of the division ratio is
controlled by output pin 5 of IC10, which selects one of the two
decoding branches, branch 1 and branch 2, consisting of parts of IC3,
IC4, ICS, and IC8, and one half of IC1.
When the mode Fl, Al, or A2H is chosen, the division ratio is decreased
by one and two alternately, independent of the above mentioned side
stepping procedure. This is controlled by the "1.5 kHz SHIF T" line and
performed by the other half of IC1, where output pin 9 is changed at the
conclusion of each counting cycle, thus shifting between the two
decoding branches, branch 3 and branch 4, alternately. This means that
the division ratio is decreased by 1.5 on the average. Because the
reference frequency of the loop is 1 kHz, this means that the output
frequency of the loop is decreased by 1.5 kHz.
The output from the Loop Divider chains fed to the Phase / Frequency
Detector and is here compared to the fixed l KHz reference frequency. In
case of a frequency difference the detector will produce a DC-error
voltage which will correct the VCO en board /236\ to establish the
wanted frequency equality.
The two inputs /238\ -9a and /238\ -10a containing information about the
MHz setting is decoded in order to select the proper band of the VCO on
board /236\. If both of the two inputs are HIGH, the Disable output line
is activated.
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