Sinclair MrX Manual Download Page 21

Description of funtions

All functions of the SSG are controlled by the 16 internal registers. The CPU

need only write data to the internal registers of the SSG. The SSG itself
generates the sound. Sound is generated by the following blocks:

Music generator:     Square waves having a different frequency are generated

                      for each channel (A,B and C)
Noise generator:     Pseudo-random waveforms are generated (variable frequency)

Mixer:               Music and noise output are mixed for the three channels
                      (A,B and C)

Level control:       Constant level or variable level is given for each of the
                      three channels (A,B and C). Constant levels are

                      controlled by the CPU, and variable levels by the
                      envelope generator.

Envelope generator:  Generates various types of attenuation (single burst
                      attenuated and repeated attenuation)

D/A convertor:       Sound is output on each of the three channels (A,B and C)
                      at the level determined by the level control.

The CPU can read the contents of the internal registers with no effect on

sound.

    Register Array

     A9  A8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
     0   1   0   0   0   0   0   0   0   0

     0   1   0   0   0   0   1   1   1   1
    \______________________/\_____________/

         Upper addresses    Lower addresses
          (chip select)    (register select)

Of the ten bit address, the lower addresses DA3 ~ DA0 are used to select the

16 internal registers(register array). The upper addresses are used for chip
selection. A9 and A8 is programmed to 01 while DA7 through DA4 are set to

0000. When the upper addresses match this program in the address mode, a
register address (lower four bits DA3 through DA0) is fetched from the

register address latch. When the value set is in the upper addresses is
different from the program value, the bidirectional bus formed from DA7

through DA0 is driven to high impedance. A register address which has been
fetched is retained until the next address is fetched, and is not affected

by the read, write, or inactive mode.

  Register Array
                            B7....B0

R0 Frequency of Channel A   00000000   8 bit fine tone adjustment
R1                          ----0000   4 bit rough tone adjustment

R2 Frequency of Channel B   00000000   8 bit fine tone adjustment
R3                          ----0000   4 bit rough tone adjustment

R4 Frequency of Channel C   00000000   8 bit fine tone adjustment
R5                          ----0000   4 bit rough tone adjustment

R6 Frequency of Noise       ---00000   5 bit noise frequency
R7 I/O port and mixer       iinnnttt   i-I/O, n-Noise, t-Tone

   settings                 bacbacba
R8 Level of channel A       ---mllll   m-Mode, l-Level

R9 Level of channel B       ---mllll   m-Mode, l-Level
RA Level of channel C       ---mllll   m-Mode, l-Level

RB Frequency of envelope    00000000   8 bit fine adjustment
RC                          00000000   8 bit rough adjustment

RD Shape of envelope        ----cath   c-Cont, a-Att, t-Alt, h-Hold
RE Data of I/O port A       00000000   8 bit data

RF Data of I/O port B       00000000   8 bit data

Version: v005

21

Date: 22.05.2012

Summary of Contents for MrX

Page 1: ...MrX Sound Board for the ZX81 from Sinclair Manual for users and programmers www eightbits de Version v005 1 Date 22 05 2012...

Page 2: ...2 MrX Sound Card 5 3 MrX Expansion Bus K3 6 4 Optional 3 5mm jacks and ZX96 bus diodes 7 5 Connection 8 6 Software 11 7 Six Channel Sound Turbo Sound Turbo AY 12 8 Programming 15 9 The Yamaha YM2149 1...

Page 3: ...rchantability or fitness of use for a particular purpose Neither the author nor the publisher shall be held liable or responsible to any person or entity with respect to any loss or incidental or cons...

Page 4: ...1 System Requirements Computer ZX81 Manufacturer Sinclair UK Amplifier active amplifier PC amplifier with 3 5mm jack Recommended 16k Ram Version v005 4 Date 22 05 2012...

Page 5: ...2 MrX Sound Card A 3 5mm jack Connect the amplifier here B Port connector C 30 pin expansion bus K3 see next chapter D Through port connector Version v005 5 Date 22 05 2012...

Page 6: ...A5 Port A from YM2149 12 IOA4 Port A from YM2149 13 IOA3 Port A from YM2149 14 IOA2 Port A from YM2149 15 IOA1 Port A from YM2149 16 CHL Left channel of 3 5mm jack behind capacitor 17 CHR Right channe...

Page 7: ...www fischerkai de zxteam treib_e htm a diode DX1 for the BUSCS signal has to be soldered and the port connector has to be exchanged by a VG64 connector The VG64 connector uses all pins of K2 Note The...

Page 8: ...amage may occur to the computer and the sound card The ZX81 computer is connected to the sound card via the ZX expansion port on the back of the computer Make sure that the pins of the ZX81 PCB are ex...

Page 9: ...The PC speaker with integrated amplifier has to be connected with the 3 5mm stereo jack Version v005 9 Date 22 05 2012...

Page 10: ...equipment NOTE Make sure that the pins of the MrX PCB are exactly aligned with the connector of the equipment Otherwise severe damage may occur to the computer the equipment and the sound card Versio...

Page 11: ...e ZON X Manual Demon Demo Dancing Demon Demo Games 2 Games from Brasilian TK85 PT3 Player Player plays PT3 files Pink Panther Music demo ZON X Manual HTML document original zonx manual Concerning the...

Page 12: ...s not ZON X compatible any more ATTENTION The following instructions describe how to exchange the orignal GAL chip with the Turbo Sound GAL Follow the instructions carefully and exactly If you are not...

Page 13: ...igned exactly with the socket Watch the pit of the GAL it must be exactly placed like shown on the picture Press down the chip slowly until it snaps into the socket While pressing make sure that none...

Page 14: ...he MrX according to chapter 5 Connection The following combinations are tested and working Modified MrX ZXpand Zxpand AY ZX81 Modified MrX Original MrX ZX81 Connect two PC speakers with the two sound...

Page 15: ...CF 0x0F from ZON X user manual 0xDF 0x1F additional combination See chapter 9 The Yamaha YM2149 for further explanation about Latch register address latch and Data write mode Examples in assembler Sim...

Page 16: ...looop LD A 14 out LATCH A LD A 00 out DTAX A set port A to 0 LD HL DFILE INC HL LD HL _O INC HL LD HL _F INC HL LD HL _F LD BC 100 CALL 0F35 LD A 14 out LATCH A LD A FF out DTAX A set all bits of por...

Page 17: ...LATCH equ DF xxx LD A 7 out LATCH A LD A 00 set port A B to Input out DTAX A looop LD A 14 out LATCH A in a LATCH Port A register No 14 is read and a 3F LD HL DFILE INC HL LD HL A Print the port conte...

Page 18: ...supply Easy connection to 8 bit or 16 bit CPU Simple connection to external system through 2 sequence 8 bit I O port Wide voicing range of 8 octaves Smooth attenuation by 5 bit envelope generator Bui...

Page 19: ...lup resistance while A9 has pulldown resistance When the voltage level at A8 while the level at A9 and DA7 DA4 is low the address mode is selected allowing for the fetching of a register address Conne...

Page 20: ...rite mode DA7 DA0 set to input mode and data is written to register currently being addressed Read mode DA7 DA0 set to output mode and contents of register currently being addressed are output 7 ANALO...

Page 21: ...internal registers register array The upper addresses are used for chip selection A9 and A8 is programmed to 01 while DA7 through DA4 are set to 0000 When the upper addresses match this program in th...

Page 22: ...d from the register value NP decimal in the following manner fN fMaster fMaster if the frequency of the master clock 16NP Noise frequency register R6 B7 B6 B5 B4 B3 B2 B1 B0 Not used NP4 NP3 NP2 NP1 N...

Page 23: ...lope setting period value EP decimal fE fMaster fMaster if the frequency of the master clock 256EP Envelope rough adjustment register RC Envelope fine adjustment register RB B7 B6 B5 B4 B3 B2 B1 B0 B7...

Page 24: ...binations of the CONT ATT ALT and HOLD signals B3 B2 B1 B0 CONT ATT ALT HOLD 0 0 x x 0 1 x x 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 NOTE The writing to register RD will reset...

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