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Silicon Laboratories TOOLSTICK C8051F330, Manual

The SILICON LABORATORIES TOOLSTICK C8051F330 is a versatile development tool equipped with an C8051F330 microcontroller. To familiarize yourself with its functionalities and unleash its full potential, a comprehensive user manual is available for free download at manualshive.com. Expand your expertise by downloading the manual today!

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C8051F330/1/2/3/4/5

138

Rev. 1.7

15.3.2. Clock Low Extension

SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different 
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow 
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line 
LOW to extend the clock low period, effectively decreasing the serial clock frequency.

15.3.3. SCL Low Timeout

If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, 
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus 
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition. 

When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to 
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to 
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable 
and re-enable) the SMBus in the event of an SCL low timeout.

15.3.4. SCL High (SMBus Free) Timeout

The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus 
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and 
SDA remain high for more than 10 SMBus clock source periods. If the SMBus is waiting to generate a 
Master START, the START will be generated following this timeout. Note that a clock source is required for 
free timeout detection, even in a slave-only implementation.

15.4. Using the SMBus

The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides 
the following application-independent features:

•

Byte-wise serial data transfers

•

Clock signal generation on SCL (Master Mode only) and SDA data synchronization

•

Timeout/bus error recognition, as defined by the SMB0CF configuration register

•

START/STOP timing, detection, and generation

•

Bus arbitration

•

Interrupt generation

•

Status information

SMBus interrupts are generated for each data byte or slave address that is transferred. When transmitting, 
this interrupt is generated after the ACK cycle so that software may read the received ACK value; when 
receiving data, this interrupt is generated before the ACK cycle so that software may define the outgoing 
ACK value. See 

Section “15.5. SMBus Transfer Modes” on page 146

 for more details on transmission 

sequences.

Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or 
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control 
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in 

Section 

“15.4.2. SMB0CN Control Register” on page 143

; Table 15.4 provides a quick SMB0CN decoding refer-

ence.

Summary of Contents for TOOLSTICK C8051F330

Page 1: ...locks Up to 25 MIPS throughput with 25 MHz clock Expanded interrupt handler Memory 768 bytes internal data RAM 256 512 8 kB F330 1 4 kB F332 3 or 2 kB F334 5 Flash In system programmable in 512 byte Sec tors 512 bytes are reserved in the 8 kB devices Digital Peripherals 17 Port I O All 5 V tolerant with high sink current Hardware enhanced UART SMBus and enhanced SPI serial ports Four general purpo...

Page 2: ...C8051F330 1 2 3 4 5 2 Rev 1 7 ...

Page 3: ...ture Sensor 42 5 3 Modes of Operation 43 5 3 1 Starting a Conversion 44 5 3 2 Tracking Modes 45 5 3 3 Settling Time Requirements 46 5 4 Programmable Window Detector 51 5 4 1 Window Detector In Single Ended Mode 53 5 4 2 Window Detector In Differential Mode 54 6 10 Bit Current Mode DAC IDA0 C8051F330 only 57 6 1 IDA0 Output Scheduling 57 6 1 1 Update Output On Demand 57 6 1 2 Update Output Based on...

Page 4: ...emory 103 11 1 Programming The Flash Memory 103 11 1 1 Flash Lock and Key Functions 103 11 1 2 Flash Erase Procedure 103 11 1 3 Flash Write Procedure 104 11 2 Non volatile Data Storage 104 11 3 Security Options 105 11 4 Flash Write and Erase Guidelines 107 11 4 1 VDD Maintenance and the VDD monitor 107 11 4 2 PSWE Maintenance 107 11 4 3 System Clock 108 12 External RAM 111 13 Oscillators 113 13 1 ...

Page 5: ...6 1 Enhanced Baud Rate Generation 154 16 2 Operational Modes 155 16 2 1 8 Bit UART 155 16 2 2 9 Bit UART 156 16 3 Multiprocessor Communications 156 17 Enhanced Serial Peripheral Interface SPI0 163 17 1 Signal Descriptions 164 17 1 1 Master Out Slave In MOSI 164 17 1 2 Master In Slave Out MISO 164 17 1 3 Serial Clock SCK 164 17 1 4 Slave Select NSS 164 17 2 SPI0 Master Mode Operation 165 17 3 SPI0 ...

Page 6: ...dules 195 19 2 1 Edge triggered Capture Mode 196 19 2 2 Software Timer Compare Mode 197 19 2 3 High Speed Output Mode 198 19 2 4 Frequency Output Mode 199 19 2 5 8 Bit Pulse Width Modulator Mode 200 19 2 6 16 Bit Pulse Width Modulator Mode 201 19 3 Watchdog Timer Mode 201 19 3 1 Watchdog Timer Operation 202 19 3 2 Watchdog Timer Usage 203 19 4 Register Descriptions for PCA 204 20 C2 Interface 209 ...

Page 7: ...Diagram Top View 37 5 10 Bit ADC ADC0 C8051F330 2 4 only Figure 5 1 ADC0 Functional Block Diagram 41 Figure 5 2 Typical Temperature Sensor Transfer Function 43 Figure 5 3 10 Bit ADC Track and Conversion Example Timing 45 Figure 5 4 ADC0 Equivalent Input Circuits 46 Figure 5 5 ADC Window Compare Example Right Justified Single Ended Data 53 Figure 5 6 ADC Window Compare Example Left Justified Single...

Page 8: ...ence 149 Figure 15 8 Typical Slave Transmitter Sequence 150 16 UART0 Figure 16 1 UART0 Block Diagram 153 Figure 16 2 UART0 Baud Rate Logic 154 Figure 16 3 UART Interconnect Diagram 155 Figure 16 4 8 Bit UART Timing Diagram 155 Figure 16 5 9 Bit UART Timing Diagram 156 Figure 16 6 UART Multi Processor Mode Interconnect Diagram 157 17 Enhanced Serial Peripheral Interface SPI0 Figure 17 1 SPI Block D...

Page 9: ...Figure 19 1 PCA Block Diagram 193 Figure 19 2 PCA Counter Timer Block Diagram 194 Figure 19 3 PCA Interrupt Block Diagram 195 Figure 19 4 PCA Capture Mode Diagram 196 Figure 19 5 PCA Software Timer Mode Diagram 197 Figure 19 6 PCA High Speed Output Mode Diagram 198 Figure 19 7 PCA Frequency Output Mode 199 Figure 19 8 PCA 8 Bit PWM Mode Diagram 200 Figure 19 9 PCA 16 Bit PWM Mode 201 Figure 19 10 ...

Page 10: ...C8051F330 1 2 3 4 5 10 Rev 1 7 ...

Page 11: ...ce Electrical Characteristics 63 8 Comparator0 Table 8 1 Comparator Electrical Characteristics 70 9 CIP 51 Microcontroller Table 9 1 CIP 51 Instruction Set Summary 73 Table 9 2 Special Function Register SFR Memory Map 79 Table 9 3 Special Function Registers 80 Table 9 4 Interrupt Summary 88 10 Reset Sources Table 10 1 Reset Electrical Characteristics 102 11 Flash Memory Table 11 1 Flash Electrical...

Page 12: ...ator 161 Table 16 5 Timer Settings for Standard Baud Rates Using an External 11 0592 MHz Oscillator 162 Table 16 6 Timer Settings for Standard Baud Rates Using an External 3 6864 MHz Oscillator 162 17 Enhanced Serial Peripheral Interface SPI0 Table 17 1 SPI Slave Timing Parameters 175 18 Timers 19 Programmable Counter Array Table 19 1 PCA Timebase Input Options 194 Table 19 2 PCA0CPM Register Sett...

Page 13: ...er High Byte 83 SFR Definition 9 3 SP Stack Pointer 83 SFR Definition 9 4 PSW Program Status Word 84 SFR Definition 9 5 ACC Accumulator 85 SFR Definition 9 6 B B Register 85 SFR Definition 9 7 IE Interrupt Enable 89 SFR Definition 9 8 IP Interrupt Priority 90 SFR Definition 9 9 EIE1 Extended Interrupt Enable 1 91 SFR Definition 9 10 EIP1 Extended Interrupt Priority 1 92 SFR Definition 9 11 IT01CF ...

Page 14: ... Byte 184 SFR Definition 18 5 TL1 Timer 1 Low Byte 184 SFR Definition 18 6 TH0 Timer 0 High Byte 184 SFR Definition 18 7 TH1 Timer 1 High Byte 184 SFR Definition 18 8 TMR2CN Timer 2 Control 187 SFR Definition 18 9 TMR2RLL Timer 2 Reload Register Low Byte 188 SFR Definition 18 10 TMR2RLH Timer 2 Reload Register High Byte 188 SFR Definition 18 11 TMR2L Timer 2 Low Byte 188 SFR Definition 18 12 TMR2H...

Page 15: ...C8051F330 1 2 3 4 5 Rev 1 7 15 C2 Register Definition 20 4 FPCTL C2 Flash Programming Control 210 C2 Register Definition 20 5 FPDAT C2 Flash Programming Data 210 ...

Page 16: ...C8051F330 1 2 3 4 5 16 Rev 1 7 ...

Page 17: ...hip solutions The Flash memory can be reprogrammed even in circuit providing non volatile data storage and also allowing field upgrades of the 8051 firmware User software has complete control of all peripherals and may individually shut down any or all peripherals for power savings The on chip Silicon Labs 2 Wire C2 Development Interface allows non intrusive uses no on chip resources full speed in...

Page 18: ...PI UART Timers 16 bit Programmable Counter Array Digital Port I Os 10 bit 200ksps ADC 10 bit Current Output DAC Internal Voltage Reference Temperature Sensor Analog Comparator Lead free RoHS Compliant Package C8051F330 GM 25 8 768 4 17 QFN 20 C8051F331 GM 25 8 768 4 17 QFN 20 C8051F332 GM 25 4 768 4 17 QFN 20 C8051F333 GM 25 4 768 4 17 QFN 20 C8051F334 GM 25 2 768 4 17 QFN 20 C8051F335 GM 25 2 768...

Page 19: ... RX P0 6 CNVSTR P0 7 VDD GND RST C2CK Brown Out P 1 D r v P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 SPI Port 1 Latch 512 byte XRAM P2 0 C2D Port 2 Latch VREF 80 kHz Internal Oscillator 10 bit DAC Port 0 Latch UART 8 kB FLASH 256 byte SRAM POR SFR Bus 8 0 5 1 C o r e Timer 0 1 2 3 3 Chnl PCA WDT P 0 D r v X B A R Reset XTAL1 XTAL2 External Oscillator Circuit System Clock 24 5 MHz 2 Internal Oscillato...

Page 20: ...P0 5 RX P0 6 CNVST P0 7 VDD GND RST C2CK Brown Out P 1 D r v P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 SPI Port 1 Latch 512 byte XRAM P2 0 C2D Port 2 Latch VREF 80 kHz Internal Oscillator Port 0 Latch UART 4 kB FLASH 256 byte SRAM POR SFR Bus 8 0 5 1 C o r e Timer 0 1 2 3 3 Chnl PCA WDT P 0 D r v X B A R Reset XTAL1 XTAL2 External Oscillator Circuit System Clock 24 5 MHz 2 Internal Oscillator Analog...

Page 21: ...P0 5 RX P0 6 CNVST P0 7 VDD GND RST C2CK Brown Out P 1 D r v P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 SPI Port 1 Latch 512 byte XRAM P2 0 C2D Port 2 Latch VREF 80 kHz Internal Oscillator Port 0 Latch UART 2 kB FLASH 256 byte SRAM POR SFR Bus 8 0 5 1 C o r e Timer 0 1 2 3 3 Chnl PCA WDT P 0 D r v X B A R Reset XTAL1 XTAL2 External Oscillator Circuit System Clock 24 5 MHz 2 Internal Oscillator Analog...

Page 22: ...dard 8051 architecture In a standard 8051 all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12 to 24 MHz By contrast the CIP 51 core exe cutes 70 of its instructions in one or two system clock cycles with only four instructions taking more than four system clock cycles The CIP 51 has a total of 109 instructions The table below shows...

Page 23: ...er in software The WDT may be permanently enabled in soft ware after a power on reset during MCU initialization The internal oscillator factory calibrated to 24 5 MHz 2 This internal oscillator period may be user pro grammed in 0 5 increments An additional low frequency oscillator is also available which facilitates low power operation An external oscillator drive circuit is included allowing an e...

Page 24: ... See Figure 1 9 for the MCU system mem ory map Figure 1 9 On Board Memory Map C8051F330 1 PROGRAM DATA MEMORY FLASH Direct and Indirect Addressing 0x00 0x7F Upper 128 RAM Indirect Addressing Only 0x80 0xFF Special Function Register s Direct Addressing Only DATA MEMORY RAM General Purpose Registers 0x1F 0x20 0x2F Bit Addressable Lower 128 RAM Direct and Indirect Addressing 0x30 INTERNAL DATA ADDRES...

Page 25: ... all the hardware and software necessary to develop applica tion code and perform in circuit debugging with the C8051F330 1 2 3 4 5 MCUs The kit includes software with a developer s studio and debugger an integrated 8051 assembler and a debug adapter It also has a target application board with the associated MCU installed and prototyping area plus the required cables and wall mount power supply Th...

Page 26: ...other digital sig nals in the controller can be configured to appear on the Port I O pins specified in the Crossbar Control registers This allows the user to select the exact mix of general purpose Port I O and digital resources needed for the particular application Figure 1 11 Digital Crossbar Diagram 1 5 Serial Ports The C8051F330 1 2 3 4 5 Family includes an SMBus I2C interface a full duplex UA...

Page 27: ...ality where the PCA is clocked by an external source while the internal oscillator drives the system clock Each capture compare module can be configured to operate in one of six modes Edge Triggered Capture Software Timer High Speed Output 8 or 16 bit Pulse Width Modulator or Frequency Output Additionally Capture Compare Module 2 offers watchdog timer WDT capabilities Following a system reset Modu...

Page 28: ...nals Conversion completions are indicated by a status bit and an interrupt if enabled The resulting 10 bit data word is latched into the ADC data SFRs upon completion of a conversion Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is either within or outside of a specified range The ADC can monitor a key voltage continuously in back ground mode...

Page 29: ...teresis are also configurable Comparator interrupts may be generated on rising falling or both edges When in IDLE mode these inter rupts may be used as a wake up source Comparator0 may also be configured as a reset source Figure 1 15 shows the Comparator0 block diagram Figure 1 15 Comparator0 Block Diagram VDD CPT0CN Reset Decision Tree Crossbar Q Q SET CLR D Q Q SET CLR D SYNCHRONIZER GND CP0 P0 ...

Page 30: ...A IDA0 features a flexible output update mechanism which allows for seamless full scale changes and sup ports jitter free updates for waveform generation Three update modes are provided allowing IDA0 output updates on a write to IDA0H on a Timer overflow or on an external pin edge Figure 1 16 IDA0 Functional Block Diagram IDA0 10 IDA0 IDA0CN IDA0EN IDA0CM2 IDA0CM1 IDA0CM0 IDA0OMD1 IDA0OMD0 IDA0H I...

Page 31: ...ND 0 3 4 2 V Maximum Total current through VDD or GND 500 mA Maximum output current sunk by RST or any Port pin 100 mA Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is n...

Page 32: ...LK High Time 18 ns TSYSL SYSCLK Low Time 18 ns Specified Operating Temperature Range 40 85 C Digital Supply Current CPU Active Normal Mode fetching instructions from Flash IDD Note 3 VDD 3 6 V F 25 MHz 10 7 11 7 mA VDD 3 0 V F 25 MHz 7 8 8 3 mA VDD 3 0 V F 1 MHz 0 38 mA VDD 3 0 V F 80 kHz 31 µA IDD Supply Sensitivity Note 3 F 25 MHz 65 V F 1 MHz 61 V IDD Frequency Sensitivity Note 3 Note 4 VDD 3 0...

Page 33: ...SYSCLK must be at least 32 kHz to enable debugging 3 Based on device characterization data Not production tested 4 IDD can be estimated for frequencies 15 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range When using these numbers to estimate IDD for 15 MHz the estimate should be the current at 25 MHz minus the difference in current indicated by ...

Page 34: ...No ADC0 Electrical Characteristics 55 IDAC Electrical Characteristics 60 Voltage Reference Electrical Characteristics 63 Comparator Electrical Characteristics 70 Reset Electrical Characteristics 102 Flash Electrical Characteristics 104 Internal Oscillator Electrical Characteristics 122 Port I O DC Electrical Characteristics 134 ...

Page 35: ... See Section 7 for a complete descrip tion P0 1 IDA0 20 3 D I O or A In AOut Port 0 1 See Section 14 for a complete description IDA0 Output See Section 6 for a complete description P0 2 XTAL1 19 2 D I O or A In A In Port 0 2 See Section 14 for a complete description External Clock Input This pin is the external oscillator return for a crystal or resonator See Section 13 for a com plete description...

Page 36: ... 1 See Section 14 for a complete description P1 2 11 14 D I O or A In Port 1 2 See Section 14 for a complete description P1 3 10 13 D I O or A In Port 1 3 See Section 14 for a complete description P1 4 9 12 D I O or A In Port 1 4 See Section 14 for a complete description P1 5 8 11 D I O or A In Port 1 5 See Section 14 for a complete description P1 6 7 10 D I O or A In Port 1 6 See Section 14 for a...

Page 37: ...igure 4 1 QFN 20 Pinout Diagram Top View 3 4 5 1 2 8 9 10 6 7 13 12 11 15 14 18 19 20 16 17 P0 0 GND VDD RST C2CK P2 0 C2D P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 C8051F330 1 2 3 4 5 GM Top View GND ...

Page 38: ...5 ddd 0 05 e 0 50 BSC eee 0 08 E 4 00 BSC Z 0 43 E2 2 00 2 15 2 25 Y 0 18 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 220 variation VGGD except for custom features D2 E2 Z Y and L which are toleranced per supplier designation 4 Recommended card reflow profil...

Page 39: ...sk defined NSMD Clearance between the solder mask and the metal pad is to be 60 μm minimum all the way around the pad Stencil Design 5 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 6 The stencil thickness should be 0 125 mm 5 mils 7 The ratio of stencil aperture to land pad size should be 1 1 for all perimeter pin...

Page 40: ...C8051F330 1 2 3 4 5 40 Rev 1 7 ...

Page 41: ... supply VDD Any of the fol lowing may be selected as the negative input Ports0 1 VREF or GND When GND is selected as the negative input ADC0 operates in Single ended Mode all other times ADC0 operates in Differential Mode The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in SFR Definition 5 1 and SFR Definition 5 2 The conversion code format differs between Single ...

Page 42: ...y the Digital Crossbar To configure a Port pin for analog input set to 0 the corresponding bit in register PnMDIN for n 0 1 To force the Crossbar to skip a Port pin set to 1 the corresponding bit in register PnSKIP for n 0 1 See Section 14 Port Input Output on page 123 for more Port I O configuration details 5 2 Temperature Sensor The typical temperature sensor transfer function is shown in Figure...

Page 43: ...ation ADC0 has a maximum conversion speed of 200 ksps The ADC0 conversion clock is a divided version of the system clock determined by the AD0SC bits in the ADC0CF register system clock divided by AD0SC 1 for 0 AD0SC 31 0 50 50 100 Celsius 0 500 0 600 0 700 0 800 0 900 Volts VTEMP 2 86 TEMPC 776 mV 1 000 ...

Page 44: ...falling edge of AD0BUSY triggers an interrupt when enabled and sets the ADC0 interrupt flag AD0INT Note When polling for ADC conversion completions the ADC0 interrupt flag AD0INT should be used Converted data is available in the ADC0 data registers ADC0H ADC0L when bit AD0INT is logic 1 Note that when Timer 2 or Timer 3 overflows are used as the conversion source Low Byte over flows are used if Ti...

Page 45: ...rsion begins on the rising edge of CNVSTR see Figure 5 3 Tracking can also be disabled shutdown when the device is in low power standby or sleep modes Low power track and hold mode is also useful when AMUX settings are frequently changed due to the settling time requirements described in Section 5 3 3 Settling Time Requirements on page 46 Figure 5 3 10 Bit ADC Track and Conversion Example Timing W...

Page 46: ...des Notice that the equivalent time constant for both input circuits is the same The required ADC0 settling time for a given settling accuracy SA may be approximated by Equation 5 1 When measuring the Temperature Sensor output or VDD with respect to GND RTOTAL reduces to RMUX See Table 5 1 for ADC0 minimum settling time requirements Equation 5 1 ADC0 Settling Time Requirements Where SA is the sett...

Page 47: ...W R W R W R W Reset Value AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 00011111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xBB AMX0P4 0 ADC0 Positive Input 00000 P0 0 00001 P0 1 00010 P0 2 00011 P0 3 00100 P0 4 00101 P0 5 00110 P0 6 00111 P0 7 01000 P1 0 01001 P1 1 01010 P1 2 01011 P1 3 01100 P1 4 01101 P1 5 01110 P1 6 01111 P1 7 10000 Temp Sensor 10001 VDD 10010 11111 no input selected ...

Page 48: ...Negative Input selections ADC0 operates in Differential mode R R R R W R W R W R W R W Reset Value AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00011111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xBA AMX0N4 0 ADC0 Negative Input 00000 P0 0 00001 P0 1 00010 P0 2 00011 P0 3 00100 P0 4 00101 P0 5 00110 P0 6 00111 P0 7 01000 P1 0 01001 P1 1 01010 P1 2 01011 P1 3 01100 P1 4 01101 P1 5 01110 P1 6 01111 ...

Page 49: ... R W R W R R Reset Value AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJST 11111000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xBC AD0SC SYSCLK CLKSAR 1 Bits7 0 ADC0 Data Word High Order Bits For AD0LJST 0 Bits 7 2 are the sign extension of Bit1 Bits 1 0 are the upper 2 bits of the 10 bit ADC0 Data Word For AD0LJST 1 Bits 7 0 are the most significant bits of the 10 bit ADC0 Data Word R W R W R ...

Page 50: ...tch has occurred Bits2 0 AD0CM2 0 ADC0 Start of Conversion Mode Select When AD0TM 0 000 ADC0 conversion initiated on every write of 1 to AD0BUSY 001 ADC0 conversion initiated on overflow of Timer 0 010 ADC0 conversion initiated on overflow of Timer 2 011 ADC0 conversion initiated on overflow of Timer 1 100 ADC0 conversion initiated on rising edge of external CNVSTR 101 ADC0 conversion initiated on...

Page 51: ...L and Less Than ADC0LTH ADC0LTL registers hold the comparison values The window detector flag can be programmed to indicate when mea sured data is inside or outside of the user programmed limits depending on the contents of the ADC0 Less Than and ADC0 Greater Than registers SFR Definition 5 7 ADC0GTH ADC0 Greater Than Data High Byte SFR Definition 5 8 ADC0GTL ADC0 Greater Than Data Low Byte Bits7 ...

Page 52: ...han Data Low Byte Bits7 0 High byte of ADC0 Less Than Data Word R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xC6 Bits7 0 Low byte of ADC0 Less Than Data Word R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xC5 ...

Page 53: ... comparison values Figure 5 5 ADC Window Compare Example Right Justified Single Ended Data Figure 5 6 ADC Window Compare Example Left Justified Single Ended Data 0x03FF 0x0081 0x0080 0x007F 0x0041 0x0040 0x003F 0x0000 0 Input Voltage Px x GND VREF x 1023 1024 VREF x 128 1024 VREF x 64 1024 AD0WINT 1 AD0WINT not affected AD0WINT not affected ADC0LTH ADC0LTL ADC0GTH ADC0GTL 0x03FF 0x0081 0x0080 0x00...

Page 54: ... data with the same comparison values Figure 5 7 ADC Window Compare Example Right Justified Differential Data Figure 5 8 ADC Window Compare Example Left Justified Differential Data 0x01FF 0x0041 0x0040 0x003F 0x0000 0xFFFF 0xFFFE 0x0200 VREF Input Voltage Px x Px x VREF x 511 512 VREF x 64 512 VREF x 1 512 0x01FF 0x0041 0x0040 0x003F 0x0000 0xFFFF 0xFFFE 0x0200 VREF Input Voltage Px x Px x VREF x ...

Page 55: ... Distortion Up to the 5th harmonic 67 dB Spurious Free Dynamic Range 78 dB Conversion Rate SAR Conversion Clock 3 MHz Conversion Time in SAR Clocks 10 clocks Track Hold Acquisition Time 300 ns Throughput Rate 200 ksps Analog Inputs ADC Input Voltage Range Single Ended AIN GND Differential AIN AIN 0 VREF VREF VREF V V Absolute Pin Voltage with respect to GND Single Ended or Differential 0 VDD V Inp...

Page 56: ...C8051F330 1 2 3 4 5 56 Rev 1 7 ...

Page 57: ...ree updates for waveform generation Three update modes are provided allowing IDAC output updates on a write to IDA0H on a Timer overflow or on an external pin edge 6 1 1 Update Output On Demand In its default mode IDA0CN 6 4 111 the IDA0 output is updated on demand on a write to the high byte of the IDA0 data register IDA0H It is important to note that writes to IDA0L are held in this mode and hav...

Page 58: ...DA0H are held until an edge occurs on the CNVSTR input pin The particular setting of the IDA0CM bits determines whether IDAC outputs are updated on rising falling or both edges of CNVSTR When a corresponding edge occurs the IDA0H IDA0L contents are copied to the IDAC input latches allowing the IDAC output to change to the new value 6 2 IDAC Output Mapping The IDAC data registers IDA0H and IDA0L ar...

Page 59: ...tes on falling edge of CNVSTR 110 DAC output updates on any edge of CNVSTR 111 DAC output updates on write to IDA0H Bits 3 2 Unused Read 00b Write don t care Bits 1 0 IDA0OMD 1 0 IDA0 Output Mode Select bits 00 0 5 mA full scale output current 01 1 0 mA full scale output current 1x 2 0 mA full scale output current R W R W R W R W R R R W R W Reset Value IDA0EN IDA0CM IDA0OMD 01110010 Bit7 Bit6 Bit...

Page 60: ...e Output Current 0 LSB Full Scale Error Tempco 30 ppm C VDD Power Supply Rejection Ratio 52 dB Output Capacitance 2 pF Dynamic Performance Output Settling Time to 1 2 LSB IDA0H L 0x3FF to 0x000 5 µs Startup Time 5 µs Gain Variation 1 mA Full Scale Output Current 0 5 mA Full Scale Output Current 1 1 Power Consumption Power Supply Current VDD supplied to IDAC 2 mA Full Scale Output Current 1 mA Full...

Page 61: ... Definition 7 1 The maximum load seen by the VREF pin must be less than 200 µA to GND When using the internal voltage reference bypass capacitors of 0 1 µF and 4 7 µF are recommended from the VREF pin to GND If the internal refer ence is not used the REFBE bit should be cleared to 0 Electrical specifications for the internal voltage reference are given in Table 7 1 Important Note about the VREF Pi...

Page 62: ...perature Sensor Enable Bit 0 Internal Temperature Sensor off 1 Internal Temperature Sensor on Bit1 BIASE Internal Analog Bias Generator Enable Bit 0 Internal Bias Generator off 1 Internal Bias Generator on Bit0 REFBE Internal Reference Buffer Enable Bit 0 Internal Reference Buffer disabled 1 Internal Reference Buffer enabled Internal voltage reference driven on the VREF pin R R R R R W R W R W R W...

Page 63: ...fficient 15 ppm C Load Regulation Load 0 to 200 µA to AGND 0 5 ppm µA VREF Turn on Time 1 4 7 µF tantalum 0 1 µF ceramic bypass 2 ms VREF Turn on Time 2 0 1 µF ceramic bypass 20 µs VREF Turn on Time 3 no bypass cap 10 µs Power Supply Rejection 140 ppm V External Reference REFBE 0 Input Voltage Range 0 VDD V Input Current Sample Rate 200 ksps VREF 3 0 V 12 µA Power Specifications ADC Bias Generator...

Page 64: ...C8051F330 1 2 3 4 5 64 Rev 1 7 ...

Page 65: ... Comparator0 Reset on page 100 The Comparator0 inputs are selected in the CPT0MX register SFR Definition 8 2 The CMX0P1 CMX 0P0 bits select the Comparator0 positive input the CMX0N1 CMX0N0 bits select the Comparator0 nega tive input Important Note About Comparator Inputs The Port pins selected as comparator inputs should be configured as analog inputs in their associated Port configuration registe...

Page 66: ...arator Hysteresis Plot The Comparator hysteresis is software programmable via its Comparator Control register CPT0CN The user can program both the amount of hysteresis voltage referred to the input voltage and the positive and negative going symmetry of this hysteresis around the threshold voltage The Comparator hysteresis is programmed using Bits3 0 in the Comparator Control Register CPT0CN shown...

Page 67: ...Power Up Time is specified in Table 8 1 on page 70 SFR Definition 8 1 CPT0CN Comparator0 Control Bit7 CP0EN Comparator0 Enable Bit 0 Comparator0 Disabled 1 Comparator0 Enabled Bit6 CP0OUT Comparator0 Output State Flag 0 Voltage on CP0 CP0 1 Voltage on CP0 CP0 Bit5 CP0RIF Comparator0 Rising Edge Flag Must be cleared by software 0 No Comparator0 Rising Edge has occurred since this flag was last clea...

Page 68: ... as the Comparator0 positive input R W R W R W R W R W R W R W R W Reset Value CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 CMX0P0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x9F CMX0N3 CMX0N2 CMX0N1 CMX0N0 Negative Input 0 0 0 0 P0 1 0 0 0 1 P0 3 0 0 1 0 P0 5 0 0 1 1 P0 7 0 1 0 0 P1 1 0 1 0 1 P1 3 0 1 1 0 P1 5 0 1 1 1 P1 7 1 x x x None CMX0P3 CMX0P2 CMX0P1 CMX0P0 Positive In...

Page 69: ...tor0 Falling Edge Interrupt Enable 0 Comparator0 Falling edge interrupt disabled 1 Comparator0 Falling edge interrupt enabled Bits3 2 UNUSED Read 00b Write don t care Bits1 0 CP0MD1 CP0MD0 Comparator0 Mode Select These bits select the response time for Comparator0 R R R W R W R R R W R W Reset Value CP0RIE CP0FIE CP0MD1 CP0MD0 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x9D Mode ...

Page 70: ... mV V Positive Hysteresis 1 CP0HYP1 0 00 0 1 mV Positive Hysteresis 2 CP0HYP1 0 01 2 5 10 mV Positive Hysteresis 3 CP0HYP1 0 10 7 10 20 mV Positive Hysteresis 4 CP0HYP1 0 11 15 20 30 mV Negative Hysteresis 1 CP0HYN1 0 00 0 1 mV Negative Hysteresis 2 CP0HYN1 0 01 2 5 10 mV Negative Hysteresis 3 CP0HYN1 0 10 7 10 20 mV Negative Hysteresis 4 CP0HYN1 0 11 15 20 30 mV Inverting or Non Inverting Input V...

Page 71: ... 9 1 for a block diagram The CIP 51 includes the following features Performance The CIP 51 employs a pipelined architecture that greatly increases its instruction throughput over the stan dard 8051 architecture In a standard 8051 all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute and usually have a maximum system clock of 12 MHz By contrast the CIP 51 core execute...

Page 72: ...and debugging Third party macro assemblers and C compil ers are also available 9 1 Instruction Set The instruction set of the CIP 51 System Controller is fully compatible with the standard MCS 51 instruc tion set Standard 8051 development tools can be used to develop software for the CIP 51 All CIP 51 instructions are the binary and functional equivalent of their MCS 51 counterparts including opco...

Page 73: ...m A with borrow 2 2 INC A Increment A 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 2 INC Ri Increment indirect RAM 1 2 DEC A Decrement A 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 2 DEC Ri Decrement indirect RAM 1 2 INC DPTR Increment Data Pointer 1 1 MUL AB Multiply A and B 1 4 DIV AB Divide A by B 1 8 DA A Decimal adjust A 1 1 Logical Operations ...

Page 74: ...yte 2 2 MOV direct data Move immediate to direct byte 3 3 MOV Ri A Move A to indirect RAM 1 2 MOV Ri direct Move direct byte to indirect RAM 2 2 MOV Ri data Move immediate to indirect RAM 2 2 MOV DPTR data16 Load DPTR with 16 bit constant 3 3 MOVC A A DPTR Move code byte relative DPTR to A 1 3 MOVC A A PC Move code byte relative PC to A 1 3 MOVX A Ri Move external data 8 bit address to A 1 3 MOVX ...

Page 75: ...addr16 Long subroutine call 3 4 RET Return from subroutine 1 5 RETI Return from interrupt 1 5 AJMP addr11 Absolute jump 2 3 LJMP addr16 Long jump 3 4 SJMP rel Short jump relative address 2 3 JMP A DPTR Jump indirect relative to DPTR 1 3 JZ rel Jump if A equals zero 2 2 3 JNZ rel Jump if A does not equal zero 2 2 3 CJNE A direct rel Compare direct byte to A and jump if not equal 3 3 4 CJNE A data r...

Page 76: ...igned two s complement offset relative to the first byte of the following instruction Used by SJMP and all conditional jumps direct 8 bit internal data location s address This could be a direct access Data RAM location 0x00 0x7F or an SFR 0x80 0xFF data 8 bit constant data16 16 bit constant bit Direct accessed bit in Data RAM or SFR addr11 11 bit destination address used by ACALL and AJMP The dest...

Page 77: ...ides a mechanism for the CIP 51 to update program code and use the program memory space for non volatile data storage Refer to Section 11 Flash Memory on page 103 for further details C8051F330 1 PROGRAM DATA MEMORY FLASH Direct and Indirect Addressing 0x00 0x7F Upper 128 RAM Indirect Addressing Only 0x80 0xFF Special Function Register s Direct Addressing Only DATA MEMORY RAM General Purpose Regist...

Page 78: ...d RS1 PSW 4 select the active register bank see description of the PSW in SFR Definition 9 4 This allows fast context switching when entering subroutines and interrupt service routines Indirect addressing modes use registers R0 and R1 as index registers 9 2 4 Bit Addressable Locations In addition to direct access to data memory organized as bytes the sixteen data memory locations at 0x20 through 0...

Page 79: ...e All other SFRs are byte addressable only Unoccupied addresses in the SFR space are reserved for future use Accessing these areas will have an indeterminate effect and should be avoided Refer to the corresponding pages of the data sheet as indicated in Table 9 3 for a detailed description of each register Table 9 2 Special Function Register SFR Memory Map F8 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 V...

Page 80: ...F0 B Register 85 CKCON 0x8E Clock Control 183 CLKSEL 0xA9 Clock Select 121 CPT0CN 0x9B Comparator0 Control 67 CPT0MD 0x9D Comparator0 Mode Selection 69 CPT0MX 0x9F Comparator0 MUX Selection 68 DPH 0x83 Data Pointer High 83 DPL 0x82 Data Pointer Low 83 EIE1 0xE6 Extended Interrupt Enable 1 91 EIP1 0xF6 Extended Interrupt Priority 1 92 EMI0CN 0xAA External Memory Interface Control 111 FLKEY 0xB7 Fla...

Page 81: ...ure 0 Low 208 PCA0CPL1 0xE9 PCA Capture 1 Low 208 PCA0CPL2 0xEB PCA Capture 2 Low 208 PCA0CPM0 0xDA PCA Module 0 Mode Register 207 PCA0CPM1 0xDB PCA Module 1 Mode Register 207 PCA0CPM2 0xDC PCA Module 2 Mode Register 207 PCA0H 0xFA PCA Counter High 208 PCA0L 0xF9 PCA Counter Low 208 PCA0MD 0xD9 PCA Mode 206 PCON 0x87 Power Control 95 PSCTL 0x8F Program Store R W Control 108 PSW 0xD0 Program Status...

Page 82: ...2H 0xCD Timer Counter 2 High 188 TMR2L 0xCC Timer Counter 2 Low 188 TMR2RLH 0xCB Timer Counter 2 Reload High 188 TMR2RLL 0xCA Timer Counter 2 Reload Low 188 TMR3CN 0x91 Timer Counter 3Control 191 TMR3H 0x95 Timer Counter 3 High 192 TMR3L 0x94 Timer Counter 3Low 192 TMR3RLH 0x93 Timer Counter 3 Reload High 192 TMR3RLL 0x92 Timer Counter 3 Reload Low 192 VDM0CN 0xFF VDD Monitor Control 99 XBR0 0xE1 ...

Page 83: ...ointer Bits7 0 DPL Data Pointer Low The DPL register is the low byte of the 16 bit DPTR DPTR is used to access indirectly addressed Flash memory or XRAM R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x82 Bits7 0 DPH Data Pointer High The DPH register is the high byte of the 16 bit DPTR DPTR is used to access indirectly addressed Flash memo...

Page 84: ...sed during register accesses Bit2 OV Overflow Flag This bit is set to 1 under the following circumstances An ADD ADDC or SUBB instruction causes a sign change overflow A MUL instruction results in an overflow result is greater than 255 A DIV instruction causes a divide by zero condition The OV bit is cleared to 0 by the ADD ADDC SUBB MUL and DIV instructions in all other cases Bit1 F1 User Flag 1 ...

Page 85: ... not enabled the interrupt pending flag is ignored by the hardware and program execution continues as normal The interrupt pending flag is set to logic 1 regard less of the interrupt s enable disable state Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR IE EIE1 However interrupts must first be globally enabled by setting...

Page 86: ...software before returning from the ISR If an interrupt pending flag remains set after the CPU completes the return from interrupt RETI instruction a new interrupt request will be generated immediately and the CPU will re enter the ISR after the completion of the next instruction 9 3 1 MCU Interrupt Sources and Vectors The MCUs support 13 interrupt sources Software can simulate an interrupt by sett...

Page 87: ...rce can be individually programmed to one of two priority levels low or high A low prior ity interrupt service routine can be preempted by a high priority interrupt A high priority interrupt cannot be preempted Each interrupt has an associated interrupt priority bit in an SFR IP or EIP1 used to configure its priority level Low priority is the default If two interrupts are recognized simultaneously...

Page 88: ...ES0 IE 4 PS0 IP 4 Timer 2 Overflow 0x002B 5 TF2H TMR2CN 7 TF2L TMR2CN 6 Y N ET2 IE 5 PT2 IP 5 SPI0 0x0033 6 SPIF SPI0CN 7 WCOL SPI0CN 6 MODF SPI0CN 5 RXOVRN SPI0CN 4 Y N ESPI0 IE 6 PSPI0 IP 6 SMB0 0x003B 7 SI SMB0CN 0 Y N ESMB0 EIE1 0 PSMB0 EIP1 0 RESERVED 0x0043 8 N A N A N A N A N A ADC0 Window Compare 0x004B 9 AD0WINT ADC0CN 3 Y N EWADC0 EIE1 2 PWADC0 EIP1 2 ADC0 Conversion Complete 0x0053 10 A...

Page 89: ...imer 2 interrupt 0 Disable Timer 2 interrupt 1 Enable interrupt requests generated by the TF2L or TF2H flags Bit4 ES0 Enable UART0 Interrupt This bit sets the masking of the UART0 interrupt 0 Disable UART0 interrupt 1 Enable UART0 interrupt Bit3 ET1 Enable Timer 1 Interrupt This bit sets the masking of the Timer 1 interrupt 0 Disable all Timer 1 interrupt 1 Enable interrupt requests generated by t...

Page 90: ...ty Control This bit sets the priority of the Timer 1 interrupt 0 Timer 1 interrupt set to low priority level 1 Timer 1 interrupt set to high priority level Bit2 PX1 External Interrupt 1 Priority Control This bit sets the priority of the External Interrupt 1 interrupt 0 External Interrupt 1 set to low priority level 1 External Interrupt 1 set to high priority level Bit1 PT0 Timer 0 Interrupt Priori...

Page 91: ...equests generated by PCA0 Bit3 EADC0 Enable ADC0 Conversion Complete Interrupt This bit sets the masking of the ADC0 Conversion Complete interrupt 0 Disable ADC0 Conversion Complete interrupt 1 Enable interrupt requests generated by the AD0INT flag Bit2 EWADC0 Enable Window Comparison ADC0 Interrupt This bit sets the masking of ADC0 Window Comparison interrupt 0 Disable ADC0 Window Comparison inte...

Page 92: ...to high priority level Bit3 PADC0 ADC0 Conversion Complete Interrupt Priority Control This bit sets the priority of the ADC0 Conversion Complete interrupt 0 ADC0 Conversion Complete interrupt set to low priority level 1 ADC0 Conversion Complete interrupt set to high priority level Bit2 PWADC0 ADC0 Window Comparator Interrupt Priority Control This bit sets the priority of the ADC0 Window interrupt ...

Page 93: ...igh Bits2 0 INT0SL2 0 INT0 Port Pin Selection Bits These bits select which Port pin is assigned to INT0 Note that this pin assignment is inde pendent of the Crossbar INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin acco...

Page 94: ...ted when an enabled interrupt is asserted or a reset occurs The assertion of an enabled interrupt will cause the Idle Mode Selection bit PCON 0 to be cleared and the CPU to resume operation The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt RETI will be the instruction immediately following the one that set the Idle Mode Select bit If Idl...

Page 95: ...nternal reset and thereby terminate the Stop mode The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the MCD timeout of 100 µs SFR Definition 9 12 PCON Power Control Bits7 2 GF5 GF0 General Purpose Flags 5 0 These are general purpose flags for use under software control Bit1 STOP Stop Mode Select Setting this bit will place the CIP 51 in Stop mode...

Page 96: ...C8051F330 1 2 3 4 5 96 Rev 1 7 ...

Page 97: ... 0xFF all logic ones in open drain mode Weak pullups are enabled during and after the reset For VDD Monitor and power on resets the RST pin is driven low until the device exits the reset state On exit from the reset state the program counter PC is reset and the system clock defaults to the inter nal oscillator Refer to Section 13 Oscillators on page 113 for information on selecting and configuring...

Page 98: ...if a power up was the cause of reset The content of internal data mem ory should be assumed to be undefined after a power on reset The VDD monitor is disabled following a power on reset Figure 10 2 Power On and VDD Monitor Reset Timing 10 2 Power Fail Reset VDD Monitor When a power down transition or power irregularity causes VDD to drop below VRST the power supply monitor will drive the RST pin l...

Page 99: ...g Clock Detector Reset The Missing Clock Detector MCD is a one shot circuit that is triggered by the system clock If the system clock remains high or low for more than 100 µs the one shot will time out and generate a reset After a MCD reset the MCDRSF flag RSTSRC 2 will read 1 signifying the MCD as the reset source otherwise this bit reads 0 Writing a 1 to the MCDRSF bit enables the Missing Clock ...

Page 100: ... 12 following any reset If a system malfunction prevents user software from updating the WDT a reset is generated and the WDTRSF bit RSTSRC 3 is set to 1 The state of the RST pin is unaffected by this reset 10 7 Flash Error Reset If a Flash read write erase or program read targets an illegal address a system reset is generated This may occur due to any of the following A Flash write or erase is at...

Page 101: ...t Bit2 MCDRSF Missing Clock Detector Flag 0 Read Source of last reset was not a Missing Clock Detector timeout Write Missing Clock Detector disabled 1 Read Source of last reset was a Missing Clock Detector timeout Write Missing Clock Detector enabled triggers a reset if a missing clock condition is detected Bit1 PORSF Power On Reset Force and Flag This bit is set anytime a power on reset occurs Wr...

Page 102: ... RST Input Low Voltage 0 3 x VDD RST Input Pullup Current RST 0 0 V 25 40 µA VDD POR Threshold VRST 2 40 2 55 2 70 V Missing Clock Detector Time out Time from last system clock rising edge to reset initiation 100 220 600 µs Reset Time Delay Delay between release of any reset source and code execution at location 0x0000 32 µs Minimum RST Low Time to Generate a System Reset 15 µs VDD Monitor Turn on...

Page 103: ...e timing does not matter but the codes must be written in order If the key codes are written out of order or the wrong codes are written Flash writes and erases will be disabled until the next system reset Flash writes and erases will also be disabled if a Flash write or erase is attempted before the key codes have been written properly The Flash lock resets after each write or erase the key codes...

Page 104: ... Flash writes are complete PSWE should be cleared so that MOVX instructions do not target program memory 11 2 Non volatile Data Storage The Flash memory can be used for non volatile data storage as well as program code This allows data such as calibration coefficients to be calculated and stored at run time Data is written using the MOVX write instruction and read using the MOVC instruction Note M...

Page 105: ...he user to lock n 512 byte Flash pages starting at page 0 addresses 0x0000 to 0x01FF where n is the 1 s complement number represented by the Security Lock Byte Note that the page containing the Flash Security Lock Byte is unlocked when no other Flash pages are locked all bits of the Lock Byte are 1 and locked when any other Flash pages are locked any bit of the Lock Byte is 0 See example below Fig...

Page 106: ...d Read contents of Lock Byte if any page is locked Not Permitted Flash Error Reset Permitted Erase page containing Lock Byte if no pages are locked Permitted Flash Error Reset Flash Error Reset Erase page containing Lock Byte Unlock all pages if any page is locked C2 Device Erase Only Flash Error Reset Flash Error Reset Lock additional pages change 1 s to 0 s in the Lock Byte Not Permitted Flash E...

Page 107: ...g the VDD monitor and enabling the VDD monitor as a reset source Code examples showing this can be found in AN201 Writing to Flash from Firmware avail able from the Silicon Laboratories web site 4 As an added precaution explicitly enable the VDD monitor and enable the VDD monitor as a reset source inside the functions that write and erase Flash memory The VDD monitor enable instructions should be ...

Page 108: ...tch back to the external oscillator after the Flash operation has completed Additional Flash recommendations and example code can be found in AN201 Writing to Flash from Firm ware available from the Silicon Laboratories web site SFR Definition 11 1 PSCTL Program Store R W Control Bits7 2 UNUSED Read 000000b Write don t care Bit1 PSEE Program Store Erase Enable Setting this bit in combination with ...

Page 109: ...a non 0xA5 value to FLKEY from software Read When read bits 1 0 indicate the current Flash lock state 00 Flash is write erase locked 01 The first key code has been written 0xA5 10 Flash is unlocked writes erases allowed 11 Flash writes erases disabled until the next reset R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xB7 Bit7 FOSE Flash O...

Page 110: ...C8051F330 1 2 3 4 5 110 Rev 1 7 ...

Page 111: ...ord are don t cares As a result the 512 byte RAM is mapped modulo style over the entire 64 k external data memory address range For example the XRAM byte at address 0x0000 is shadowed at addresses 0x0200 0x0400 0x0600 0x0800 etc This is a useful feature when performing a linear memory fill as the address pointer doesn t have to be reset when reaching the RAM block boundary SFR Definition 12 1 EMI0...

Page 112: ...C8051F330 1 2 3 4 5 112 Rev 1 7 ...

Page 113: ...scillator All C8051F330 1 2 3 4 5 devices include a programmable internal high frequency oscillator that defaults as the system clock after a system reset The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 13 1 On C8051F330 1 2 3 4 5 devices OSCICL is factory calibrated to obtain a 24 5 MHz base frequency Electrical specifications for the precision ...

Page 114: ... Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xB3 Bit7 IOSCEN Internal H F Oscillator Enable Bit 0 Internal H F Oscillator Disabled 1 Internal H F Oscillator Enabled Bit6 IFRDY Internal H F Oscillator Frequency Ready Flag 0 Internal H F Oscillator is not running at programmed frequency 1 Internal H F Oscillator is running at programmed frequency Bits5 2 UNUSED Read 0000b Write don t care B...

Page 115: ...is copied into the timer reload registers TMRnRLH TMRnRLL By recording the differ ence between two successive timer capture values the low frequency oscillator s period can be calcu lated The OSCLF bits can then be adjusted to produce the desired oscillator frequency SFR Definition 13 3 OSCLCN Internal L F Oscillator Control Bit7 OSCLEN Internal L F Oscillator Enable 0 Internal L F Oscillator Disa...

Page 116: ...lected appropriately see SFR Definition 13 4 Important Note on External Oscillator Usage Port pins must be configured when using the external oscillator circuit When the external oscillator drive circuit is enabled in crystal resonator mode Port pins P0 2 and P0 3 are used as XTAL1 and XTAL2 respectively When the external oscillator drive circuit is enabled in capacitor RC or CMOS clock mode Port ...

Page 117: ...e 13 1 Option 2 XOSCMD 10x Choose XFCN value to match frequency range f 1 23 103 R C where f frequency of clock in MHz C capacitor value in pF R Pullup resistor value in kΩ C MODE Circuit from Figure 13 1 Option 3 XOSCMD 10x Choose K Factor KF for the oscillation frequency desired f KF C VDD where f frequency of clock in MHz C capacitor value the XTAL2 pin in pF VDD Power Supply on MCU in volts R ...

Page 118: ...to achieve proper bias Introducing a delay of 1 ms between enabling the oscillator and checking the XTLVLD bit will prevent a premature switch to the external oscillator as the system clock Switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior The rec ommended procedure is Step 1 Force XTAL1 and XTAL2 to a low state This involves ena...

Page 119: ...a sheet when completing these calculations For example a tuning fork crystal of 32 768 kHz with a recommended load capacitance of 12 5 pF should use the configuration shown in Figure 13 1 Option 1 The total value of the capacitors and the stray capac itance of the XTAL pins should equal 25 pF With a stray capacitance of 3 pF per pin the 22 pF capacitors yield an equivalent capacitance of 12 5 pF a...

Page 120: ...ition 13 4 the required XFCN setting is 010b 13 3 3 External Capacitor Example If a capacitor is used as an external oscillator for the MCU the circuit should be configured as shown in Figure 13 1 Option 3 The capacitor should be no greater than 100 pF however for very small capacitors the total capacitance may be dominated by parasitic capacitance in the PCB layout To determine the required Exter...

Page 121: ...clock CLKSL 1 0 must be set to 01b for the system clock to run from the external oscillator however the exter nal oscillator may still clock certain peripherals timers PCA when the internal oscillator is selected as the system clock The system clock may be switched on the fly between the internal oscillator external oscilla tor and Clock Multiplier so long as the selected clock source is enabled a...

Page 122: ...Oscillator Supply Current from VDD 25 C VDD 3 0 V OSCICN 7 1 450 µA Power Supply Sensitivity Constant Temperature 0 3 0 1 V Temperature Sensitivity Constant Supply 50 10 ppm C Internal Low Frequency Oscillator Using Factory Calibrated Settings Oscillator Frequency OSCLD 11b 72 80 88 kHz Oscillator Supply Current from VDD 25 C VDD 3 0 V OSCLCN 7 1 5 5 µA Power Supply Sensitivity Constant Temperatur...

Page 123: ...ettings The Crossbar assigns the selected internal digital resources to the I O pins based on the Priority Decoder Figure 14 3 and Figure 14 4 The registers XBR0 and XBR1 defined in SFR Definition 14 1 and SFR Definition 14 2 are used to select internal digital functions All Port I Os are 5 V tolerant refer to Figure 14 2 for the Port cell circuit The Port I O cells are configured as either push p...

Page 124: ...C8051F330 1 2 3 4 5 124 Rev 1 7 Figure 14 2 Port I O Cell Block Diagram GND PORT OUTENABLE PORT OUTPUT PUSH PULL VDD VDD WEAK PULLUP WEAK PORT PAD ANALOG INPUT Analog Select PORT INPUT ...

Page 125: ... P0 3 and or P0 2 if the external oscillator circuit is enabled P0 6 if the ADC or IDAC is configured to use the external conversion start signal CNVSTR and any selected ADC or Comparator inputs The Crossbar skips selected pins as if they were already assigned and moves to the next unassigned pin Figure 14 3 shows the Crossbar Decoder priority with no Port pins skipped P0SKIP P1SKIP 0x00 Figure 14...

Page 126: ...iguously after the prioritized functions have been assigned Important Note The SPI can be operated in either 3 wire or 4 wire modes pending the state of the NSS MD1 NSSMD0 bits in register SPI0CN According to the SPI mode the NSS signal may or may not be routed to a Port pin P2 VREF IDA x1 x2 CNVSTR 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 NSS is only pinned out in 4 wire SPI Mode SYSCLK CEX0 CEX1 CEX2 E...

Page 127: ...t See SFR Defini tion 14 4 for the PnMDIN register details The output driver characteristics of the I O pins are defined using the Port Output Mode registers PnMD OUT Each Port Output driver can be configured as either open drain or push pull This selection is required even for the digital resources selected in the XBRn registers and is not automatic The only exception to this is the SMBus SDA SCL...

Page 128: ...able 0 SYSCLK unavailable at Port pin 1 SYSCLK output routed to Port pin Bit2 SMB0E SMBus I O Enable 0 SMBus I O unavailable at Port pins 1 SMBus I O routed to Port pins Bit1 SPI0E SPI I O Enable 0 SPI I O unavailable at Port pins 1 SPI I O routed to Port pins Note that the SPI can be assigned either 3 or 4 GPIO pins Bit0 URT0E UART I O Output Enable 0 UART I O unavailable at Port pin 1 UART TX0 R...

Page 129: ...hen operating on a Port SFR are the following ANL ORL XRL JBC CPL INC DEC DJNZ and MOV CLR or SETB when the destination is an individual bit in a Port SFR For these instructions the value of the register not the pin is read modified and written back to the SFR Bit7 WEAKPUD Port I O Weak Pullup Disable 0 Weak Pullups enabled except for Ports whose I O are configured as analog input 1 Weak Pullups d...

Page 130: ...logic low 1 P0 n pin is logic high R W R W R W R W R W R W R W R W Reset Value P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address bit addressable 0x80 Bits7 0 Analog Input Configuration Bits for P0 7 P0 0 respectively Port pins configured as analog inputs have their weak pullup digital driver and digital receiver disabled 0 Corresponding P0 n pin i...

Page 131: ...Port pins used as ana log inputs for ADC or Comparator or used as special functions VREF input external oscil lator circuit CNVSTR input should be skipped by the Crossbar 0 Corresponding P0 n pin is not skipped by the Crossbar 1 Corresponding P0 n pin is skipped by the Crossbar R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xD4 Bits7 0 P1 ...

Page 132: ... 0 respectively ignored if corresponding bit in regis ter P1MDIN is logic 0 0 Corresponding P1 n Output is open drain 1 Corresponding P1 n Output is push pull R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xA5 Bit7 UNUSED Read 0b Write don t care Bits6 0 P1SKIP 6 0 Port1 Crossbar Skip Enable Bits These bits select Port pins to be skipped b...

Page 133: ...edance if corresponding P2MDOUT n bit 0 Read Directly reads Port pin 0 P2 n pin is logic low 1 P2 n pin is logic high R R R R R R R R W Reset Value P2 0 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address bit addressable 0xA0 Bits7 1 Unused Read 0000000b Write don t care Bit0 Output Configuration Bit for P2 0 0 P2 0 Output is open drain 1 P2 0 Output is push pull R R R R R R R R W Reset V...

Page 134: ...s Conditions Min Typ Max Units Output High Voltage IOH 3 mA Port I O push pull IOH 10 µA Port I O push pull IOH 10 mA Port I O push pull VDD 0 7 VDD 0 1 VDD 0 8 V Output Low Voltage IOL 8 5 mA IOL 10 µA IOL 25 mA 1 0 0 6 0 1 V Input High Voltage 2 0 V Input Low Voltage 0 8 V Input Leakage Current Weak Pullup Off Weak Pullup On VIN 0 V 25 1 50 µA ...

Page 135: ...and or slave and may function on a bus with multiple mas ters The SMBus provides control of SDA serial data SCL serial clock generation and synchronization arbitration logic and START STOP control and generation Three SFRs are associated with the SMBus SMB0CF configures the SMBus SMB0CN controls the status of the SMBus and SMB0DAT is the data register used for both transmitting and receiving SMBus...

Page 136: ... Configuration 15 3 SMBus Operation Two types of data transfers are possible data transfers from a master transmitter to an addressed slave receiver WRITE and data transfers from an addressed slave transmitter to a master receiver READ The master device initiates both types of data transfers and provides the serial clock pulses on SCL The SMBus interface may operate as a master or a slave and mult...

Page 137: ...us Figure 15 3 illustrates a typical SMBus transaction Figure 15 3 SMBus Transaction 15 3 1 Arbitration A master may start a transfer only if the bus is free The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time see Section 15 3 4 SCL High SMBus Free Timeout on page 138 In the event that two or more devices attempt to begin a transfer at the same ti...

Page 138: ...BFTE bit in SMB0CF is set the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods If the SMBus is waiting to generate a Master START the START will be generated following this timeout Note that a clock source is required for free timeout detection even in a slave only implementation 15 4 Using the SMBus The SMBus can operate in both Master and Slave m...

Page 139: ...e Timeout detection SCL Low Timeout and or Bus Free Timeout SDA setup and hold time extensions Slave event enable disable Clock source selection These options are selected in the SMB0CF register as described in Section 15 4 1 SMBus Configura tion Register on page 140 ...

Page 140: ... enabled When operating as a master overflows from the selected source determine the absolute minimum SCL low and high times as defined in Equation 15 1 Note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times For example Timer 1 overflows may generate the SMBus and UART baud rates simultaneously Timer configuration is covered in Sect...

Page 141: ... SYSCLK is above 10 MHz With the SMBTOE bit set Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts see Section 15 3 3 SCL Low Timeout on page 138 The SMBus interface will force Timer 3 to reload while SCL is high and allow Timer 3 to count when SCL is low The Timer 3 interrupt service rou tine should be used to reset SMBus communication by disabling and re ena...

Page 142: ...BTOE SMBus SCL Timeout Detection Enable This bit enables SCL low timeout detection If set to logic 1 the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low If Timer 3 is con figured to Split Mode only the High Byte of the timer is held in reload while SCL is high Timer 3 should be programmed to generate interrupts at 25 ms and the Timer 3 interrupt servi...

Page 143: ...es the value received on the last ACK cycle ACKRQ is set each time a byte is received indicating that an outgoing ACK value is needed When ACKRQ is set software should write the desired outgoing value to the ACK bit before clearing SI A NACK will be generated if software does not write the ACK bit before clearing SI SDA will reflect the defined ACK value immediately following a write to the ACK bi...

Page 144: ...is transmitted followed by a START condition Read 0 No Stop condition detected 1 Stop condition detected if in Slave Mode or pending if in Master Mode Bit3 ACKRQ SMBus Acknowledge Request This read only bit is set to logic 1 when the SMBus has received a byte and needs the ACK bit to be written with the correct ACK response value Bit2 ARBLOST SMBus Arbitration Lost Indicator This read only bit is ...

Page 145: ... a detected STOP A pending STOP is generated ACKRQ A byte has been received and an ACK response value is needed After each ACK cycle ARBLOST A repeated START is detected as a MASTER when STA is low unwanted repeated START SCL is sensed low while attempting to gener ate a STOP or repeated START condition SDA is sensed low while transmitting a 1 excluding ACK bits Each time SI is cleared ACK The inc...

Page 146: ...upt is generated before the ACK cycle when operat ing as a receiver and after the ACK cycle when operating as a transmitter 15 5 1 Master Transmitter Mode Serial data is transmitted on SDA while the serial clock is output on SCL The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit In this case the data ...

Page 147: ...7 Figure 15 5 Typical Master Transmitter Sequence A A A S W P Data Byte Data Byte SLA S START P STOP A ACK W WRITE SLA Slave Address Received by SMBus Interface Transmitted by SMBus Interface Interrupt Interrupt Interrupt Interrupt ...

Page 148: ...owledge value Note writing a 1 to the ACK bit gen erates an ACK writing a 0 generates a NACK Software should write a 0 to the ACK bit after the last byte is received to transmit a NACK The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated The interface will switch to Master Transmitter Mode if SMB0DAT is written while an active Master Receiver Figure 15 6 shows ...

Page 149: ... If the received slave address is acknowledged zero or more data bytes are received Software must write the ACK bit after each received byte to ACK or NACK the received byte The interface exits Slave Receiver Mode after receiving a STOP Note that the interface will switch to Slave Transmitter Mode if SMB0DAT is written while an active Slave Receiver Figure 15 7 shows a typical Slave Receiver seque...

Page 150: ...o before SI is cleared Note an error condition may be gener ated if SMB0DAT is written following a received NACK while in Slave Transmitter Mode The interface exits Slave Transmitter Mode after receiving a STOP Note that the interface will switch to Slave Receiver Mode if SMB0DAT is not written following a Slave Transmitter interrupt Figure 15 8 shows a typical Slave Transmitter sequence Two trans...

Page 151: ... End transfer with STOP 0 1 X End transfer with STOP and start another transfer 1 1 X Send repeated START 1 0 X Switch to Master Receiver Mode clear SI without writ ing new data to SMB0DAT 0 0 X Master Receiver 1000 1 0 X A master data byte was received ACK requested Acknowledge received byte Read SMB0DAT 0 0 1 Send NACK to indicate last byte and send STOP 0 1 0 Send NACK to indicate last byte and...

Page 152: ...nowledge received address 0 0 0 Reschedule failed transfer do not acknowledge received address 1 0 0 0010 0 1 X Lost arbitration while attempting a repeated START Abort failed transfer 0 0 X Reschedule failed transfer 1 0 X 0001 1 1 X Lost arbitration while attempting a STOP No action required transfer complete aborted 0 0 0 0 0 X A STOP was detected while addressed as a Slave Transmitter or Slave...

Page 153: ...he buffered Receive register it is not possible to read data from the Transmit register With UART0 interrupts enabled an interrupt is generated each time a transmit is completed TI0 is set in SCON0 or a data byte has been received RI0 is set in SCON0 The UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by software...

Page 154: ...179 The Timer 1 reload value should be set so that over flows will occur at two times the desired UART baud rate frequency Note that Timer 1 may be clocked by one of six sources SYSCLK SYSCLK 4 SYSCLK 12 SYSCLK 48 the external oscillator clock 8 or an external input T1 For any given Timer 1 clock source the UART0 baud rate is determined by Equation 16 1 A and Equation 16 1 B Equation 16 1 UART0 Ba...

Page 155: ...f the stop bit time Data recep tion can begin any time after the REN0 Receive Enable bit SCON0 4 is set to logic 1 After the stop bit is received the data byte will be loaded into the SBUF0 receive register if the following conditions are met RI0 must be logic 0 and if MCE0 is logic 1 the stop bit must be logic 1 In the event of a receive data over run the first received 8 bits are latched into th...

Page 156: ...Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit When a master processor wants to transmit to one or more slaves it first sends an address byte to select the target s An address byte differs from a data byte in that its ninth bit is logic 1 in a data byte the ninth bit is always set to logic 0 Setti...

Page 157: ...C8051F330 1 2 3 4 5 Rev 1 7 157 Figure 16 6 UART Multi Processor Mode Interconnect Diagram Master Device Slave Device TX RX RX TX Slave Device RX TX Slave Device RX TX V ...

Page 158: ...signed to the ninth transmission bit in 9 bit UART Mode It is not used in 8 bit UART Mode Set or cleared by software as required Bit2 RB80 Ninth Receive Bit RB80 is assigned the value of the STOP bit in Mode 0 it is assigned the value of the 9th data bit in Mode 1 Bit1 TI0 Transmit Interrupt Flag Set by hardware when a byte of data has been transmitted by UART0 after the 8th bit in 8 bit UART Mode...

Page 159: ...transmit shift register and a receive latch register When data is written to SBUF0 it goes to the transmit shift register and is held for serial transmis sion Writing a byte to SBUF0 initiates the transmission A read of SBUF0 returns the con tents of the receive latch R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x99 ...

Page 160: ... found in Section 18 1 2 X Don t care Table 16 2 Timer Settings for Standard Baud Rates Using an External 25 0 MHz Oscillator Frequency 25 0 MHz Target Baud Rate bps Baud Rate Error Oscilla tor Divide Factor Timer Clock Source SCA1 SCA0 pre scale select 1 T1M1 Timer 1 Reload Value hex SYSCLK from External Osc 230400 0 47 108 SYSCLK XX2 1 0xCA 115200 0 45 218 SYSCLK XX 1 0x93 57600 0 01 434 SYSCLK ...

Page 161: ...600 0 00 2304 EXTCLK 8 11 0 0x70 Notes 1 SCA1 SCA0 and T1M bit definitions can be found in Section 18 1 2 X Don t care Table 16 4 Timer Settings for Standard Baud Rates Using an External 18 432 MHz Oscillator Frequency 18 432 MHz Target Baud Rate bps Baud Rate Error Oscilla tor Divide Factor Timer Clock Source SCA1 SCA0 pre scale select 1 T1M1 Timer 1 Reload Value hex SYSCLK from External Osc 2304...

Page 162: ...D0 9600 0 00 1152 EXTCLK 8 11 0 0xB8 Notes 1 SCA1 SCA0 and T1M bit definitions can be found in Section 18 1 2 X Don t care Table 16 6 Timer Settings for Standard Baud Rates Using an External 3 6864 MHz Oscillator Frequency 3 6864 MHz Target Baud Rate bps Baud Rate Error Oscilla tor Divide Factor Timer Clock Source SCA1 SCA0 pre scale select 1 T1M1 Timer 1 Reload Value hex SYSCLK from External Osc ...

Page 163: ...one master attempts simultaneous data transfers NSS can also be configured as a chip select output in master mode or disabled for 3 wire operation Additional gen eral purpose port I O pins can be used to select multiple slave devices in master mode Figure 17 1 SPI Block Diagram SFR Bus Data Path Control SFR Bus Write SPI0DAT Receive Data Buffer SPI0DAT 0 1 2 3 4 5 6 7 Shift Register SPI CONTROL LO...

Page 164: ...CK signal is ignored by a SPI slave when the slave is not selected NSS 1 in 4 wire slave mode 17 1 4 Slave Select NSS The function of the slave select NSS signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the SPI0CN register There are three possible modes that can be selected with these bits 1 NSSMD 1 0 00 3 Wire Master or 3 Wire Slave Mode SPI0 operates in 3 wire mode and NSS is...

Page 165: ...er mode is active when NSS MD1 SPI0CN 3 0 and NSSMD0 SPI0CN 2 1 In this mode NSS is an input to the device and is used to disable the master SPI0 when another master is accessing the bus When NSS is pulled low in this mode MSTEN SPI0CN 6 and SPIEN SPI0CN 0 are set to 0 to disable the SPI master device and a Mode Fault is generated MODF SPI0CN 5 1 Mode Fault will generate an interrupt if enabled SP...

Page 166: ...ave Mode Connection Diagram Figure 17 4 4 Wire Single Master Mode and 4 Wire Slave Mode Connection Diagram Master Device 2 Master Device 1 MOSI MISO SCK MISO MOSI SCK NSS GPIO NSS GPIO Slave Device Master Device MOSI MISO SCK MISO MOSI SCK Slave Device Master Device MOSI MISO SCK MISO MOSI SCK NSS NSS GPIO Slave Device MOSI MISO SCK NSS ...

Page 167: ...ve when NSSMD1 SPI0CN 3 0 and NSSMD0 SPI0CN 2 0 NSS is not used in this mode and is not mapped to an external port pin through the crossbar Since there is no way of uniquely addressing the device in 3 wire slave mode SPI0 must be the only slave device present on the bus It is important to note that in 3 wire slave mode there is no external means of resetting the bit counter that determines when a ...

Page 168: ...register is ignored when operating in slave mode When the SPI is configured as a master the maximum data transfer rate bits sec is one half the system clock frequency or 12 5 MHz whichever is slower When the SPI is configured as a slave the maximum data transfer rate bits sec for full duplex operation is 1 10 the system clock frequency provided that the master issues SCK NSS in 4 wire slave mode a...

Page 169: ...egister SPI0CFG Configuration Register and SPI0CKR Clock Rate Register The four special function registers related to the operation of the SPI0 Bus are described in the following figures MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO NSS 4 Wire Mode MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MOSI SCK CKPOL 0 CKPHA 0 SCK CKPOL 1 CKPHA 0 SCK CKPOL 0 CKPHA 1 SCK CKPOL 1 CKPHA 1 MSB Bit 6 Bit 5...

Page 170: ... on the NSS port pin at the time that the register is read This input is not de glitched Bit 1 SRMT Shift Register Empty Valid in Slave Mode read only This bit will be set to logic 1 when all data has been transferred in out of the shift register and there is no new information available to read from the transmit buffer or write to the receive buffer It returns to logic 0 when a data byte is trans...

Page 171: ...ious transfer and the last bit of the current transfer is shifted into the SPI0 shift register This bit is not automatically cleared by hardware It must be cleared by software Bits 3 2 NSSMD1 NSSMD0 Slave Select Mode Selects between the following NSS operation modes See Section 17 2 SPI0 Master Mode Operation on page 165 and Section 17 3 SPI0 Slave Mode Operation on page 167 00 3 Wire Slave or 3 w...

Page 172: ...egister for 0 SPI0CKR 255 Example If SYSCLK 2 MHz and SPI0CKR 0x04 R W R W R W R W R W R W R W R W Reset Value SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xA2 fSCK 2000000 2 4 1 fSCK 200kHz fSCK SYSCLK 2 SPI0CKR 1 Bits 7 0 SPI0DAT SPI0 Transmit and Receive Data The SPI0DAT register is used to transmit and receive SPI0 data Writing data to S...

Page 173: ...ng CKPHA 0 Figure 17 9 SPI Master Timing CKPHA 1 SCK T MCKH T MCKL MOSI T MIS MISO SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T MIH SCK T MCKH T MCKL MISO T MIH MOSI SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T MIS ...

Page 174: ... Timing CKPHA 1 SCK T SE NSS T CKH T CKL MOSI T SIS T SIH MISO T SD T SOH SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T SEZ T SDZ SCK T SE NSS T CKH T CKL MOSI T SIS T SIH MISO T SD T SOH SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T SLH T SEZ T SDZ ...

Page 175: ...igure 17 11 TSE NSS Falling to First SCK Edge 2 x TSYSCLK ns TSD Last SCK Edge to NSS Rising 2 x TSYSCLK ns TSEZ NSS Falling to MISO Valid 4 x TSYSCLK ns TSDZ NSS Rising to MISO High Z 4 x TSYSCLK ns TCKH SCK High Time 5 x TSYSCLK ns TCKL SCK Low Time 5 x TSYSCLK ns TSIS MOSI Valid to SCK Sample Edge 2 x TSYSCLK ns TSIH SCK Sample Edge to MOSI Change 2 x TSYSCLK ns TSOH SCK Shift Edge to MISO Chan...

Page 176: ...C8051F330 1 2 3 4 5 176 Rev 1 7 ...

Page 177: ...mer 0 and Timer 1 Each timer is implemented as a 16 bit register accessed as two separate bytes a low byte TL0 or TL1 and a high byte TH0 or TH1 The Counter Timer Control register TCON is used to enable Timer 0 and Timer 1 as well as indicate status Timer 0 interrupts can be enabled by setting the ET0 bit in the IE regis ter Section 9 3 5 Interrupt Register Descriptions on page 89 Timer 1 interrup...

Page 178: ...et The timer registers should be loaded with the desired initial value before the timer is enabled TL1 and TH1 form the 13 bit register for Timer 1 in the same manner as described above for TL0 and TH0 Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0 The input signal INT1 is used with Timer 1 the INT1 polarity is defined by bit IN1PL in register IT01C...

Page 179: ...in Mode 2 Timer 1 operates identically to Timer 0 Both counter timers are enabled and configured in Mode 2 in the same manner as Mode 0 Setting the TR0 bit TCON 4 enables the timer when either GATE0 TMOD 3 is logic 0 or when the input signal INT0 is active as defined by bit IN0PL in register IT01CF see Section 9 3 2 External Interrupts on page 87 for details on the external input signals INT0 and ...

Page 180: ...in Mode 3 When Timer 0 is operating in Mode 3 Timer 1 can be operated in Modes 0 1 or 2 but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt However the Timer 1 overflow can be used to generate baud rates for the SMBus and or UART and or initiate ADC conversions While Timer 0 is operating in Mode 3 Timer 1 run control is handled through its mode set tings To run...

Page 181: ...his flag is set to 1 when INT1 is active as defined by bit IN1PL in register IT01CF see SFR Definition 9 11 Bit2 IT1 Interrupt 1 Type Select This bit selects whether the configured INT1 interrupt will be edge or level sensitive INT1 is configured active low or high by the IN1PL bit in the IT01CF register see SFR Definition 9 11 0 INT1 is level triggered 1 INT1 is edge triggered Bit1 IE0 External I...

Page 182: ...er 0 enabled only when TR0 1 AND INT0 is active as defined by bit IN0PL in regis ter IT01CF see SFR Definition 9 11 Bit2 C T0 Counter Timer Select 0 Timer Function Timer 0 incremented by clock defined by T0M bit CKCON 2 1 Counter Function Timer 0 incremented by high to low transitions on external input pin T0 Bits1 0 T0M1 T0M0 Timer 0 Mode Select These bits select the Timer 0 operation mode R W R ...

Page 183: ...bit selects the clock supplied to Timer 2 If Timer 2 is configured in split 8 bit timer mode this bit selects the clock supplied to the lower 8 bit timer 0 Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN 1 Timer 2 low byte uses the system clock Bit3 T1M Timer 1 Clock Select This select the clock source supplied to Timer 1 T1M is ignored when C T1 is set to logic 1 0 Timer 1 use...

Page 184: ...8A Bits 7 0 TL1 Timer 1 Low Byte The TL1 register is the low byte of the 16 bit Timer 1 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x8B Bits 7 0 TH0 Timer 0 High Byte The TH0 register is the high byte of the 16 bit Timer 0 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x8C Bits ...

Page 185: ...16 bit timer with auto reload Timer 2 can be clocked by SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 As the 16 bit timer register increments and overflows from 0xFFFF to 0x0000 the 16 bit value in the Timer 2 reload registers TMR2RLH and TMR2RLL is loaded into the Timer 2 register as shown in Figure 18 4 and the Timer 2 High Byte Overflow Flag TMR2CN 7 is set If...

Page 186: ...he TF2L bit is set when TMR2L overflows from 0xFF to 0x00 When Timer 2 interrupts are enabled IE 5 an interrupt is generated each time TMR2H overflows If Timer 2 interrupts are enabled and TF2LEN TMR2CN 5 is set an interrupt is gener ated each time either TMR2L or TMR2H overflows When TF2LEN is enabled software must check the TF2H and TF2L flags to determine the source of the Timer 2 interrupt The...

Page 187: ... generated on a falling edge of the low frequency oscillator output and the current 16 bit timer value in TMR2H TMR2L will be copied to TMR2RLH TMR2RLL See Section 13 Oscillators on page 113 for more details 0 Timer 2 Low Frequency Oscillator Capture disabled 1 Timer 2 Low Frequency Oscillator Capture enabled Bit3 T2SPLIT Timer 2 Split Mode Enable When this bit is set Timer 2 operates as two 8 bit...

Page 188: ...H holds the high byte of the reload value for Timer 2 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xCB Bits 7 0 TMR2L Timer 2 Low Byte In 16 bit mode the TMR2L register contains the low byte of the 16 bit Timer 2 In 8 bit mode TMR2L contains the 8 bit low byte timer value R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit...

Page 189: ...perates as a 16 bit timer with auto reload Timer 3 can be clocked by SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 As the 16 bit timer register increments and overflows from 0xFFFF to 0x0000 the 16 bit value in the Timer 3 reload registers TMR3RLH and TMR3RLL is loaded into the Timer 3 register as shown in Figure 18 6 and the Timer 3 High Byte Overflow Flag TMR3C...

Page 190: ... to 0x00 the TF3L bit is set when TMR3L overflows from 0xFF to 0x00 When Timer 3 interrupts are enabled an interrupt is generated each time TMR3H over flows If Timer 3 interrupts are enabled and TF3LEN TMR3CN 5 is set an interrupt is generated each time either TMR3L or TMR3H overflows When TF3LEN is enabled software must check the TF3H and TF3L flags to determine the source of the Timer 3 interrup...

Page 191: ...t will be generated on a rising edge of the low frequency oscillator output and the current 16 bit timer value in TMR3H TMR3L will be copied to TMR3RLH TMR3RLL See Section 13 Oscillators on page 113 for more details 0 Timer 3 Low Frequency Oscillator Capture disabled 1 Timer 3 Low Frequency Oscillator Capture enabled Bit3 T3SPLIT Timer 3 Split Mode Enable When this bit is set Timer 3 operates as t...

Page 192: ...LH holds the high byte of the reload value for Timer 3 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x93 Bits 7 0 TMR3L Timer 3 Low Byte In 16 bit mode the TMR3L register contains the low byte of the 16 bit Timer 3 In 8 bit mode TMR3L contains the 8 bit low byte timer value R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bi...

Page 193: ... configured to operate independently in one of six modes Edge Triggered Capture Software Timer High Speed Output Fre quency Output 8 Bit PWM or 16 Bit PWM each mode is described in Section 19 2 Capture Compare Modules on page 195 The external oscillator clock option is ideal for real time clock RTC functionality allowing the PCA to be clocked by a precision external oscillator while the internal o...

Page 194: ...leared by hardware when the CPU vectors to the interrupt service routine and must be cleared by soft ware Note PCA0 interrupts must be globally enabled before CF interrupts are recognized PCA0 inter rupts are globally enabled by setting the EA bit IE 7 and the EPCA0 bit in EIE1 to logic 1 Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in I...

Page 195: ...abled by setting the EA bit and the EPCA0 bit to logic 1 See Figure 19 3 for details on the PCA interrupt configuration Figure 19 3 PCA Interrupt Block Diagram Table 19 2 PCA0CPM Register Settings for PCA Capture Compare Modules PWM16 ECOM CAPP CAPN MAT TOG PWM ECCF Operation Mode X X 1 0 0 0 0 X Capture triggered by positive edge on CEXn X X 0 1 0 0 0 X Capture triggered by negative edge on CEXn ...

Page 196: ... and an interrupt request is generated if CCF interrupts are enabled The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software If both CAPPn and CAPNn bits are set to logic 1 then the state of the Port pin associated with CEXn can be read directly to determine whether a rising edge or falling edge caused the capture ...

Page 197: ...leared by software Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Cap ture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 Figure 19 5 PCA Software Timer Mode Diagram Match 16 bit...

Page 198: ... Compare Registers When writing a 16 bit value to the PCA0 Cap ture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 Figure 19 6 PCA High Speed Output Mode Diagram Match 16 bit Comparator PCA0H PCA0CPHn Enable PCA0L PCA Timebase PCA0CPLn 0 1 0 0 0 x ENB ENB 0 1 Write to PCA0CPLn Write to PCA0CPHn Reset P...

Page 199: ...e of the capture compare module is compared to the PCA counter low byte on a match CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn Frequency Output Mode is enabled by setting the ECOMn TOGn and PWMn bits in the PCA0CPMn reg ister Figure 19 7 PCA Frequency Output Mode FCEXn FPCA 2 PCA0CPHn Note A value of 0x00 in the PCA0CPHn register is equal to 256 f...

Page 200: ...n without software intervention Setting the ECOMn and PWMn bits in the PCA0CPMn register enables 8 Bit Pulse Width Modulator mode The duty cycle for 8 Bit PWM Mode is given by Equation 19 4 Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Cap ture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writin...

Page 201: ... to 1 Equation 19 5 16 Bit PWM Duty Cycle Using Equation 19 5 the largest duty cycle is 100 PCA0CPn 0 and the smallest duty cycle is 0 0015 PCA0CPn 0xFFFF A 0 duty cycle may be generated by clearing the ECOMn bit to 0 Figure 19 9 PCA 16 Bit PWM Mode 19 3 Watchdog Timer Mode A programmable watchdog timer WDT function is available through the PCA Module 2 The WDT is used to generate a reset if the t...

Page 202: ...e WDT is disabled The PCA counter run control CR will read zero if the WDT is enabled but user software has not enabled the PCA counter If a match occurs between PCA0CPH2 and PCA0H while the WDT is enabled a reset will be generated To prevent a WDT reset the WDT may be updated with a write of any value to PCA0CPH2 Upon a PCA0CPH2 write PCA0H plus the offset held in PCA0CPL2 is loaded into PCA0CPH2...

Page 203: ...riting a 0 to the WDTE bit Select the desired PCA clock source with the CPS2 CPS0 bits Load PCA0CPL2 with the desired WDT update offset value Configure the PCA Idle mode set CIDL if the WDT should be suspended while the CPU is in Idle mode Enable the WDT by setting the WDTE bit to 1 Write a value to PCA0CPH2 to reload the WDT The PCA clock source and Idle mode select cannot be changed while the WD...

Page 204: ...nterval ms 24 500 000 255 32 1 24 500 000 128 16 2 24 500 000 32 4 1 18 432 000 255 42 7 18 432 000 128 21 5 18 432 000 32 5 5 11 059 200 255 71 1 11 059 200 128 35 8 11 059 200 32 9 2 3 062 5002 255 257 3 062 5002 128 129 5 3 062 5002 32 33 1 32 000 255 24576 32 000 128 12384 32 000 32 3168 Notes 1 Assumes SYSCLK 12 as the PCA clock source and a PCA0L value of 0x00 at the update time 2 Internal S...

Page 205: ...pt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software Bit1 CCF1 PCA Module 1 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF1 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit...

Page 206: ...er Timer Pulse Select These bits select the timebase source for the PCA counter Bit0 ECF PCA Counter Timer Overflow Interrupt Enable This bit sets the masking of the PCA Counter Timer Overflow CF interrupt 0 Disable the CF interrupt 1 Enable a PCA Counter Timer Overflow interrupt request when CF PCA0CN 7 is set Note When the WDTE bit is set to 1 the PCA0MD register cannot be modified To change the...

Page 207: ...1 Enabled Bit2 TOGn Toggle Function Enable This bit enables disables the toggle function for PCA module n When enabled matches of the PCA counter with a module s capture compare register cause the logic level on the CEXn pin to toggle If the PWMn bit is also set to logic 1 the module operates in Frequency Output Mode 0 Disabled 1 Enabled Bit1 PWMn Pulse Width Modulation Mode Enable This bit enable...

Page 208: ...CA0H register holds the high byte MSB of the 16 bit PCA Counter Timer R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Address 0xFA Bits7 0 PCA0CPLn PCA Capture Module Low Byte The PCA0CPLn register holds the low byte LSB of the 16 bit capture module n R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1...

Page 209: ...rough the C2 interface as described in the C2 Interface Specification C2 Register Definition 20 1 C2ADD C2 Address C2 Register Definition 20 2 DEVICEID C2 Device ID Bits7 0 The C2ADD register is accessed via the C2 interface to select the target Data register for C2 Data Read and Data Write commands Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address Description 0x00 Selects the D...

Page 210: ...Flash programming via the C2 interface To enable C2 Flash programming the following codes must be written in order 0x02 0x01 Note that once C2 Flash programming is enabled a system reset must be issued to resume normal operation Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7 0 FPDAT C2 Flash Programming Data Register This register is used to pass Flash commands addresses and da...

Page 211: ...ce can safely borrow the C2CK RST and C2D P2 0 pins In most applica tions external resistors are required to isolate C2 interface traffic from the user application A typical isola tion configuration is shown in Figure 20 1 Figure 20 1 Typical C2 Pin Sharing The configuration in Figure 20 1 assumes the following 1 The user input b cannot change state while the target device is halted 2 The RST pin ...

Page 212: ... Table 3 1 Added supply current data from characterization Updated Table 5 1 Added MIN MAX numbers for ADC Offset and Full Scale Error Fixed SFR Definition 8 2 Typo in bit descriptions 2 0 changed to 3 0 Fixed SFR Definition 9 4 Text at bottom of figure was cut off Added Section 11 4 Flash Write and Erase Guidelines on page 107 Fixed Section 12 External RAM on page 111 paragraph 2 Typo in descript...

Page 213: ...C8051F330 1 2 3 4 5 Rev 1 7 213 NOTES ...

Page 214: ...or health which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories products are generally not intended for military applications Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including but not limited to nuclear biological or chemical weapons or missiles capable of delivering such weapons...

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