1.2 Alternative Configurations
Positive Voltage Gate Drive Only
The standard configuration for the gate driver to apply positive voltage, VDDB-VMID, to the gate during the high drive portion of the
PWM cycle and negative voltage, VSSB-VMID, during the low drive portion of the PWM cycle. Alternatively, if only positive drive voltage
is desired, remove R13 and install a 0 Ω resistor at R19.
Prototyping Area
If additional components are needed to evaluate the gate drive function for a particular load, there is a prototyping area just below Q2
locations.
1.3 Demonstrating Driver Functionality
Even with no load present, the basic functionality of the Si8284 can be demonstrated.
1. Apply 24 V to VDDP to power both sides of the Si8284. With jumpers installed at JP4–JP8, D5–D8 will illuminate indicating sup-
plies are biased.
2. Leave VPWR unpowered. Install a jumper at JP9. This disables desaturation detection and allows for normal operation of the
Si8284. Since both sides of the Si8284 have been powered on, RDY will output 5 V, which can be observed at J8.
3. Apply 5 V to both J9, IN+ and J10, IN-. VL will turn on and –9 V will be observed across pins 1 and 3 of Q1.
4. Remove 5 V from J10 and allow IN- to be pulled to GNDA. VH will turn on and +15 V will be observed across pins 1 and 3 of Q1.
5. Remove the short between VPWR and VMID at JP9.
6. With no path for DSAT current, the voltage at the DSAT pin rises and the Si8284 will drive the output low and FLTb to 0V which
can be observed at J7.
7. Once again, place the short between VPWR and VMID at JP9. Apply 0 V to RSTb input at J6. This clears the fault and normal
operation is restored.
1.4 Quick Reference Tables
Table 1.2. Test Point Descriptions
Test Point
Description
Referenced to:
TP1
VDDA
GNDA
TP3
VPWR
VMID
TP4
VDDB
VMID
TP5
VMID
N/A
TP6
VSSB
VMID
TP7
VDDP
GNDA
TPV8
IGBT_GATE
VMID
TP9
GNDA
N/A
TPV9
DSAT
VMID
TPV10
MOSFET_D
GNDA
TPV11
MOSFET_G
GNDA
TPV12
CLMP
VSSB
UG168: Si8284-EVB User's Guide
Overview and Setup
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