9.4.1 Verify Free-run Mode Operation
Assuming no external clocks have been connected to the INPUT CLOCK differential SMA connectors (labeled “INx/INxB”) located
around the perimeter of the EVB, the DUT should now be operating in free-run mode, as the DUT will be locked to the crystal in this
case.
You can run a quick check to determine if the device is powered up and generating output clocks (and consuming power) by clicking on
the "Read All" button (bottom right-hand corner of
Figure 9.9 EVB GUI Window on page 15
) and then reviewing the voltage, current,
and power readings for each VDDx supply.
Note:
Shutting the VDD and VDDA power supplies “Off” and then “On” will power-down and reset the DUT. Every time you do this, to
reload the Silicon Labs-created default plan into the DUT’s register space, you must go back to the Wizard’s main menu and select
"Write Design to EVB".
Figure 9.10. Write Design to EVB
Failure to do the step above will cause the device to read in a pre-programmed plan from its non-volatile memory (NVM). However, the
plan loaded from the NVM may not be the latest plan recommended by Silicon Labs for evaluation.
At this point, you should verify the presence and frequencies of the output clocks (running in free-run mode from the crystal) using ap-
propriate external instrumentation connected to the output clock SMA connectors. To verify the output clocks are toggling at the correct
frequency and signal format, click on "View Design Report" as highlighted in the figure below.
UG372: Si5372 Evaluation Board User’s Guide
Using Si5372 EVB
silabs.com
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