Silicon Laboratories Si5040, User Manual

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Si5040-EVB
Rev. 0.4 5
Figure 7. Synchronous Test Clock
1.4. Reference Clock Details
The Si5040 can function without a reference clock and
meet all system jitter generation and jitter tolerance
specifications. However, the presence of a reference
clock provides the following capabilities:
 Ability to measure the frequency error of the input
data and generate a Loss-of-Lock indication if the
frequency error exceeds 1000 ppm with respect to
the reference clock.
 Only acquire lock if the input data is within 200 ppm.
 If the reference clock is synchronous, the Si5040
can operate in the clean, synchronous CMU mode
as defined in section 3.9.1 of the XFP specification.
A reference clock to the Si5040 can be input from an
external source, or it can be generated from the
onboard Si534. Since the clock from the Si534 is
linearly summed with the external reference clock input,
care must be taken to ensure that both clock sources
are not active at the same time. When the Si534 is
enabled (JP16 on), its output will be present at SMAs J1
and J5 for monitoring and/or system usage. When the
Si534 is OFF, a differential clock applied at J1 and J5
will be attenuated by 2.7 dB before it reaches the
REFCLK± inputs of the Si5040.
While an Si534 has the capability of generating any four
frequencies between 10 MHz and 1400 MHz, this Si534
has been programmed to generate four specific
frequencies. Jumpers JP17 and JP18 control the
FS[1:0] inputs to the Si534 (see Figure 6). The four
frequencies are as follows:
 155.52000 MHz Set FS[1:0] = 00
This is 1/64 of the SONET OC-192 rate of
9.95328e9 bps
 161.13281 MHz Set FS[1:0] = 01
This is 1/64 of the 10 GIGE LAN PHY rate of
10.3125e9 bps
 167.33165 MHz Set FS[1:0] = 10
This is 1/64 of the SONET OC-192 rate with 255/237
FEC overhead (10.709225e9 bps)
 173.37075 MHz Set FS[1:0] = 11
This is 1/64 of the 10 GIGE LAN Phy rate with 255/
237 FEC overhead (11.095727e9 bps)
The Si534 holds the above frequencies to within
±20 ppm over temperature (–40 to +85 °C) and voltage.
The XFP specification allows for an optional clean
synchronous CMU mode if the reference clock has
sufficiently low phase noise. See Section 3.9.1 and
Table 25 of the XFP specification. For the four
frequencies above, the typical phase noise of the Si534
is shown in Table 2 with the XFP requirements for
reference.
1.5. Crystal Cleaning
There is a crystal, Y1, on the evaluation board that is
located very close to the Si5040 for the purpose of jitter
improvement on the Txdout signal. Y1 is a 114.285 Mhz
third overtone crystal that is enabled by putting the
transmit CMU into crystal cleaning Mode 3. Even when
the Si5040 uses the crystal for transmit jitter
improvement, the transmit CMU is still continuously
agile across the entire operating range of 9.9 to
11.4 GHz. Of course, the transmit CMU may also
operate without the Y1 crystal and still be continuously
rate agile (mode 0). The layout for Y1 is specifically
designed for three different size crystals, 3.5x6 mm,
3.2x5 mm, and 2.5x3.2 mm.
1.6. RD Preemphasis
Even though the output data at the Si5040 RD pins has
very fast transitions, we have found that some
customers prefer some signal shaping of the RD output
signal at the XFI. Therefore, the Si5040 EVB that you
are receiving has a pre-emphasis circuit added to the
RD± outputs. This circuit is composed of a few resistors
and capacitors, all of which can be generic, low-cost
units. Because it is a passive circuit, it slightly
Table 2. Phase Noise
Frequency
Offset
Si534 Nominal
Performance
XFP Clean
Synch CMU
Specification
1 kHz –116 dBc/Hz –85 dBc
10 kHz –120 dBc/Hz –108 dBc
100 kHz –128 dBc/Hz –128 dBc
1 MHz –141 dBc/Hz –138 dBc
10 MHz –144 dBc/Hz –138 dBc