Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual Download Page 916

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26.5.28 ADCn_SINGLEFIFOCLEAR - Single FIFO Clear Register

Offset

Bit Position

0x08C

Reset

Access

Name

SINGLEFIFOCLEAR

Bit

Name

Reset

Access Description

31:1

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in

1.2 Conven-

tions

SINGLEFIFOCLEAR 0

Clear Single FIFO Content

Write a 1 to clear Single FIFO content.

26.5.29 ADCn_SCANFIFOCLEAR - Scan FIFO Clear Register

Offset

Bit Position

0x090

Reset

Access

Name

SCANFIFOCLEAR

Bit

Name

Reset

Access Description

31:1

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in

1.2 Conven-

tions

SCANFIFOCLEAR

Clear Scan FIFO Content

Write a 1 to clear Scan FIFO content.

Reference Manual

ADC - Analog to Digital Converter

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Summary of Contents for EFR32xG14 Wireless Gecko

Page 1: ...tigation Timers and Triggers 32 bit bus Peripheral Reflex System Serial Interfaces I O Ports Analog I F Lowest power mode with peripheral operational USART Low Energy UARTTM I2 C External Interrupts General Purpose I O Pin Reset Pin Wakeup ADC VDAC Analog Comparator EM3 Stop EM2 Deep Sleep EM1 Sleep EM4 Hibernate EM4 Shutoff EM0 Active Energy Management Brown Out Detector DC DC Converter Voltage R...

Page 2: ...3 Convolutional Encoding Decoding 34 2 14 Binary Block Encoding Decoding 34 2 15 Data Encryption and Authentication 35 2 16 Timers 36 2 17 RF Test Modes 36 3 System Processor 37 3 1 Introduction 37 3 2 Features 38 3 3 Functional Description 38 3 3 1 Interrupt Operation 39 3 3 2 Interrupt Request Lines IRQ 40 4 Memory and Bus System 41 4 1 Introduction 42 4 2 Functional Description 43 4 2 1 Periphe...

Page 3: ...Register 13 MHz 71 4 7 20 HFRCOCAL7 HFRCO Calibration Register 16 MHz 72 4 7 21 HFRCOCAL8 HFRCO Calibration Register 19 MHz 73 4 7 22 HFRCOCAL10 HFRCO Calibration Register 26 MHz 74 4 7 23 HFRCOCAL11 HFRCO Calibration Register 32 MHz 75 4 7 24 HFRCOCAL12 HFRCO Calibration Register 38 MHz 76 4 7 25 AUXHFRCOCAL0 AUXHFRCO Calibration Register 4 MHz 77 4 7 26 AUXHFRCOCAL3 AUXHFRCO Calibration Register...

Page 4: ...ation Register for DRIVESTRENGTH 1 INCBW 0 107 4 7 58 OPA0CAL6 OPA0 Calibration Register for DRIVESTRENGTH 2 INCBW 0 108 4 7 59 OPA0CAL7 OPA0 Calibration Register for DRIVESTRENGTH 3 INCBW 0 109 4 7 60 OPA1CAL4 OPA1 Calibration Register for DRIVESTRENGTH 0 INCBW 0 110 4 7 61 OPA1CAL5 OPA1 Calibration Register for DRIVESTRENGTH 1 INCBW 0 111 4 7 62 OPA1CAL6 OPA1 Calibration Register for DRIVESTRENG...

Page 5: ...d Register 138 7 5 5 MSC_ADDRB Page Erase Write Address Buffer 139 7 5 6 MSC_WDATA Write Data Register 139 7 5 7 MSC_STATUS Status Register 140 7 5 8 MSC_IF Interrupt Flag Register 141 7 5 9 MSC_IFS Interrupt Flag Set Register 142 7 5 10 MSC_IFC Interrupt Flag Clear Register 143 7 5 11 MSC_IEN Interrupt Enable Register 144 7 5 12 MSC_LOCK Configuration Lock Register 145 7 5 13 MSC_CACHECMD Flash C...

Page 6: ...hannel Linking Done Register Single Cycle RMW 183 8 6 7 LDMA_DBGHALT DMA Channel Debug Halt Register 184 8 6 8 LDMA_SWREQ DMA Channel Software Transfer Request Register 184 8 6 9 LDMA_REQDIS DMA Channel Request Disable Register 185 8 6 10 LDMA_REQPEND DMA Channel Requests Pending Register 185 8 6 11 LDMA_LINKLOAD DMA Channel Link Load Register 186 8 6 12 LDMA_REQCLEAR DMA Channel Request Clear Reg...

Page 7: ... 10 3 Functional Description 214 10 3 1 Energy Modes 215 10 3 2 Entering Low Energy Modes 219 10 3 3 Exiting a Low Energy Mode 221 10 3 4 Power Configurations 222 10 3 5 DC to DC Interface 226 10 3 6 Analog Peripheral Power Selection 228 10 3 7 Digital LDO Power Selection 229 10 3 8 IOVDD Connection 229 10 3 9 Voltage Scaling 230 10 3 10 EM23 Peripheral Retention Disable 232 10 3 11 Brown Out Dete...

Page 8: ...ontrol 265 10 5 24 EMU_DCDCSYNC DCDC Read Status Register 265 10 5 25 EMU_VMONAVDDCTRL VMON AVDD Channel Control 266 10 5 26 EMU_VMONALTAVDDCTRL Alternate VMON AVDD Channel Control 267 10 5 27 EMU_VMONDVDDCTRL VMON DVDD Channel Control 268 10 5 28 EMU_VMONIO0CTRL VMON IOVDD0 Channel Control 269 10 5 29 EMU_RAM1CTRL Memory Control Register 270 10 5 30 EMU_RAM2CTRL Memory Control Register 271 10 5 3...

Page 9: ...errupt Flag Register 336 11 5 23 CMU_IFS Interrupt Flag Set Register 338 11 5 24 CMU_IFC Interrupt Flag Clear Register 340 11 5 25 CMU_IEN Interrupt Enable Register 342 11 5 26 CMU_HFBUSCLKEN0 High Frequency Bus Clock Enable Register 0 344 11 5 27 CMU_HFPERCLKEN0 High Frequency Peripheral Clock Enable Register 0 345 11 5 28 CMU_HFRADIOALTCLKEN0 High Frequency Alternate Radio Peripheral Clock Enabl...

Page 10: ...70 12 5 6 SMU_PPUPATD0 PPU Privilege Access Type Descriptor 0 371 12 5 7 SMU_PPUPATD1 PPU Privilege Access Type Descriptor 1 373 12 5 8 SMU_PPUFS PPU Fault Status 374 13 RTCC Real Time Counter and Calendar 376 13 1 Introduction 376 13 2 Features 376 13 3 Functional Description 377 13 3 1 Counter 378 13 3 2 Capture Compare Channels 382 13 3 3 Interrupts and PRS Output 384 13 3 4 Energy Mode Availab...

Page 11: ...es 405 14 3 Functional Description 405 14 3 1 Clock Source 406 14 3 2 Debug Functionality 406 14 3 3 Energy Mode Handling 406 14 3 4 Register Access 406 14 3 5 Warning Interrupt 406 14 3 6 Window Interrupt 407 14 3 7 PRS as Watchdog Clear 408 14 3 8 PRS Rising Edge Monitoring 408 14 4 Register Map 409 14 5 Register Description 410 14 5 1 WDOG_CTRL Control Register Async Reg 410 14 5 2 WDOG_CMD Com...

Page 12: ...gister Access 457 16 3 6 Clock Sources 457 16 3 7 Input Filter 457 16 3 8 Edge Polarity 458 16 3 9 PRS and PCNTn_S0IN PCNTn_S1IN Inputs 458 16 3 10 Interrupts 458 16 3 11 Cascading Pulse Counters 460 16 4 Register Map 461 16 5 Register Description 462 16 5 1 PCNTn_CTRL Control Register Async Reg 462 16 5 2 PCNTn_CMD Command Register Async Reg 466 16 5 3 PCNTn_STATUS Status Register 466 16 5 4 PCNT...

Page 13: ...LKDIV Clock Division Register 510 17 5 6 I2Cn_SADDR Slave Address Register 510 17 5 7 I2Cn_SADDRMASK Slave Address Mask Register 511 17 5 8 I2Cn_RXDATA Receive Buffer Data Register Actionable Reads 511 17 5 9 I2Cn_RXDOUBLE Receive Buffer Double Data Register Actionable Reads 512 17 5 10 I2Cn_RXDATAP Receive Buffer Data Peek Register 512 17 5 11 I2Cn_RXDOUBLEP Receive Buffer Double Data Peek Regist...

Page 14: ...XP RX Buffer Double Data Extended Peek Register 577 18 5 13 USARTn_TXDATAX TX Buffer Data Extended Register 578 18 5 14 USARTn_TXDATA TX Buffer Data Register 579 18 5 15 USARTn_TXDOUBLEX TX Buffer Double Data Extended Register 580 18 5 16 USARTn_TXDOUBLE TX Buffer Double Data Register 581 18 5 17 USARTn_IF Interrupt Flag Register 582 18 5 18 USARTn_IFS Interrupt Flag Set Register 584 18 5 19 USART...

Page 15: ...r Actionable Reads 636 19 5 9 LEUARTn_RXDATAXP Receive Buffer Data Extended Peek Register 636 19 5 10 LEUARTn_TXDATAX Transmit Buffer Data Extended Register Async Reg 637 19 5 11 LEUARTn_TXDATA Transmit Buffer Data Register Async Reg 638 19 5 12 LEUARTn_IF Interrupt Flag Register 639 19 5 13 LEUARTn_IFS Interrupt Flag Set Register 640 19 5 14 LEUARTn_IFC Interrupt Flag Clear Register 641 19 5 15 L...

Page 16: ... 5 17 TIMERn_CCx_CCVP CC Channel Value Peek Register 702 20 5 18 TIMERn_CCx_CCVB CC Channel Buffer Register 703 20 5 19 TIMERn_DTCTRL DTI Control Register 704 20 5 20 TIMERn_DTTIME DTI Time Control Register 706 20 5 21 TIMERn_DTFC DTI Fault Configuration Register 708 20 5 22 TIMERn_DTOGEN DTI Output Generation Enable Register 710 20 5 23 TIMERn_DTFAULT DTI Fault Register 711 20 5 24 TIMERn_DTFAULT...

Page 17: ...Debug Mode 747 22 3 4 Energy Mode Availability 747 22 4 Register Map 748 22 5 Register Description 749 22 5 1 CRYOTIMER_CTRL Control Register 749 22 5 2 CRYOTIMER_PERIODSEL Interrupt Duration 750 22 5 3 CRYOTIMER_CNT Counter Value 751 22 5 4 CRYOTIMER_EM4WUEN Wake Up Enable 751 22 5 5 CRYOTIMER_IF Interrupt Flag Register 752 22 5 6 CRYOTIMER_IFS Interrupt Flag Set Register 752 22 5 7 CRYOTIMER_IFC...

Page 18: ...13 VDACn_CAL Calibration Register 783 23 5 14 VDACn_OPAx_APORTREQ Operational Amplifier APORT Request Status Register 784 23 5 15 VDACn_OPAx_APORTCONFLICT Operational Amplifier APORT Conflict Status Register 785 23 5 16 VDACn_OPAx_CTRL Operational Amplifier Control Register 786 23 5 17 VDACn_OPAx_TIMER Operational Amplifier Timer Control Register 789 23 5 18 VDACn_OPAx_MUX Operational Amplifier Mu...

Page 19: ...er 833 25 5 8 ACMPn_APORTREQ APORT Request Status Register 834 25 5 9 ACMPn_APORTCONFLICT APORT Conflict Status Register 835 25 5 10 ACMPn_HYSTERESIS0 Hysteresis 0 Register 837 25 5 11 ACMPn_HYSTERESIS1 Hysteresis 1 Register 838 25 5 12 ACMPn_ROUTEPEN I O Routing Pine Enable Register 839 25 5 13 ACMPn_ROUTELOC0 I O Routing Location Register 840 25 5 14 ACMPn_EXTIFCTRL External Override Interface C...

Page 20: ...FC Interrupt Flag Clear Register 907 26 5 17 ADCn_IEN Interrupt Enable Register 909 26 5 18 ADCn_SINGLEDATA Single Conversion Result Data Actionable Reads 910 26 5 19 ADCn_SCANDATA Scan Conversion Result Data Actionable Reads 910 26 5 20 ADCn_SINGLEDATAP Single Conversion Result Data Peek Register 911 26 5 21 ADCn_SCANDATAP Scan Sequence Result Data Peek Register 911 26 5 22 ADCn_SCANDATAX Scan Se...

Page 21: ... 28 3 1 Channel Configuration 933 28 3 2 Scan Sequence 934 28 3 3 Sensor Timing 935 28 3 4 Sensor Interaction 937 28 3 5 Sensor Sampling 938 28 3 6 Sensor Evaluation 939 28 3 7 Decoder 941 28 3 8 Measurement Results 944 28 3 9 VDAC Interface 945 28 3 10 ACMP Interface 945 28 3 11 ACMP and VDAC Duty Cycling 945 28 3 12 ADC Interface 946 28 3 13 DMA Requests 946 28 3 14 PRS Output 946 28 3 15 RAM 94...

Page 22: ...CONFB State Transition Configuration B Async Reg 992 28 5 27 LESENSE_BUFx_DATA Scan Results Async Reg 993 28 5 28 LESENSE_CHx_TIMING Scan Configuration Async Reg 994 28 5 29 LESENSE_CHx_INTERACT Scan Configuration Async Reg 995 28 5 30 LESENSE_CHx_EVAL Scan Configuration Async Reg 997 29 GPCRC General Purpose Cyclic Redundancy Check 999 29 1 Introduction 999 29 2 Features 999 29 3 Functional Descr...

Page 23: ...024 31 1 Introduction 1024 31 2 Features 1025 31 3 Usage and Programming Interface 1025 31 4 Functional Description 1026 31 4 1 Data and Key Registers 1027 31 4 2 Instructions and Execution 1029 31 4 3 Repeated Sequence 1034 31 4 4 AES 1035 31 4 5 SHA 1037 31 4 6 ECC 1037 31 4 7 GCM and GMAC 1038 31 4 8 DMA 1038 31 4 9 BUFC Data Transfer 1040 31 4 10 Debugging 1041 31 4 11 Example Cipher Block Cha...

Page 24: ... DATA0 Register Byte 13 Access No Bit Access 1073 31 6 30 CRYPTO_DATA0BYTE14 DATA0 Register Byte 14 Access No Bit Access 1074 31 6 31 CRYPTO_DATA0BYTE15 DATA0 Register Byte 15 Access No Bit Access 1074 31 6 32 CRYPTO_DDATA0 DDATA0 Register Access No Bit Access Actionable Reads 1075 31 6 33 CRYPTO_DDATA1 DDATA1 Register Access No Bit Access Actionable Reads 1075 31 6 34 CRYPTO_DDATA2 DDATA2 Registe...

Page 25: ...XTIPINSELL External Interrupt Pin Select Low Register 1115 32 5 12 GPIO_EXTIPINSELH External Interrupt Pin Select High Register 1118 32 5 13 GPIO_EXTIRISE External Interrupt Rising Edge Trigger Register 1120 32 5 14 GPIO_EXTIFALL External Interrupt Falling Edge Trigger Register 1121 32 5 15 GPIO_EXTILEVEL External Interrupt Level Register 1122 32 5 16 GPIO_IF Interrupt Flag Register 1123 32 5 17 G...

Page 26: ...t be used as this may lead to unpredictable behaviour Address The address for each register can be found by adding the base address of the module found in the Memory Map see Figure 4 2 Sys tem Address Space With Core and Code Space Listing on page 43 and the offset address for the register found in module Register Map Access Type The register access types used in the register descriptions are expl...

Page 27: ...o be initialized before use Note that read modify write operations on these registers before they are initialized results in undefined register values Pin Connections Pin connections are given with a module prefix followed by a short pin name CMU_CLKOUT1 Clock management unit clock output pin number 1 The location for the pin names given in the module documentation can be found in the device speci...

Page 28: ...vity selectivity and blocking Excellent transmitter performance including programmable output power low phase noise and PA ramping Ultra Low Energy RF Detection for wake up from any Energy Mode through RFSENSE Configurable protocol support including standards and customer developed protocols Preamble and frame synchronization insertion in transmit and recovery in receive Flexible CRC support inclu...

Page 29: ...UFC RFSENSE MOD FRC RAC Frequency Synthesizer PGA PA I Q RF Frontend LNA RFSENSE PA I Q RF Frontend LNA To 2 4 GHz receive I Q mixers and PA To Sub GHz receive I Q mixers and PA To Sub GHz and 2 4 GHz PA Sub GHz 2 4 GHz BALUN CRYPTO CRC True Random Number Generator SMU Core Memory ARM CortexTM M4 processor with DSP extensions FPU and MPU Debug Interface RAM Memory LDMA Controller Flash Program Mem...

Page 30: ...is Counter Mode GCM Cipher Block Chaining CBC Cipher Feedback CFB and Output Feedback OFB Accelerated SHA 1 and SHA 2 SHA 224 SHA 256 Accelerated Elliptic Curve Cryptography ECC with binary or prime fields Flexible 256 bit ALU and sequencer True Random Number Generator TRNG General Purpose Cyclic Redundancy Check Programmable 16 bit polynomial fixed 32 bit polynomial The General Purpose Cyclic Red...

Page 31: ... 1 differential channel Up to 2 Operational Amplifiers Supports rail to rail inputs and outputs Programmable gain Current Digital to Analog Converter Source or sink a configurable constant current 2 Analog Comparator Programmable speed current Analog Port Low Energy Sensor Interface Autonomous sensor monitoring in deep sleep mode Wide range of supported sensors including LC sensors and capacitive ...

Page 32: ... RC oscillators can be calibrated against either of the crystal oscillators in order to compensate for temperature and voltage supply variations Hardware support is included to measure the frequency of various oscillators against each other Oscillator and clock management is available through the Clock Management Unit CMU see section 11 CMU Clock Management Unit for details 2 5 RF Frequency Synthe...

Page 33: ...cation Overflow and underflow detection In receive mode data following frame synchronization is moved directly from the demodulator to the buffer storage In transmit mode data following the inserted preamble and synchronization word is moved directly from the buffer storage to the modu lator 2 10 Unbuffered Data Transfer For most system designs it is recommended to use the data buffering within EF...

Page 34: ...rmed by the Frame Controller FRC module Constraint length configurable up to 7 for the highest robustness Configurable puncturing to achieve rates between 1 2 rate and full rate Configurable soft decision or hard decision decoding Convolutional coding may be used together with the symbol interleaver to improve robustness against burst errors 2 14 Binary Block Encoding Decoding EFR32 includes hardw...

Page 35: ...n Decryption Authentication Comment ECB Yes Electronic Code Book CTR Yes Counter mode CCM Yes Yes Counter with CBC MAC CCM Yes Yes CCM with encryption only and integrity only capabilities GCM Yes Yes Galois Counter Mode CBC Yes Cipher Block Chaining CBC MAC Yes Cipher Block Chaining Mes sage Authentication Code CMAC Yes Cipher based MAC CFB Yes Cipher Feedback OFB Yes Output Feedback The CRYPTO mo...

Page 36: ...perating System timer WDOG 1 Low frequency LFXO LFRCO or ULFRCO Watch dog timer Once enabled this module must be periodically accessed If not this is consid ered an error and the EFR32 is reset in order to recover the system LETIMER 1 Low frequency LFXO LFRCO or ULFRCO Low energy general purpose timer Advanced interconnect features allows synchronization between timers This includes Start stop any...

Page 37: ...a strict cost and power consumption budget How Combined with the ultra low energy peripherals available in EFR32 devices the Cortex M4 process or s Harvard architecture 3 stage pipeline single cy cle instructions Thumb 2 instruction set support and fast interrupt handling make it perfect for 8 bit 16 bit and 32 bit applications 3 1 Introduction The ARM Cortex M4 32 bit RISC processor provides outs...

Page 38: ...nt 32 bit migration choice for 8 16 bit architecture based designs Simplified stack based programmer s model is compatible with traditional ARM architecture and retains the programming simplici ty of legacy 8 bit and 16 bit architectures Alligned or unaligned data storage and access Contiguous storage of data requiring different byte lengths Data access in a single core access cycle Integrated pow...

Page 39: ...Extraneous Interrupts There can be latencies in the system such that clearing an interrupt flag could take longer than leaving an Interrupt Service Routine ISR This can lead to the ISR being re entered as the interrupt flag has yet to clear immediately after leaving the ISR To avoid this when clearing an interrupt flag at the end of an ISR the user should execute ARM s Data Synchronization Barrier...

Page 40: ...0 12 USART0_RX 13 USART0_TX 14 ACMP0 ACMP1 15 ADC0 16 IDAC0 17 I2C0 18 GPIO_ODD 19 TIMER1 20 USART1_RX 21 USART1_TX 22 LEUART0 23 PCNT0 24 CMU 25 MSC 26 CRYPTO0 27 LETIMER0 31 RTCC 33 CRYOTIMER 35 FPUEH 36 SMU 37 WTIMER0 38 VDAC0 39 LESENSE 40 TRNG0 Reference Manual System Processor silabs com Building a more connected world Rev 1 1 40 ...

Page 41: ...nd enables frequent use of the ultra low en ergy modes EM2 Deep Sleep and EM3 Stop How Low energy and non volatile Flash memory stores program and application data in all energy modes and can easily be reprogrammed in system Low leakage RAM with data retention in EM0 Active to EM3 Stop removes the data restore time penalty and the DMA ensures fast autonomous transfers with predictable response tim...

Page 42: ...ntire memory space except Code memory valid address range 0x20000000 0xFFFFFFFF DMA Can access the entire memory space except the internal core memory region and the DMEM code region Sequencer Code Used for instruction fetches and data accesses Instruction fetches still come from data memory valid address range 0x00000000 0x0FFFFFFF 0x20000000 0x3FFFFFFF Sequencer System Can access entire memory s...

Page 43: ...ure 4 2 System Address Space With Core and Code Space Listing on page 43 Figure 4 2 System Address Space With Core and Code Space Listing Additionally the peripheral address map is detailed by Figure 4 3 System Address Space With Peripheral Listing on page 44 Reference Manual Memory and Bus System silabs com Building a more connected world Rev 1 1 43 ...

Page 44: ...AM effi ciently the SRAM is also mapped in the code space at address 0x10000000 When running code from this space the Cortex M4 fetches instructions through the I D Code bus interface leaving the System bus interface for data access The SRAM mapped into the code space can however only be accessed by the CPU and not any other bus masters e g DMA See 4 5 SRAM for more detailed info on the system SRA...

Page 45: ...omic single bit writes to the embedded SRAM and peripherals of the EFR32 Note Bit banding is only available through the CPU No other AHB masters e g DMA can perform Bit banding operations Using a standard approach to modify a single register or SRAM bit in the aliased regions would require software to read the value of the byte half word or word containing the bit modify the bit and then write the...

Page 46: ...register register register OR mask For bit clear operations bit locations that are 1 in the bit mask will be cleared in the destination register register register AND NOT mask Note It is possible to combine bit clear and bit set operations in order to arbitrarily modify multi bit register fields without affecting other fields in the same register In this case care should be taken to ensure that th...

Page 47: ...TIMER0 0x40010400 0x40010800 USART1 0x40010000 0x40010400 USART0 0x4000C000 0x4000C400 I2C0 0x4000A000 0x4000B000 GPIO 0x40008000 0x40008400 VDAC0 0x40006000 0x40006400 IDAC0 0x40002000 0x40002400 ADC0 0x40000400 0x40000800 ACMP1 0x40000000 0x40000400 ACMP0 Table 4 3 Low Energy Peripherals Address Range Module Name 0x40055000 0x40055400 LESENSE 0x40052400 0x40052800 WDOG1 0x40052000 0x40052400 WDO...

Page 48: ...h of 5x a single AHB interface The Cortex M4 DMA Controller and peripherals not peripherals in the low frequency clock domain run on clocks which can be pre scaled separately Clocks and prescaling are described in more detail in 11 CMU Clock Management Unit This section describes the expected bus wait states for a peripheral based on its frequency relative to the HFCLK frequency For this discussio...

Page 49: ...ave Figure 4 4 Bus Access Latency General Case Note that a latency of 1 cycle corresponds to 0 wait states Additionally for back to back accesses to the same peripheral the throughput in number of cycles per transfer is given by Nbus cycles Nslave cycles fHFCLK fPERCLK write accesses Nbus cycles Nslave cycles 1 fHFCLK fPERCLK read accesses Figure 4 5 Bus Access Throughput Back to Back Transfers La...

Page 50: ...ghput in number of cycles per transfer is given by Nbus cycles max fHFCLK fPERCLK 2 Nslave cycles fHFCLK fPERCLK write accesses Nbus cycles Nslave cycles 1 fHFCLK fPERCLK read accesses Figure 4 8 Bus Access Throughput Back to Back Transfers Lastly in the highest performing case where PERCLK equals HFCLK and the slave does not introduce any additional wait states the access latency in number of cyc...

Page 51: ...when an instruction fetch results in a bus fault invalid data may be cached This means that the next time the instruction that caused the bus fault is fetched the processor core will get the invalid cached data without any bus fault In order to avoid invalid cached data propagation to the processor core software should man ually invalidate cache by writing 1 to MSC_CMD_INVCACHE bitfield at the eve...

Page 52: ... the Low Energy Peripheral being accessed Registers requiring synchronization are marked Async Reg in their description header Note On the Gecko series of devices all LE peripherals are subject to delayed synchronization Register 0 Register 1 Register n Synchronizer 0 Synchronizer 1 Synchronizer n Register 0 Sync Register 1 Sync Register n Sync Write request 0 n Syncbusy Register 0 Syncbusy Regist...

Page 53: ...k Low Frequency Clock High Frequency Clock Domain Low Frequency Clock Domain Write request 0 Write request 1 Write request n Figure 4 12 Write Operation to Low Energy Peripherals 4 3 1 2 Immediate Synchronization In contrast to the peripherals with delayed synchronization peripherals with immediate synchronization do not experience a delay from a value is written to it takes effect in the peripher...

Page 54: ...egister In all Low Energy Peripheral with delayed synchronization there is a module_name _FREEZE register e g RTCC_FREEZE The register contains a bit named REGFREEZE If precise control of the synchronization process is required this bit may be utilized When REGFREEZE is set the synchronization process is halted allowing the software to write multiple Low Energy registers before starting the synchr...

Page 55: ...n use Data retention of the entire memory in EM0 Active to EM3 Stop Note The individual RAM sections may be smaller on some parts however the RAM AHB slaves maintain a contiguous address map For example if RAM0 is half size on a part then RAM1 is relocated to begin immediately after RAM0 s last address Using the provided software header files and linker scripts allows handling of this remapping in...

Page 56: ...DC0CAL1 RO ADC0 calibration register 1 0x068 ADC0CAL2 RO ADC0 calibration register 2 0x06C ADC0CAL3 RO ADC0 calibration register 3 0x080 HFRCOCAL0 RO HFRCO Calibration Register 4 MHz 0x08C HFRCOCAL3 RO HFRCO Calibration Register 7 MHz 0x098 HFRCOCAL6 RO HFRCO Calibration Register 13 MHz 0x09C HFRCOCAL7 RO HFRCO Calibration Register 16 MHz 0x0A0 HFRCOCAL8 RO HFRCO Calibration Register 19 MHz 0x0A8 ...

Page 57: ...BW 1 0x198 OPA0CAL2 RO OPA0 Calibration Register for DRIVESTRENGTH 2 INCBW 1 0x19C OPA0CAL3 RO OPA0 Calibration Register for DRIVESTRENGTH 3 INCBW 1 0x1A0 OPA1CAL0 RO OPA1 Calibration Register for DRIVESTRENGTH 0 INCBW 1 0x1A4 OPA1CAL1 RO OPA1 Calibration Register for DRIVESTRENGTH 1 INCBW 1 0x1A8 OPA1CAL2 RO OPA1 Calibration Register for DRIVESTRENGTH 2 INCBW 1 0x1AC OPA1CAL3 RO OPA1 Calibration ...

Page 58: ... 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO RO Name TEMP CRC Bit Name Access Description 31 24 Reserved Reserved for future use 23 16 TEMP RO Calibration temperature as an usigned int in DegC 25 25DegC 15 0 CRC RO CRC of DI page CRC 16 CCITT Reference Manual Memory and Bus System silabs com Building a more connected world Rev 1 1 58 ...

Page 59: ...RO MCM Revision Value Mode Description 1 REV1 Revision 1 255 NONE No external component present 15 8 CONNECTION RO Connection protocal to external interface Value Mode Description 1 SPI SPI control interface 255 NONE None 7 0 TYPE RO External Component Value Mode Description 1 IS25LQ040B IS25LQ040B JWLE1 512kB Serial Flash 2 AT25S041 AT25S041 DWFHT 512kB Serial Flash 255 NONE None Reference Manual...

Page 60: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO Name OUI48H Bit Name Access Description 31 16 Reserved Reserved for future use 15 0 OUI48H RO Upper two Octets of EUI48 Organizationally Unique Identifier 4 7 5 CUSTOMINFO Custom information Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO Name PARTNO Bit Name Access Description 31...

Page 61: ...SIZE 10 0xFF Ie the value 0xFF 512 bytes 23 16 PINCOUNT RO Device pin count as unsigned integer eg 48 15 8 PKGTYPE RO Package Identifier as character Value Mode Description 74 WLCSP WLCSP package 76 BGA BGA package 77 QFN QFN package 81 QFP QFP package 7 0 TEMPGRADE RO Temperature Grade of product as unsigned integer enumeration Value Mode Description 0 N40TO85 40 to 85degC 1 N40TO125 40 to 125deg...

Page 62: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO Name UNIQUEH Bit Name Access Description 31 0 UNIQUEH RO High 32 bits of device unique number 4 7 9 MSIZE Flash and SRAM Memory size in kB Offset Bit Position 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO RO Name SRAM FLASH Bit Name Access Description 31 16 SRAM RO Ram size kbyte count ...

Page 63: ...27 EFR32FG1V EFR32 Flex Gecko Family Series 1 Device Config 1 28 EFR32MG12P EFR32 Mighty Gecko Family Series 1 Device Config 2 29 EFR32MG12B EFR32 Mighty Gecko Family Series 1 Device Config 2 30 EFR32MG12V EFR32 Mighty Gecko Family Series 1 Device Config 2 31 EFR32BG12P EFR32 Blue Gecko Family Series 1 Device Config 2 32 EFR32BG12B EFR32 Blue Gecko Family Series 1 Device Config 2 33 EFR32BG12V EFR...

Page 64: ...evice Family 72 EFM32GG EFM32 Giant Gecko Device Family 72 GG EFM32 Giant Gecko Device Family 73 TG EFM32 Tiny Gecko Device Family 73 EFM32TG EFM32 Tiny Gecko Device Family 74 EFM32LG EFM32 Leopard Gecko Device Family 74 LG EFM32 Leopard Gecko Device Family 75 EFM32WG EFM32 Wonder Gecko Device Family 75 WG EFM32 Wonder Gecko Device Family 76 ZG EFM32 Zero Gecko Device Family 76 EFM32ZG EFM32 Zero ...

Page 65: ...ription 31 8 Reserved Reserved for future use 7 0 DEVINFOREV RO DEVINFO layout revision as unsigned integer initially 1 4 7 12 EMUTEMP EMU Temperature Calibration Information Offset Bit Position 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO Name EMUTEMPROOM Bit Name Access Description 31 8 Reserved Reserved for future use 7 0 EMUTEMPROOM RO E...

Page 66: ...n 31 Reserved Reserved for future use 30 24 GAIN2V5 RO Gain for 2 5V reference 23 20 NEGSEOFFSET2V5 RO Negative single ended offset for 2 5V reference 19 16 OFFSET2V5 RO Offset for 2 5V reference 15 Reserved Reserved for future use 14 8 GAIN1V25 RO Gain for 1 25V reference 7 4 NEGSEOFFSET1V25 RO Negative single ended offset for 1 25V reference 3 0 OFFSET1V25 RO Offset for 1 25V reference Reference...

Page 67: ...rved for future use 30 24 GAIN5VDIFF RO Gain for for 5V differential reference 23 20 NEGSEOFFSET5VDIFF RO Negative single ended offset with for 5V differential reference 19 16 OFFSET5VDIFF RO Offset for 5V differential reference 15 Reserved Reserved for future use 14 8 GAINVDD RO Gain for VDD reference 7 4 NEGSEOFFSETVDD RO Negative single ended offset for VDD reference 3 0 OFFSETVDD RO Offset for...

Page 68: ...Reserved Reserved for future use 7 4 NEGSEOFFSET2XVDD RO Negative single ended offset for 2XVDD reference 3 0 OFFSET2XVDD RO Offset for 2XVDD reference 4 7 16 ADC0CAL3 ADC0 calibration register 3 Offset Bit Position 0x06C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO Name TEMPREAD1V25 Bit Name Access Description 31 16 Reserved Reserved for future u...

Page 69: ...emperature Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 T...

Page 70: ...emperature Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 T...

Page 71: ...emperature Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 T...

Page 72: ...emperature Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 T...

Page 73: ...emperature Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 T...

Page 74: ...Temperature Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 ...

Page 75: ...Temperature Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 ...

Page 76: ...Temperature Coefficient Trim on Comparator Reference 27 FINETUNINGEN RO HFRCO enable reference for fine tuning 26 25 CLKDIV RO HFRCO Clock Output Divide 24 LDOHP RO HFRCO LDO High Power Mode 23 21 CMPBIAS RO HFRCO Comparator Bias Current 20 16 FREQRANGE RO HFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO HFRCO Fine Tuning Value 7 Reserved Reserved for future use 6 0 ...

Page 77: ...ure Coefficient Trim on Comparator Ref erence 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for futu...

Page 78: ...ure Coefficient Trim on Comparator Ref erence 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for futu...

Page 79: ...ture Coefficient Trim on Comparator Ref erence 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for fut...

Page 80: ...ture Coefficient Trim on Comparator Ref erence 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for fut...

Page 81: ...ture Coefficient Trim on Comparator Ref erence 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for fut...

Page 82: ...ture Coefficient Trim on Comparator Ref erence 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for fut...

Page 83: ...ture Coefficient Trim on Comparator Ref erence 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for fut...

Page 84: ...ture Coefficient Trim on Comparator Ref erence 27 FINETUNINGEN RO AUXHFRCO enable reference for fine tuning 26 25 CLKDIV RO AUXHFRCO Clock Output Divide 24 LDOHP RO AUXHFRCO LDO High Power Mode 23 21 CMPBIAS RO AUXHFRCO Comparator Bias Current 20 16 FREQRANGE RO AUXHFRCO Frequency Range 15 14 Reserved Reserved for future use 13 8 FINETUNING RO AUXHFRCO Fine Tuning Value 7 Reserved Reserved for fut...

Page 85: ...98THRESCOARSE RO ALTAVDD 2 98 V Coarse Threshold Adjust 27 24 ALTAVDD2V98THRESFINE RO ALTAVDD 2 98 V Fine Threshold Adjust 23 20 ALTAVDD1V86THRESCOARSE RO ALTAVDD 1 86 V Coarse Threshold Adjust 19 16 ALTAVDD1V86THRESFINE RO ALTAVDD 1 86 V Fine Threshold Adjust 15 12 AVDD2V98THRESCOARSE RO AVDD 2 98 V Coarse Threshold Adjust 11 8 AVDD2V98THRESFINE RO AVDD 2 98 V Fine Threshold Adjust 7 4 AVDD1V86TH...

Page 86: ...O02V98THRESCOARSE RO IO0 2 98 V Coarse Threshold Adjust 27 24 IO02V98THRESFINE RO IO0 2 98 V Fine Threshold Adjust 23 20 IO01V86THRESCOARSE RO IO0 1 86 V Coarse Threshold Adjust 19 16 IO01V86THRESFINE RO IO0 1 86 V Fine Threshold Adjust 15 12 DVDD2V98THRESCOARSE RO DVDD 2 98 V Coarse Threshold Adjust 11 8 DVDD2V98THRESFINE RO DVDD 2 98 V Fine Threshold Adjust 7 4 DVDD1V86THRESCOARSE RO DVDD 1 86 V...

Page 87: ...V98THRESCOARSE RO FVDD 2 98 V Coarse Threshold Adjust 27 24 FVDD2V98THRESFINE RO FVDD 2 98 V Fine Threshold Adjust 23 20 FVDD1V86THRESCOARSE RO FVDD 1 86 V Coarse Threshold Adjust 19 16 FVDD1V86THRESFINE RO FVDD 1 86 V Fine Threshold Adjust 15 12 PAVDD2V98THRESCOARSE RO PAVDD 2 98 V Coarse Threshold Adjust 11 8 PAVDD2V98THRESFINE RO PAVDD 2 98 V Fine Threshold Adjust 7 4 PAVDD1V86THRESCOARSE RO PA...

Page 88: ... Bit Name Access Description 31 24 SOURCERANGE3TUNING RO Calibrated middle step 16 of current source mode range 3 23 16 SOURCERANGE2TUNING RO Calibrated middle step 16 of current source mode range 2 15 8 SOURCERANGE1TUNING RO Calibrated middle step 16 of current source mode range 1 7 0 SOURCERANGE0TUNING RO Calibrated middle step 16 of current source mode range 0 Reference Manual Memory and Bus Sy...

Page 89: ... current sink mode range 1 7 0 SINKRANGE0TUNING RO Calibrated middle step 16 of current sink mode range 0 4 7 38 DCDCLNVCTRL0 DCDC Low noise VREF Trim Register 0 Offset Bit Position 0x168 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO RO RO RO Name 3V0LNATT1 1V8LNATT1 1V8LNATT0 1V2LNATT0 Bit Name Access Description 31 24 3V0LNATT1 RO DCDC LNVREF Tri...

Page 90: ...TT0LPCMPBIAS0 Bit Name Access Description 31 24 1V8LPATT0LPCMPBIAS1 RO DCDC LPVREF Trim for 1 8V output LPATT 0 LPCMPBIAS 1 23 16 1V2LPATT0LPCMPBIAS1 RO DCDC LPVREF Trim for 1 2V output LPATT 0 LPCMPBIAS 1 15 8 1V8LPATT0LPCMPBIAS0 RO DCDC LPVREF Trim for 1 8V output LPATT 0 LPCMPBIAS 0 7 0 1V2LPATT0LPCMPBIAS0 RO DCDC LPVREF Trim for 1 2V output LPATT 0 LPCMPBIAS 0 Reference Manual Memory and Bus S...

Page 91: ...TT0LPCMPBIAS2 Bit Name Access Description 31 24 1V8LPATT0LPCMPBIAS3 RO DCDC LPVREF Trim for 1 8V output LPATT 0 LPCMPBIAS 3 23 16 1V2LPATT0LPCMPBIAS3 RO DCDC LPVREF Trim for 1 2V output LPATT 0 LPCMPBIAS 3 15 8 1V8LPATT0LPCMPBIAS2 RO DCDC LPVREF Trim for 1 8V output LPATT 0 LPCMPBIAS 2 7 0 1V2LPATT0LPCMPBIAS2 RO DCDC LPVREF Trim for 1 2V output LPATT 0 LPCMPBIAS 2 Reference Manual Memory and Bus S...

Page 92: ...TT1LPCMPBIAS0 Bit Name Access Description 31 24 3V0LPATT1LPCMPBIAS1 RO DCDC LPVREF Trim for 3 0V output LPATT 1 LPCMPBIAS 1 23 16 1V8LPATT1LPCMPBIAS1 RO DCDC LPVREF Trim for 1 8V output LPATT 1 LPCMPBIAS 1 15 8 3V0LPATT1LPCMPBIAS0 RO DCDC LPVREF Trim for 3 0V output LPATT 1 LPCMPBIAS 0 7 0 1V8LPATT1LPCMPBIAS0 RO DCDC LPVREF Trim for 1 8V output LPATT 1 LPCMPBIAS 0 Reference Manual Memory and Bus S...

Page 93: ...IAS 3 15 8 3V0LPATT1LPCMPBIAS2 RO DCDC LPVREF Trim for 3 0V output LPATT 1 LPCMPBIAS 3 7 0 1V8LPATT1LPCMPBIAS2 RO DCDC LPVREF Trim for 1 8V output LPATT 1 LPCMPBIAS 2 4 7 43 DCDCLPCMPHYSSEL0 DCDC LPCMPHYSSEL Trim Register 0 Offset Bit Position 0x17C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO RO Name LPCMPHYSSELLPATT1 LPCMPHYSSELLPATT0 Bit Name A...

Page 94: ...CMPBIAS2 LPCMPHYSSELLPCMPBIAS1 LPCMPHYSSELLPCMPBIAS0 Bit Name Access Description 31 24 LPCMPHYSSELLPCMPBIAS3 RO DCDC LPCMPHYSSEL Trim LPCMPBIAS 3 23 16 LPCMPHYSSELLPCMPBIAS2 RO DCDC LPCMPHYSSEL Trim LPCMPBIAS 2 15 8 LPCMPHYSSELLPCMPBIAS1 RO DCDC LPCMPHYSSEL Trim LPCMPBIAS 1 7 0 LPCMPHYSSELLPCMPBIAS0 RO DCDC LPCMPHYSSEL Trim LPCMPBIAS 0 Reference Manual Memory and Bus System silabs com Building a m...

Page 95: ...GAINERRTRIMVDDANAEXTPIN RO Gain Error Trim Value for DAC main output using references VDDANA and EXTPIN 23 18 GAINERRTRIM2V5 RO Gain Error Trim Value for DAC main output using reference 2V5 17 12 GAINERRTRIM1V25 RO Gain Error Trim Value for DAC main output using reference 1V25 11 6 GAINERRTRIM2V5LN RO Gain Error Trim Value for DAC main output using reference 2V5LN 5 0 GAINERRTRIM1V25LN RO Gain Err...

Page 96: ...EXTPI NALT RO Gain Error Trim Value for DAC alternative output using referen ces VDDANA and EXTPIN 23 18 GAINERRTRIM2V5ALT RO Gain Error Trim Value for DAC alternative output using reference 2V5 17 12 GAINERRTRIM1V25ALT RO Gain Error Trim Value for DAC alternative output using reference 1V25 11 6 GAINERRTRIM2V5LNALT RO Gain Error Trim Value for DAC alternative output using reference 2V5LN 5 0 GAIN...

Page 97: ...iption 31 12 Reserved Reserved for future use 11 8 GAINERRTRIMCH1B RO Gain Error Trim Value for Channel 1 for references 2V5LN 2V5 7 4 GAINERRTRIMCH1A RO Gain Error Trim Value for Channel 1 for references 1V25LN 1V25 VDDANA EXTPIN 3 Reserved Reserved for future use 2 0 OFFSETTRIM RO Input Buffer Offset Calibration Value for all DAC references Reference Manual Memory and Bus System silabs com Build...

Page 98: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 99: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 100: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 101: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 102: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 103: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 104: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 105: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 106: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 107: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 108: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 109: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 110: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 111: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 112: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 113: ...ion Value 25 Reserved Reserved for future use 24 20 OFFSETP RO OPA Non Inverting Input Offset Configuration Value 19 Reserved Reserved for future use 18 17 GM3 RO Gm3 Trim Value 16 Reserved Reserved for future use 15 13 GM RO Gm Trim Value 12 Reserved Reserved for future use 11 10 CM3 RO Compensation cap Cm3 trim value 9 Reserved Reserved for future use 8 5 CM2 RO Compensation cap Cm2 trim value 4...

Page 114: ... enables the user to commu nicate using a wide range of data rates modulation and frame formats How Dynamic or fixed frame lengths optional address recognition flexible CRC and crypto schemes makes the EFR32 perfectly suit any application us ing low or medium data rate radio communication Reference Manual Radio Transceiver silabs com Building a more connected world Rev 1 1 114 ...

Page 115: ...ransceiver CRC Figure 5 1 Radio Overview During transmission TX the Radio Controller enables the SYNTH Modulator and PA The Modulator requests data from the Frame Controller which reads data from a buffer Based upon modulation format and data to send the Modulator manipulates the SYNTH to output the correct frequency and phase When the whole frame has been transmitted the radio can automatically s...

Page 116: ...t Action Group JTAG interface For more technical information about the debug interface the reader is referred to ARM Cortex M4 Technical Reference Manual ARM CoreSight Components Technical Reference Manual ARM Debug Interface v5 Architecture Specification IEEE Standard for Test Access Port and Boundary Scan Architecture IEEE 1149 1 2013 6 2 Features Debug Access Port Serial Wire JTAG DAPSWJ Implem...

Page 117: ...consumption measurements 6 3 3 Authentication Access Point The Authentication Acces Point AAP is a set of registers that provide a minimal amount of debugging and system level commands The AAP registers contain commands to issue a FLASH erase a system reset a CRC of user code pages and stalling the system bus The user must program the APSEL bit field to 255 inside of the ARM DAPSWJ Debug Port SELE...

Page 118: ...echanism is controlled by the Authentication Access Port AAP as illustrated by Figure 6 1 AAP Authentication Access Port on page 118 SW DP AHB AP Cortex SerialWire debug interface DEVICEERASE Authentication Access Port AAP ERASEBUSY ALW 3 0 0xF DLW 3 0 0xF Figure 6 1 AAP Authentication Access Port If the DLW is cleared the device is locked If the device is locked and the the AAP Lock Word ALW has ...

Page 119: ...he Cortex M4 executes code For example the first few instructions may disconnect the debugger pins When this occurs it is difficult to connect the debugger and halt the Cortex M4 before the Cortex M4 starts to execute By holding down pin reset issuing the System Bus Stall AAP instruction then releasing pin reset the debugger can stall the system bus before the Cortex M4 has a chance to execute Bec...

Page 120: ... erased the SRAM is cleared and then the Lock Bit LB page is erased This also includes the Debug Lock Word DLW causing debug access to be enabled after the next reset The in formation block User Data page UD is left unchanged but the User data page Lock Word ULW is erased This register is write enabled from the AAP_CMDKEY register 6 5 2 AAP_CMDKEY Command Key Register Offset Bit Position 0x004 31 ...

Page 121: ...ERASEBUSY 0 R Device Erase Command Status This bit is set when a device erase is executing 6 5 4 AAP_CTRL Control Register Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access RW Name SYSBUSSTALL Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More informatio...

Page 122: ...command is not available if debug access or AAP is locked 6 5 6 AAP_CRCSTATUS CRC Status Register Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name CRCBUSY Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 CRCBUS...

Page 123: ...C Execution Set this to the address the CRC executes on 6 5 8 AAP_CRCRESULT CRC Result Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name CRCRESULT Bit Name Reset Access Description 31 0 CRCRESULT 0x00000000 R CRC Result of the CRCADDRESS Result of the CRC calculation using the CRCADDRESS Reference...

Page 124: ... 9 8 7 6 5 4 3 2 1 0 Reset 0x26E60011 Access R Name ID Bit Name Reset Access Description 31 0 ID 0x26E60011 R AAP Identification Register Access port identification register in compliance with the ARM ADI v5 specification JEDEC Manufacturer ID Reference Manual DBG Debug Interface silabs com Building a more connected world Rev 1 1 124 ...

Page 125: ...ng minimum energy consump tion while eliminating the need for external program ming voltage to erase the memory An easy to use write and erase interface is supported by an internal fixed frequency oscillator and autonomous flash tim ing and control reduces software complexity while not using other timer resources Application code may dynamically scale between high energy optimization and high code...

Page 126: ... EM0 Active DMA write support in EM0 Active and EM1 Sleep Core clock independent Flash timing Internal oscillator and internal timers for precise and autonomous Flash timing General purpose timers are not occupied during Flash erase and write operations Configurable interrupt erase abort Improved interrupt predictability Memory and bus fault control Security features Lockable debug access Page loc...

Page 127: ...s Reserved 0x00040000 Reserved for flash ex pansion 24 MB Information 0 0x0FE00000 Software debug Yes User Data UD 2KB 0x0FE00800 Reserved 1 0x0FE04000 Write Software debug Erase Debug only Yes Lock Bits LB 2KB 0x0FE04800 Reserved 2 0x0FE081B0 Yes Device Information DI 1KB 0x0FE08400 Reserved 2 0x0FE0C000 1KB 0x0FE0C400 Reserved 0x0FE10000 Software debug Yes Bootloader BL 16 KB 10 0x0FE13800 Reser...

Page 128: ...on Access Point Note that the AAP is only accessible from the debug interface and can not be accessed from the Cortex M4 core Word 125 is the mass erase lock word MLW Bit 0 locks the entire flash The mass erase lock bits will not have any effect on device erases initiated from the Authenitcation Access Port AAP registers The AAP is described in more detail in 6 3 3 Authentication Ac cess Point Wor...

Page 129: ...ay cause the device to be come non functional and irrevocably locked 7 3 5 Device Revision Family FamilyAlt RevMajor RevMajorAlt RevMinor can be accessed through ROM Table The Revision number is extracted from the PID2 and PID3 registers as illustrated in Table 7 3 Revision Number Extraction on page 129 The Rev 7 4 and Rev 3 0 must be com bined to form the complete revision number Revision 7 0 Tab...

Page 130: ...mand wakeup and interrupt of MSC_IF PWRUPF will be flaged if the MSC_IEN PWRUPF is set 7 3 8 Wait states Table 7 5 Flash Wait States Wait States Frequency WS0 no more than 25 MHz WS1 above 25 MHz and no more than 40 MHz 7 3 8 1 One Wait state Access After reset the HFCORECLK is normally 19 MHz from the HFRCO and the MODE field of the MSC_READCTRL register is set to WS1 one wait state The reset val...

Page 131: ...to the MODE field of the MSC_READCTRL register For frequencies above 26 MHz use the WS1SCBTP mode and for frequencies above 40 MHz use the WS2SCBTP mode An increased performance penalty per clock cycle must be expected compared to WS0SCBTP mode The perform ance penalty in WS1SCBTP WS2SCBTP mode depends greatly on the density and organization of conditional branch instructions in the code 7 3 10 Co...

Page 132: ...s means that the next time the instruction that caused the bus fault is fetched the processor core will get the invalid cached data without any bus fault In order to avoid invalid cached data propagation to the processor core software should man ually invalidate icache by writing 1 to INVCACHE in MSC_CMD at the event of a bus fault In general it is highly recommended to keep the cache enabled all ...

Page 133: ...ritten to the MSC_WDATA register the WDATAREADY bit of the MSC_STATUS register is cleared When this status bit is set software or DMA may write the next word A single word write is commanded by setting the WRITEONCE bit of the MSC_WRITECMD register The operation is complete when the BUSY bit of the MSC_STATUS register is cleared and control of the flash is handed back to the AHB interface allowing...

Page 134: ...8 MSC_IFC R W1 Interrupt Flag Clear Register 0x03C MSC_IEN RW Interrupt Enable Register 0x040 MSC_LOCK RWH Configuration Lock Register 0x044 MSC_CACHECMD W1 Flash Cache Command Register 0x048 MSC_CACHEHITS R Cache Hits Performance Counter 0x04C MSC_CACHEMISSES R Cache Misses Performance Counter 0x054 MSC_MASSLOCK RWH Mass Erase Lock Register 0x05C MSC_STARTUP RW Startup Control 0x074 MSC_CMD W1 Co...

Page 135: ...FC Read Clears IF This bit controls what happens when an IFC register in a module is read Value Description 0 IFC register reads 0 No side effect when reading 1 IFC register reads the same value as IF and the corresponding inter rupt flags are cleared 2 PWRUPONDEMAND 0 RW Power Up on Demand During Wake Up When set during wake up pending AHB transfer will cause MSC to issue power up request to CMU ...

Page 136: ... HFRCO may produce a frequency above 19 MHz before it is calibrated A large wait states is associated with high frequency When changing to a higher frequency this register must be set to a large wait states first before the core clock is switched to the higher frequency When changing to a lower frequency this register should be set to lower wait states after the frequency transition has been compl...

Page 137: ... always write bits to 0 More information in 1 2 Conven tions 7 5 3 MSC_WRITECTRL Write Control Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access RW RW Name IRQERASEABORT WREN Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 ...

Page 138: ...rt write of the first word written to MSC_WDATA then add 4 to ADDR and write the next word if available within a 30us timeout When ADDR is incremented past the page boundary ADDR is set to the base of the page If WDOUBLE is set two words are required every time and ADDR is incremented by 8 3 WRITEONCE 0 W1 Word Write Once Trigger Write the word in MSC_WDATA to ADDR Flash access is returned to the ...

Page 139: ...r is loaded into the internal MSC_ADDR register when the LADDRIM field in MSC_WRITECMD is set 7 5 6 MSC_WDATA Write Data Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name WDATA Bit Name Reset Access Description 31 0 WDATA 0x00000000 RW Write Data The data to be written to the address in MSC_ADDR ...

Page 140: ... this bit is cleared 5 ERASEABORTED 0 R The Current Flash Erase Operation Aborted When set the current erase operation was aborted by interrupt 4 WORDTIMEOUT 0 R Flash Write Word Timeout When this bit is set MSC_WDATA was not written within the timeout The flash write operation timed out and access to the flash is returned to the AHB interface This bit is cleared when the ERASEPAGE WRITETRIG or WR...

Page 141: ...write bits to 0 More information in 1 2 Conven tions 6 WDATAOV 0 R Flash Controller Write Buffer Overflow If one flash controller write buffer overflow detected 5 ICACHERR 0 R ICache RAM Parity Error Flag If one iCache RAM parity Error detected 4 PWRUPF 0 R Flash Power Up Sequence Complete Flag Set after MSC_CMD PWRUP received flash powered up complete and ready for read write 3 CMOF 0 R Cache Mis...

Page 142: ...y with future devices always write bits to 0 More information in 1 2 Conven tions 6 WDATAOV 0 W1 Set WDATAOV Interrupt Flag Write 1 to set the WDATAOV interrupt flag 5 ICACHERR 0 W1 Set ICACHERR Interrupt Flag Write 1 to set the ICACHERR interrupt flag 4 PWRUPF 0 W1 Set PWRUPF Interrupt Flag Write 1 to set the PWRUPF interrupt flag 3 CMOF 0 W1 Set CMOF Interrupt Flag Write 1 to set the CMOF interr...

Page 143: ...flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 4 PWRUPF 0 R W1 Clear PWRUPF Interrupt Flag Write 1 to clear the PWRUPF interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 3 CMOF 0 R W1 Clear CMOF Interrupt Flag Write 1 to clear...

Page 144: ...o ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 6 WDATAOV 0 RW WDATAOV Interrupt Enable Enable disable the WDATAOV interrupt 5 ICACHERR 0 RW ICACHERR Interrupt Enable Enable disable the ICACHERR interrupt 4 PWRUPF 0 RW PWRUPF Interrupt Enable Enable disable the PWRUPF interrupt 3 CMOF 0 RW CMOF Interrupt Enable Enable disable the CMOF interrup...

Page 145: ...CKKEY 0x0000 RWH Configuration Lock Write any other value than the unlock code to lock access to MSC_CTRL MSC_READCTRL MSC_WRITECMD MSC_STARTUP and MSC_AAPUNLOCKCMD Write the unlock code to enable access When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOCKED 0 MSC registers are unlocked LOCKED 1 MSC registers are locked Write Operation LOCK 0...

Page 146: ...ters The performance counters always start counting from 0 0 INVCACHE 0 W1 Invalidate Instruction Cache Use this register to invalidate the instruction cache 7 5 14 MSC_CACHEHITS Cache Hits Performance Counter Offset Bit Position 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000 Access R Name CACHEHITS Bit Name Reset Access Description 31 20 ...

Page 147: ...SES Bit Name Reset Access Description 31 20 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 19 0 CACHEMISSES 0x00000 R Cache Misses Since Last Performance Counter Start Command Use to measure cache performance for a particular code section Reference Manual MSC Memory System Controller silabs com Building a more connected world Rev 1 ...

Page 148: ...2 Conven tions 15 0 LOCKKEY 0x0001 RWH Mass Erase Lock Write any other value than the unlock code to lock access the the ERASEMAINn commands Write the unlock code 631A to enable access When reading the register bit 0 is set when the lock is enabled Locked by default Mode Value Description Read Operation UNLOCKED 0 Mass erase unlocked LOCKED 1 Mass erase locked Write Operation LOCK 0 Lock mass eras...

Page 149: ...the optional STDLY1 timeout 24 ASTWAIT 1 RW Active Startup Wait Active wait for flash startup startup after SDLY0 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 12 STDLY1 0x001 RW Startup Delay 0 Number of cycles with startup waitstates and also the maximum number of cycles startup sampling will be attempted be fore startin...

Page 150: ...er Offset Bit Position 0x090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access RW RW Name BLWDIS BLRDIS Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 BLWDIS 0 RW Flash Bootloader Write Erase Disable Controls write erase access of the flash...

Page 151: ...atibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 UNLOCKAAP 0 W1 Software Unlock AAP Command Write to this bit to unlock AAP This is only possible when bit 31 of the AAP Lock Word ALW in flash is set to 1 If bit 31 of the ALW has been cleared to 0 this command has no effect Register is writable only when MSC_LOCK is unlocked Reference Manual MSC Memory Sys...

Page 152: ...ADVANCED Advanced buffering mode where the cache uses the fetch pattern to predict highly accessed data and store it in low energy memory 3 MINACTIVITY Minimum activity mode which allows the cache to minimize activity in logic that it predicts has a low probability being used This mode can introduce wait states into the instruction fetch stream when the cache exits one of its low activity states T...

Page 153: ...tiple highly configura ble prioritized DMA channels A linked list of flexible descriptors makes it possible to tailor the controller to the specific needs of an application 8 1 Introduction The Linked Direct Memory Access LDMA controller performs memory transfer operations independently of the CPU This has the benefit of reducing the energy consumption and the workload of the CPU and enables the s...

Page 154: ...iptors Circular and ping pong buffers Scatter Gather Looping Pause and restart triggered by other channels Sophisticated flow control which can function without CPU interaction Channel arbitration includes Fixed priority Simple round robin Round robin with programmable multiple interleaved entries for higher priority requesters Programmable data size and source and destination address strides Prog...

Page 155: ...inked DMA Controller consists of three main parts A DMA core that executes transfers and communicates status to the core A channel select block that routes peripheral DMA requests and acknowledge signals to the DMA A set of internal channel configuration registers for tracking the progress of each DMA channel The DMA has access to all system memory through the AHB bus and the AHB APB bridge It can...

Page 156: ...nally be signaled to the CPU s interrupt controller at the end of any DMA trans fer or at the completion of a descriptor if the DONEIFSEN bit is set An AHB error will always generate an interrupt 8 3 1 Channel Descriptor Each DMA channel has descriptor registers A transfer can be initialized by software writing to the registers or by the DMA itself copying a descriptor from RAM to memory When usin...

Page 157: ...oading a linked descriptor the descriptor registers will reflect the content of the loaded descriptor Note that the linked descriptor must be word aligned in memory The two least significant bits of the LDMA_CHx_LINK register are used by the LINK and LINKMODE bits The two least significant bits of the link address are always zero 8 3 1 7 Addressing Modes The DMA descriptors support absolute addres...

Page 158: ... are not byte swapped B3 B2 B1 B0 B3b7 B3b0 B2b7 B2b0 B1b7 B1b0 B0b7 B0b0 B3 B2 B1 B0 B3b7 B3b0 B2b7 B2b0 B1b7 B1b0 B0b7 B0b0 BYTESWAP 1 SIZE WORD B1 B0 B3b7 B3b0 B2b7 B2b0 B1b7 B1b0 B0b7 B0b0 B1 B0 B3b7 B3b0 B2b7 B2b0 B1b7 B1b0 B0b7 B0b0 BYTESWAP 1 SIZE HALF Figure 8 2 Word and Half Word Endian Byte Swap Examples Reference Manual LDMA Linked DMA Controller silabs com Building a more connected wor...

Page 159: ...0 yB3 yB2 yB1 yB0 zB3 zB2 zB1 zB0 wB3 wB2 wB1 wB0 lB3 lB2 lB1 lB0 mB3 mB2 mB1 mB0 nB3 nB2 nB1 nB0 oB3 oB2 oB1 oB0 pB3 pB2 pB1 pB0 qB3 qB2 qB1 qB0 rB3 rB2 rB1 rB0 sB3 sB2 sB1 sB0 tB3 tB2 tB1 tB0 uB3 uB2 uB1 uB0 vB3 vB2 vB1 vB0 kB3 kB2 kB1 kB0 lB3 lB2 lB1 lB0 mB3 mB2 mB1 mB0 kB3 kB2 kB1 kB0 lB3 lB2 lB1 lB0 mB3 mB2 mB1 mB0 nB3 nB2 nB1 nB0 Next read data oB3 opB2 oB1 oB0 Next write data nB3 nB2 nB1 nB...

Page 160: ...B3 yB2 yB1 yB0 zB3 zB2 zB1 zB0 wB3 wB2 wB1 wB0 lB3 lB2 lB1 lB0 mB3 mB2 mB1 mB0 nB3 nB2 nB1 nB0 oB3 oB2 oB1 oB0 pB3 pB2 pB1 pB0 qB3 qB2 qB1 qB0 rB3 rB2 rB1 rB0 sB3 sB2 sB1 sB0 tB3 tB2 tB1 tB0 uB3 uB2 uB1 uB0 vB3 vB2 vB1 vB0 lB1 lB0 kB1 kB0 nB1 nB0 mB1 mB0 pB1 pB0 oB1 oB0 rB1 rB0 qB1 qB0 kB1 kB0 lB1 lB0 mB1 mB0 nB1 nB0 0x200 0x400 source destination Memory DMA Controller FIFO kB3 kB2 kB1 kB0 First r...

Page 161: ...iptors To repeat a single descriptor the LINK address of the descriptor should point to itself After LOOPCNT reaches zero if the LINK bit in the descriptor LINK word is clear the transfer stops If the LINK bit is set the LDMA will load the next sequential descriptor located immediately following the looping descriptor The behavior of the LINK bit is different for a looping descriptor This is neces...

Page 162: ...rity channel with an active request is granted the transfer This mode guarantees smallest latency for the highest priority requesters It is best suited for systems where peak bandwidth is well below LDMA controller s maximum ability to serve The drawback of this mode is the possibility of starvation for lowest priority requesters In the round robin priority mode each active requesting channel is s...

Page 163: ...OTS ONE CHNL2_CFG ARBSLOTS ONE If all channels are constantly requesting transfers then the arbitration order is CHNL0 CHNL1 CHNL0 CHNL2 CHNL0 CHNL1 CHNL0 CHNL2 CHNL0 etc Note there are no channels assigned to arbitration slot four or eight in this example so those slots are skipped and the final sequence is ARBSLOT2 ARBSLOT1 ARBSLOT2 ARBSLOT1 etc Channel 1 and Channel 2 are selected in round robi...

Page 164: ...x 1 1 x 2 2 x 3 3 x 4 4 x 6 5 x 8 6 x 12 7 x 16 8 x 24 9 x 32 10 x 64 11 x 128 12 x 256 13 x 512 14 x 1024 15 x lock Note Software must take care not to assign a low priority channel with a large BLOCKSIZE because this prevents the controller from servic ing high priority requests until it re arbitrates The number of DMA transfers that need to be done is specified by the user in XFERCNT When XFERC...

Page 165: ...R Descriptor Structure This descriptor defines a typical data transfer which may be a Normal Link or Loop transfer Only this structure type can be written directly into LDMA s registers by the CPU All descriptors may be linked to Refer to the register descriptions for additional information For specifying XFER structure type set STRUCTTYPE to 0 See the peripheral register descriptions for informat...

Page 166: ...LR SYNCSET DST MATCHEN MATCHVAL LINK LINKADDR LINK LINKMODE Bit Name Description 1 0 STRUCTTYPE Descriptor Type This field indicates which type of descriptor this is It must be 1 for a SYNC descriptor 20 DONEIFSEN Done if Set indicator If set the interrupt flag will be set when descriptor completes 15 8 SYNCCLR Sync Trigger Clear This bit field is used to clear corresponding bits within the SYNCTR...

Page 167: ...This field indicates which type of descriptor this is It must be 2 for a WRI descriptor 20 DONEIFSEN Done if Set indicator If set the interrupt flag will be set when descriptor completes 31 0 IMMVAL Immediate Value for Write This bit field specifies the immediate data value that is to be written to the address pointed to by DSTADDR Only one write occurs for WRI structures 31 0 DSTADDR Address to w...

Page 168: ... linking Software writes directly to the LDMA channel registers This example does not use a memory based descriptor list This example is suitable for most simple transfers that are limited to transferring one block of data It supports anything that can be done using a single descriptor This includes endian conversion and packing unpacking data Channel 0 is used for this example The LDMA will be us...

Page 169: ...data as soon as they are loaded Write 0x00000013 to the LINK member of all but the last descriptor LINKMODE 1 relative addressing LINK 1 Link to the next descriptor LINKADDR 0x00000010 size of descriptor Set the DONEIFSEN bit in the CTRL member of the 2nd structure so that the interrupt flag will be set when it completes Write 0x00000000 to the LINK member of the last descriptor LINK 0 Do not link...

Page 170: ...select none for memory to memory Clear and enable interrupts as desired Set bit 0 in the LDMA_LINKLOAD register to initiate loading and execution of the first descriptor Alternativley software can manually copy the first descriptor contents to the LDMA_CH0_CTRL LDMA_CH0_SRC LDMA_CH0_DST and LDMA_CH0_LINK registers and then enable the channel in the LDMA_CHEN register Reference Manual LDMA Linked D...

Page 171: ...AP 0 no swap XFERCNT 4 4 words STRUCTTPYE 0 TRANSFER IGNORESREQ 1 ignore single requests Write the address ADC0_SINGLEDATA register to the SRC member Write 0x1000 address to DST member Configure the LINKLink member LINK 0 stop after loop MODE 1 relative link address LINKADDR 0 point to ourself Configure the Channel Write the desired number of repeats to the LDMA_CH0_LOOP register SOURCESEL in LDMA...

Page 172: ...on of looping Once the LOOPCNT rea ches zero the LDMA will load descriptor C Descriptor C must be located immediately following descriptor B Ctrl Src Dst Link A B Ctrl Src Dst Link Memory 0x00 0x10 link_addr B link_addr NA C Ctrl Src Dst Link 0x20 link_addr A Alternate link A B LINKADDR A DECLOOPCNT 1 C LINK 0 LINKADDR B Figure 8 7 Descriptor List With Looping Initialization is similar to the sing...

Page 173: ...IG 7 to be set by a sync set clear structure which is controlled by channel 1 Sync structures do not transfer data they can only set clear or wait to match the SYNCTRIG 7 0 bits Note that sync structures cannot decrement loop counter LDMA_SYNC SYNCTRIG 0x0 at time 0 LDMA_CH0 Structure A 0x00 Structure B 0x10 Structure C 0x20 CTRL CTRL CTRL STRUCTTYPE XFER STRUCTTYPE SYNC STRUCTTYPE XFER LINK LINK ...

Page 174: ... Example Both A and Y effectively start at the same time A finishes earlier then it links to B which waits for the SYNCTRIG 7 bit to be set before loading C Y finishes after B is loaded and it links to sync structure Z which sets the SYNCTRIG 7 bit Channel 0 responds to the trigger set by loading C for the final data transfer Reference Manual LDMA Linked DMA Controller silabs com Building a more c...

Page 175: ... should point to the desired target ad dresses The first descriptor will copy only the first row The XFERCNT of the first descriptor is set to the desired width minus one CTRL XFERCNT WIDTH 1 SRCMD 0 absolute DSTMD 0 absolute SRCADDR target source address DSTADDR target destination address LINK 0x00000013 LINK 1 LINKMD 1 LINKADDR 0x00000010 point to next descriptor The second descriptor will use r...

Page 176: ...ransfer This same method is easily extended to copy multiple rectangles by linking descriptors together To initialize the LDMA_CHx_LOOP register precede each descriptor pair described above with a write immediate descriptor which writes the desired value to the LOOPCNT field of the LDMA_CHx_LOOP register Reference Manual LDMA Linked DMA Controller silabs com Building a more connected world Rev 1 1...

Page 177: ...tware will then process the data in the first buffer while the LDMA is transferring data to the second buffer For a receiver ping pong buffer each descriptor should link to the other descriptor The link bit should be set to provide infinite ping pong between the two buffers The DONIFS bit in each descriptor should be set to generate an interrupt on the completion of each descriptor Descriptor A CT...

Page 178: ...LINK 0 link to previous descriptor LINKMD 1 relative addressing 8 4 8 Scatter Gather Scatter Gather in general refers to a process that copies data from multiple locations scattered in memory and gathers the data to a single location in memory or vice versa A simple descriptor list allows data gathering For example data from a discontiguous list of buffers might be copied to a contiguous sequentia...

Page 179: ...elect Register 0x084 LDMA_CH0_CFG RW Channel Configuration Register 0x088 LDMA_CH0_LOOP RWH Channel Loop Counter Register 0x08C LDMA_CH0_CTRL RWH Channel Descriptor Control Word Register 0x090 LDMA_CH0_SRC RWH Channel Descriptor Source Data Address Register 0x094 LDMA_CH0_DST RWH Channel Descriptor Destination Data Address Register 0x098 LDMA_CH0_LINK RWH Channel Descriptor Link Structure Address ...

Page 180: ...tion channels Channels CH0 though CH n 1 are fixed and channels CH n through CH7 are round robin where n is the field value The reset value will give all fixed channels 23 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 8 SYNCPRSCLREN 0x00 RW Synchronization PRS Clear Enable Setting a bit in this field will enable the correspon...

Page 181: ... of entries in the FIFO 15 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 10 8 CHERROR 0x0 R Errant Channel Number When the ERROR flag is set in the LDMA_IF register the CHERROR field will indicate the most recent channel to have a transfer error 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More...

Page 182: ...ailed in 4 2 3 Peripheral Bit Set and Clear 8 6 4 LDMA_CHEN DMA Channel Enable Register Single Cycle RMW Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RWH Name CHEN Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions...

Page 183: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RWH Name CHDONE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0 CHDONE 0x00 RWH DMA Channel Linking or Done Each DMA channel sets the corresponding bit in this register when the entire transfer...

Page 184: ...g and the CPU is halted This may be useful for debugging DMA software 8 6 8 LDMA_SWREQ DMA Channel Software Transfer Request Register Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access W1 Name SWREQ Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More in...

Page 185: ...ponding channel When cleared any pending periph eral requests will be serviced 8 6 10 LDMA_REQPEND DMA Channel Requests Pending Register Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access R Name REQPEND Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 Mor...

Page 186: ...d enable the channel This empowers software to step through a sequence of descriptors 8 6 12 LDMA_REQCLEAR DMA Channel Request Clear Register Offset Bit Position 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access W1 Name REQCLEAR Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits t...

Page 187: ...R DMA Structure Operation Done Interrupt Flag When a channel completes a transfer or sync operation the corresponding DONE bit is set in the LDMA_IF register 8 6 14 LDMA_IFS Interrupt Flag Set Register Offset Bit Position 0x064 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x00 Access W1 W1 Name ERROR DONE Bit Name Reset Access Description 31 ERROR 0...

Page 188: ...1 Clear DONE Interrupt Flag Write 1 to clear the DONE interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 8 6 16 LDMA_IEN Interrupt Enable Register Offset Bit Position 0x06C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x00 Access RW RW Name ERROR DONE Bit Name ...

Page 189: ...ter 0 0b001100 USART0 Universal Synchronous Asynchronous Receiver Transmitter 0 0b001101 USART1 Universal Synchronous Asynchronous Receiver Transmitter 1 0b010000 LEUART0 Low Energy UART 0 0b010100 I2C0 I2C 0 0b011000 TIMER0 Timer 0 0b011001 TIMER1 Timer 1 0b011010 WTIMER0 Wide Timer 0 0b110000 MSC Memory System Controller 0b110001 CRYPTO0 Advanced Encryption Standard Accelerator 0 0b110011 LESENS...

Page 190: ...PTY 0b0011 USART1RXDATAV RIGHT USART1RXDATAVRIGHT REQ SREQ 0b0100 USART1TXBLRIGHT USART1TXBLRIGHT REQ SREQ SOURCESEL 0b010000 LEUART0 0b0000 LEUART0RXDATAV LEUART0RXDATAV 0b0001 LEUART0TXBL LEUART0TXBL 0b0010 LEUART0TXEMPTY LEUART0TXEMPTY SOURCESEL 0b010100 I2C0 0b0000 I2C0RXDATAV I2C0RXDATAV REQ SREQ 0b0001 I2C0TXBL I2C0TXBL REQ SREQ SOURCESEL 0b011000 TIMER0 0b0000 TIMER0UFOF TIMER0UFOF 0b0001 T...

Page 191: ...CWDATA MSCWDATA REQ SREQ SOURCESEL 0b110001 CRYPTO0 0b0000 CRYPTO0DATA0WR CRYPTO0DATA0WR 0b0001 CRYPTO0DATA0XWR CRYPTO0DATA0XWR 0b0010 CRYPTO0DATA0RD CRYPTO0DATA0RD 0b0011 CRYPTO0DATA1WR CRYPTO0DATA1WR 0b0100 CRYPTO0DATA1RD CRYPTO0DATA1RD SOURCESEL 0b110011 LESENSE 0b0000 LESENSEBUFDATAV LESENSEBUFDATAV REQ SREQ Reference Manual LDMA Linked DMA Controller silabs com Building a more connected world...

Page 192: ... Sign Value Mode Description 0 POSITIVE Increment source address 1 NEGATIVE Decrement source address 19 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 17 16 ARBSLOTS 0x0 RW Arbitration Slot Number Select For channels using round robin arbitration this bit field is used to select the number of slots in the round robin queue Value ...

Page 193: ...tion 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0 LOOPCNT 0x00 RWH Linked Structure Sequence Loop Counter This bit field specifies the number of iterations when using looping descriptors Software should write to LOOPCNT before using a looping descriptor Reference Manual LDMA Linked DMA Controller silabs com Building a mor...

Page 194: ...ecifies the source addressing mode of linked descriptors After loading a linked descriptor reading this field will indicate the source addressing mode of the linked descriptor Note that the first descriptor always uses absolute addressing mode Value Mode Description 0 ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute ad dress of the source data 1 RELATIVE The SRCADDR field of LDMA_C...

Page 195: ...gnore single requests SREQ and only respond to multiple requests REQ when this bit is set 22 DECLOOPCNT 0 RWH Decrement Loop Count When using looping setting this bit will decrement the LOOPCNT field in the LDMA_CHx_LOOP register after each de scriptor execution 21 REQMODE 0 RWH DMA Request Transfer Mode Select Value Mode Description 0 BLOCK The LDMA transfers one BLOCKSIZE per transfer request 1 ...

Page 196: ...4 4 XFERCNT 0x000 RWH DMA Unit Data Transfer Count Specifies number of unit data words half words or bytes to transfer as determined by the SIZE field The value written should be one less than the desired transfer count 3 STRUCTREQ 0 W1 Structure DMA Transfer Request When a linked descriptor is loaded with this bit set it will immediately trigger a transfer 2 Reserved To ensure compatibility with ...

Page 197: ... or decremented with each source read 8 6 22 LDMA_CHx_DST Channel Descriptor Destination Data Address Register Offset Bit Position 0x094 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RWH Name DSTADDR Bit Name Reset Access Description 31 0 DSTADDR 0x00000000 RWH Destination Data Address Writing to this register sets the destination add...

Page 198: ... completing the initial transfer if this bit is set the DMA will load the next linked descriptor If the next linked descriptor also has this bit set the DMA will load the next linked descriptor 0 LINKMODE 0 R Link Structure Addressing Mode This field specifies the addressing mode of linked descriptors After loading a linked descriptor reading this field will indi cate the addressing mode of the lo...

Page 199: ...w power consumption The cause of the re set may be read from a register thus providing soft ware with information about the cause of the reset 9 1 Introduction The RMU is responsible for handling the reset functionality of the EFR32 9 2 Features Reset sources Power on Reset POR Brown out Detection BOD on the following power domains Analog Unregulated Power Domain AVDD Digital Unregulated Power Dom...

Page 200: ...BODn AVDD EM4H EM4S Wakeup Resetn DVDD PORSTn POR DEC BOD BOD BOD DECBODn EXRST FULLRESETn EM4 Pin Wakeup cause Enable Full Reset Enable Extended Reset Enable Limited Reset CRYOTIMER RFSENSE LFOSC Ctrl RTCC VMON EXTENDEDRESETn SYSREQRST WDOGRST LOCKUPRST EXTRST SYSREQRST WDOGRST LOCKUPRST EXTRST LIMITEDRESETn DEBUGRESETn RMU_RSTCAUSE EM4S only SYSEXTENDEDRESETn CACHE SYSNORETRESETn EM4H EM4S Wakeu...

Page 201: ...tion of CRYOTIMER RFSENSE DE BUGGER and parts of CMU RMU and EMU FULL Everything reset with exception of some registers in RMU and EMU The reset sources resulting in a soft reset are Watchdog reset Lockup reset System reset request Pin reset1 1 Pin reset can be configured to be either a soft or a hard reset see 9 3 5 RESETn Pin Reset for details Note LIMITED and EXTENDED resets are synchronized to...

Page 202: ...ause bit is invalidated i e can not be trusted if one of the bits to the right of it does not match the table X bits are don t care Note Notice that it is possible to have multiple reset causes For example an external reset and a watchdog reset may happen simultaneous ly Table 9 2 RMU Reset Cause Register Interpretation RMU_RSTCAUSE Reset cause EM4RST WDOGRST SYSREQRST LOCKUPRST EXTRST DECBOD DVDD...

Page 203: ...UPLE and one for the Analog Power Domain AVDD The BODs are constantly monitoring these supply voltages Whenever the unregulated or regulated power drops below the VBODthr value see the Electrical Characteristics section of the data sheet for details or if AVDD drops below the voltage at the DECOUPLE pin the corresponding active low BROWNOUTn line is held low The BODs also include hysteresis which ...

Page 204: ... unrecoverable exception following the activation of the processor s built in system state protection hardware For more information about the Cortex M4 lockup conditions see the ARMv7 M Architecture Reference Manual The Lockup reset does not reset the Debug Interface unless configured as a FULL reset The Lockup reset can be configured to cause different levels of reset as determined by the LOCKUPR...

Page 205: ...C0 Alternate Reset for Registers in EMU EMU Reset Levels POR BOD and hard pin reset EMU_BIASCONF_LSBIAS_SEL POR BOD and hard pin reset EMU_DCDCLNVCTRL POR and hard pin reset EMU_CTRL_EM2BODDIS POR BOD and hard pin reset EMU_PWRCTRL EMU_DCDCCTRL EMU_DCDCMISCCTRL EMU_DCDCZDETCTRL EMU_DCDCCLIMCTRL EMU_DCDCLNCOMPCTRL EMU_DCDCLPVCTRL EMU_DCDCLPCTRL EMU_DCDCLNFREQCTRL EMU_DCDCLPEM01CFG EXTENDED reset EM...

Page 206: ...escription 0x000 RMU_CTRL RW Control Register 0x004 RMU_RSTCAUSE R Reset Cause Register 0x008 RMU_CMD W1 Command Register 0x00C RMU_RST RW Reset Control Register 0x010 RMU_LOCK RWH Configuration Lock Register Reference Manual RMU Reset Management Unit silabs com Building a more connected world Rev 1 1 206 ...

Page 207: ...equest These settings only apply when PINRESETSOFT in CLW0 in the Lock bit page is set Value Mode Description 0 DISABLED Reset request is blocked 1 LIMITED The CRYOTIMER DEBUGGER RTCC are not reset 2 EXTENDED The CRYOTIMER DEBUGGER are not reset RTCC is reset 4 FULL The entire device is reset except some EMU and RMU registers 11 Reserved To ensure compatibility with future devices always write bit...

Page 208: ...To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 0 WDOGRMODE 0x4 RW WDOG Reset Mode Controls the reset level for WDOG reset request Value Mode Description 0 DISABLED Reset request is blocked This disable bit is redundant with enable disable bit in WDOG 1 LIMITED The CRYOTIMER DEBUGGER RTCC are not reset 2 EXTENDED The CRYOTIMER DEBUGGER are ...

Page 209: ...d Must be cleared by software See Table 9 2 RMU Reset Cause Register Inter pretation on page 202 for details on how to interpret this bit 8 EXTRST 0 R External Pin Reset Set if an external pin reset has been performed Must be cleared by software See Table 9 2 RMU Reset Cause Register Interpretation on page 202 for details on how to interpret this bit 7 5 Reserved To ensure compatibility with futur...

Page 210: ...Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 RCCLR 0 W1 Reset Cause Clear Set this bit to clear the RSTCAUSE register 9 5 4 RMU_RST Reset Control Register Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset Access Name Bit Name Reset Access...

Page 211: ...1 2 Conven tions 15 0 LOCKKEY 0x0000 RWH Configuration Lock Key Write any other value than the unlock code to lock RMU_CTRL and RMU_RST from editing Write the unlock code to un lock When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOCKED 0 RMU registers are unlocked LOCKED 1 RMU registers are locked Write Operation LOCK 0 Lock RMU registers UN...

Page 212: ...mize energy consumption during program execution 10 1 Introduction The Energy Management Unit EMU manages all the low energy modes EM in EFR32 Each energy mode manages whether the CPU and the various peripherals are available The energy modes range from EM0 Active to EM4 Shutoff EM0 Active mode provides the highest amount of features enabling the CPU Radio and peripherals with the highest clock fr...

Page 213: ...ion settings Power routing configurations DCDC control Internal power switches allowing for extensible system power architecture Temperature measurement control and status Brown Out Detection Voltage Monitoring Four dedicated continuous monitor channels Optional monitor features include interrupt generation and low power mode wake up State Retention Voltage Scaling EM01 voltage scaling EM23 voltag...

Page 214: ...s PRS The combined state of these modules defines the required energy mode Figure 10 1 EMU Overview The EMU is available on the peripheral bus The energy management state machine controls the internal voltage regulators oscillators memories and interrupt system Events interrupts and resets can trigger the energy management state machine to return to the active state This is further described in th...

Page 215: ...nd LEUART have the ability to temporarily wake up the part from either EM2 Deep Sleep or EM3 Stop to EM1 Sleep in order to transfer data Once completed the part is automatically placed back into the EM2 Deep Sleep or EM3 Stop mode The Core can always request to go to EM1 Sleep with the WFI or WFE command during EM0 Active The core will be prevented from entering EM2 Deep Sleep or EM3 Stop if the R...

Page 216: ...lable Available6 Available6 TIMER Timer Counter Available LETIMER Low Energy Timer Available Available Available7 CRYOTIMER Ultra Low Energy Timer Counter Available Available Available7 Available Available WDOG Watchdog Available Available Available7 PCNT Pulse Counter Available Available Available ACMP Analog Comparator Available Available8 Available8 ADC Analog to Digital Converter Available Ava...

Page 217: ...DC which are not supported in EM2 3 e g AUXHFRCO will be automatically enabled to allow the ADC to convert a sample and then automatically disabled afterwards 6 I2C functionality limited to receive address recognition 7 Must be using ULFRCO 8 ACMP functionality in EM2 3 limited to edge interrupt 9 Pin wake up in EM4 supported only on GPIO_EM4WUx pins Consult data sheet for complete list of pins 10...

Page 218: ...4 EM3 Stop In this low energy mode all low frequency oscillators LFXO LFRCO and all low frequency clocks derived from them are stopped as well as all high frequency clocks Most peripherals are disabled or have reduced functionality Memory and registers retain their values Cortex M4 is in sleep mode Clocks to the core are off RFSENSE available Radio inactive High frequency clock tree is inactive Al...

Page 219: ...pending on EMU EM4CTRL EM4IORETMODE configuration The DC DC converter configuration is reset to its default Unconfigured configuration DC DC converter disabled and bypass switch is off 10 3 2 Entering Low Energy Modes The following sections describe the requirements for entering the various energy modes Note If Voltage scaling is being used to save system energy it is important to ensure the prope...

Page 220: ... SLEEPONEXIT bit in the Cortex M4 System Control Register is set Refer to ARM documentation on entering Sleep modes Alternately EM2 Deep Sleep or EM3 Stop is entered from EM1 Sleep upon the completion of a Peripheral Wake Up Request from the RAC if no EM0 Active wake up happens in the meantime 10 3 2 3 Entry Into EM4 Hibernate or EM4 Shutoff Energy mode EM4 Hibernate and EM4 Shutoff is entered thr...

Page 221: ... 3 EMU Wake Up Triggers from Low Energy Modes Peripheral Wake Up Trigger EM2 Deep Sleep EM3 Stop EM4 Hiber nate EM4 Shut off LEUART Low Energy UART Receive transmit Yes LETIMER Any enabled interrupt Yes WDOG Any enabled interrupt Yes Yes LESENSE Any enabled interrupt Yes LFXO Ready Interrupt Yes LFRCO Ready Interrupt Yes I2C Receive address recognition Yes Yes ACMP Any enabled edge interrupt Yes Y...

Page 222: ...The EFR32 has multiple internal power domains IO Supply IOVDD Analog Flash AVDD RF Analog Supply RFVDD RF Power Amplifier Supply PAVDD Input to Digital LDO DVDD and Low Voltage Digital Supply DECOUPLE Additional detail for each con figuration and option is given in the following sections When assigning supply sources the following requirement must be adhered to VREGVDD AVDD Must be the highest vol...

Page 223: ...wer the digital LDO from DVDD The analog blocks are powered from the AVDD supply pin i e ANASW 0 in EMU_PWRCTRL After power on firmware can configure the device to based on the external hardware configuration Note that the PWRCFG register can only be written once to a valid value and is then locked This should be done immediately out of boot to select the proper power config uration The DC DC and ...

Page 224: ...main supply as well RFVDD and PAVDD which power the radio are shorted to the main supply as well VREGSW must be left disconnected in this configuration DECOUPLE DVDD AVDD VREGSW Main Supply VREGVSS IOVDD VREGVDD VDD DC DC DC DC Driver Bypass Switch OFF FLASH DECOUPLE DVDD AVDD VREGSW VREGVSS IOVDD VREGVDD ANASW 0 1 REGPWRSEL 0 1 Analog Blocks Digital Logic Digital LDO PAVDD RFVDD RF Analog RF Powe...

Page 225: ...EGVDD VDD DC DC DC DC Driver Bypass Switch OFF FLASH DECOUPLE DVDD AVDD VREGSW VREGVSS IOVDD VREGVDD ANASW 0 1 REGPWRSEL 0 1 Digital Logic PAVDD RFVDD RF Analog VDCDC Analog Blocks Digital LDO RF Power Amplifier Figure 10 4 DC DC Standard Power Configuration As the Main Supply voltage approaches the DC DC output voltage it eventually reaches a point where becomes inefficient or impossi ble for the...

Page 226: ...kes the VREGVDD input voltage and converts it down to an output voltage between VREGVDD and 1 8 V with a peak efficien cy of approximately 90 in Low Noise LN mode and 85 in Low Power LP mode Refer to the data sheet for full DC DC specifica tions The DC DC converter operates in either Low Noise LN or Low Power LP mode LN mode is intended for higher current operation e g 10 mA whereas LP mode is int...

Page 227: ... voltage is at the programmed upper level the powertrain PFET is turned off The output ripple voltage may be quite large 100 mV in LP mode The LP controller supports load currents up to approximately 10 mA making it suitable for light loads in EM0 and EM1 as well as EM2 EM3 or EM4 low energy modes 10 3 5 3 Low Noise LN Mode The Low Noise LN controller continuously switches the powertrain NFET and ...

Page 228: ... Peripheral Power Selection The analog peripherals e g ULFRCO LFRCO LFXO HFRCO AUXHFRCO VMON IDAC ADC are powered from an internal ana log supply domain VDDX_ANA VDDX_ANA may be supplied from either the AVDD or DVDD supply pins depending on the configura tion of the ANASW bit in the EMU_PWRCTRL register Changes to the ANASW setting should be made immediately out of reset i e in the Unconfigured Co...

Page 229: ...or example if IOVDD VDCDC 1 It isn t directly possible to program an unprogrammed device on a PCB through the serial wire interface Programming the device requires IOVDD to be present i e for SWCLK SWDIO etc and IOVDD won t be present until after the part is programmed i e the DC DC is enabled in firmware to power up VDCDC It is possible to work around this issue however by providing an external s...

Page 230: ...ardware begins the process of volt age scaling and when done the VSCALEDONE interrupt is triggered Users can also poll VSCALEBUSY in EMU_STATUS which indi cates that hardware is busy changing the voltage scale setting when set VSCALE in EMU_STATUS shows the current voltage the sys tem is in at any time Note If more than one voltage scaling command is issued in EMU_CMD simultaneously the lower volt...

Page 231: ...try with EM23VSCALE 10 3 9 3 EM4H Voltage Scaling EM4HVSCALE bitfield in EMU_CTRL allows user to independently setup the voltage scaling levels for EM4H energy mode The EM4HVSCALE in EMU_CTRL should be programmed to a level which is smaller than or equal to VSCALE level in EMU_STATUS or EM23VSCALE in EMU_CTRL This means that EM4H voltage scaling is always a voltage scaling down process If EM4HVSCA...

Page 232: ...n by the system and subsequently locked out from register access Locking out peripherals prevents users from accidentally using peripherals with con figurations at their reset state EMU_EM23PERNORETAINCMD allows user to unlock these peripherals and hence grant access to their registers for updating their configurations 10 3 11 Brown Out Detector BOD 10 3 11 1 AVDD BOD The EFR32 has a fast response...

Page 233: ...i e 1 62 V to 3 4 V Using the values given in VMONCAL registers one can calculate T1 86 T2 98 Va and Vb T1 86 10 x VMONCALX_XVDD1V86THRESCOARSE VMONCALX_XVDD1V86THRESFINE T2 98 10 x VMONCALX_XVDD2V98THRESCOARSE VMONCALX_XVDD2V98THRESFINE Va 1 12 T2 98 T1 86 Vb 1 86 Va x T1 86 Figure 10 6 VMON Calibration Equations Now if it is required to find the coarse and fine thresholds for a certain voltage Y...

Page 234: ...h the corresponding calibra tion temperature and reading stored off in the DI page as follows DEVINFO CAL TEMP This bitfield contains the temperature in degrees C at calibration DEVINFO EMUTEMP This register contains the EMU TEMP reading at the calibration temperature stored in DEVINFO CAL TEMP The current calibrated EMU temperature sensor result from EMU TEMP may be converted to degrees C using t...

Page 235: ...rgy modes and power transitions and will consequently need to be reset with a different condition The following reset conditions will apply to the appropriate set of registers as marked in the Register Description table Reset with POR or Hard Pin Reset Reset with POR Hard Pin Reset or any BOD reset Reset with SYSEXTENDEDRESETn Reset with FULLRESETn default If a register field is not marked with a ...

Page 236: ...ent Limiter Control Register 0x058 EMU_DCDCLNCOMPCTRL RW DCDC Low Noise Compensator Control Register 0x05C EMU_DCDCLNVCTRL RWH DCDC Low Noise Voltage Register 0x064 EMU_DCDCLPVCTRL RW DCDC Low Power Voltage Register 0x06C EMU_DCDCLPCTRL RW DCDC Low Power Control Register 0x070 EMU_DCDCLNFREQCTRL RW DCDC Low Noise Controller Frequency Control 0x078 EMU_DCDCSYNC R DCDC Read Status Register 0x090 EMU...

Page 237: ... Type Description 0x108 EMU_EM23PERNORETAINCTRL RW When Set Corresponding Peripherals May Get Powered Down in EM23 Reference Manual EMU Energy Management Unit silabs com Building a more connected world Rev 1 1 237 ...

Page 238: ...ty with future devices always write bits to 0 More information in 1 2 Conven tions 9 8 EM23VSCALE 0x0 RW EM23 Voltage Scale Set EM23 voltage Entry to EM2 3 will trigger voltage scaling to this voltage if voltage scale level in EM23VSCALE is lesser than that of VSCALE Value Mode Description 0 VSCALE2 Voltage Scale Level 2 2 VSCALE0 Voltage Scale Level 0 3 RESV RESV 7 5 Reserved To ensure compatibil...

Page 239: ...able BODs to minimize current in EM2 Reset with POR or Hard Pin Reset 1 EM2BLOCK 0 RW Energy Mode 2 Block This bit is used to prevent the MCU from entering Energy Mode 2 or 3 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions Reference Manual EMU Energy Management Unit silabs com Building a more connected world Rev 1 1 239 ...

Page 240: ...re information in 1 2 Conven tions 20 EM4IORET 0 R IO Retention Status The status of IO retention Will be set upon EM4 entry based on EM4IORETMODE in EMU_EM4CTRL Cleared by setting EM4UNLATCH in EMU_CMD and can also be cleared in EM4H by the VMON Value Mode Description 0 DISABLED IO retention is disabled 1 ENABLED IO retention is enbled 19 Reserved To ensure compatibility with future devices alway...

Page 241: ...icates the status of the IOVDD0 channel of the VMON 3 VMONDVDD 0 R VMON DVDD Channel Indicates the status of the DVDD channel of the VMON 2 VMONALTAVDD 0 R Alternate VMON AVDD Channel Indicates the status of the Alternate AVDD channel of the VMON 1 VMONAVDD 0 R VMON AVDD Channel Indicates the status of the AVDD channel of the VMON 0 VMONRDY 0 R VMON Ready VMON status When high this bit indicates t...

Page 242: ...rs from editing Write the unlock code to unlock When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOCKED 0 EMU registers are unlocked LOCKED 1 EMU registers are locked Write Operation LOCK 0 Lock EMU registers UNLOCK 0xADE8 Unlock EMU registers 10 5 4 EMU_RAM0CTRL Memory Control Register Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 2...

Page 243: ...1VSCALE0 0 W1 EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 Start EM01 voltage scaling to Voltage Scale Level 0 Write to this register will trigger voltage scaling to Voltage Scale Level 0 followed by an VSCALEDONE interrupt 3 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 EM4UNLATCH 0 W1 EM4 Unlatch When entering...

Page 244: ...et state when exiting EM4 2 SWUNLATCH Retention through EM4 and Wakeup software writes UNLATCH regis ter to remove retention 3 RETAINULFRCO 0 RW ULFRCO Retain During EM4S Retain the ULFRCO upon EM4S entry If set to 1 an already running ULFRCO will be retained in its running state in EM4 ULFRCO will always be retained if EM4STATE is in EM4H 2 RETAINLFXO 0 RW LFXO Retain During EM4 Retain the LFXO u...

Page 245: ...pt flag is set when a periodic temperature measurement is equal to or lower than this value If the low limit is changed during a temperature measurement TEMPACTIVE 1 the limit update will be delayed until the end of the temperature measurement 10 5 8 EMU_TEMP Value of Last Temperature Measurement Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 ...

Page 246: ...s to 0 More information in 1 2 Conven tions 25 VSCALEDONE 0 R Voltage Scale Steps Done IRQ Will be set when all the steps needed for voltage scaling is done For voltage upgrade the software can start increasing clock frequency after this interrupt For voltage downgrade this will indicate that hardware has finished all the steps includ ing updating of BOD levels and regultor controls but voltage dr...

Page 247: ...all A falling edge on VMON IOVDD0 channel has been detected 5 VMONDVDDRISE 0 R VMON DVDD Channel Rise A rising edge on VMON DVDD channel has been detected 4 VMONDVDDFALL 0 R VMON DVDD Channel Fall A falling edge on VMON DVDD channel has been detected 3 VMONALTAVDDRISE 0 R Alternate VMON AVDD Channel Rise A rising edge on Alternate VMON AVDD channel has been detected 2 VMONALTAVDDFALL 0 R Alternate...

Page 248: ...tibility with future devices always write bits to 0 More information in 1 2 Conven tions 25 VSCALEDONE 0 W1 Set VSCALEDONE Interrupt Flag Write 1 to set the VSCALEDONE interrupt flag 24 EM23WAKEUP 0 W1 Set EM23WAKEUP Interrupt Flag Write 1 to set the EM23WAKEUP interrupt flag 23 21 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 20 D...

Page 249: ...LL interrupt flag 5 VMONDVDDRISE 0 W1 Set VMONDVDDRISE Interrupt Flag Write 1 to set the VMONDVDDRISE interrupt flag 4 VMONDVDDFALL 0 W1 Set VMONDVDDFALL Interrupt Flag Write 1 to set the VMONDVDDFALL interrupt flag 3 VMONALTAVDDRISE 0 W1 Set VMONALTAVDDRISE Interrupt Flag Write 1 to set the VMONALTAVDDRISE interrupt flag 2 VMONALTAVDDFALL 0 W1 Set VMONALTAVDDFALL Interrupt Flag Write 1 to set the...

Page 250: ... ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 25 VSCALEDONE 0 R W1 Clear VSCALEDONE Interrupt Flag Write 1 to clear the VSCALEDONE interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 24 EM23WAKEUP 0 R W1 Clear EM23WAKEUP Interrupt Flag Write 1 to clear th...

Page 251: ...L interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 5 VMONDVDDRISE 0 R W1 Clear VMONDVDDRISE Interrupt Flag Write 1 to clear the VMONDVDDRISE interrupt flag Reading returns the value of the IF and clears the corresponding inter rupt flags This feature must be enabled globally in MSC 4 VMONDVDDFALL 0 R W1 Cle...

Page 252: ... ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 25 VSCALEDONE 0 RW VSCALEDONE Interrupt Enable Enable disable the VSCALEDONE interrupt 24 EM23WAKEUP 0 RW EM23WAKEUP Interrupt Enable Enable disable the EM23WAKEUP interrupt 23 21 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 20 DC...

Page 253: ...he VMONIO0FALL interrupt 5 VMONDVDDRISE 0 RW VMONDVDDRISE Interrupt Enable Enable disable the VMONDVDDRISE interrupt 4 VMONDVDDFALL 0 RW VMONDVDDFALL Interrupt Enable Enable disable the VMONDVDDFALL interrupt 3 VMONALTAVDDRISE 0 RW VMONALTAVDDRISE Interrupt Enable Enable disable the VMONALTAVDDRISE interrupt 2 VMONALTAVDDFALL 0 RW VMONALTAVDDFALL Interrupt Enable Enable disable the VMONALTAVDDFALL...

Page 254: ...Configuration Lock Key Write any other value than the unlock code to lock all regulator control registers from editing Write the unlock code to un lock When reading the register bit 0 is set when the lock is enabled Registers that are locked PWRCFG PWRCTRL and DCDC registers Mode Value Description Read Operation UNLOCKED 0 EMU Regulator registers are unlocked LOCKED 1 EMU Regulator registers are l...

Page 255: ...If DCDC is configured to drive DVDD hardware will make the switch to DVDD only when DCDC is stable Value Mode Description 0 AVDD The AVDD pin is the supply for the digital LDO LDO current is limited to 20 mA in this configuration 1 DVDD The DVDD pin is the supply for the digital LDO Firmware should set REGPWRSEL 1 after startup before increasing the core clock fre quency 9 6 Reserved To ensure com...

Page 256: ...pass Reset with POR Hard Pin Re set or BOD Reset Value Mode Description 0 EM23SW DCDC mode is according to DCDCMODE field 1 EM23LOWPOWER DCDC mode is low power 3 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 0 DCDCMODE 0x3 RW Regulator Mode Determines the operating mode of the DCDC regulator Reset with POR Hard Pin Reset or BOD...

Page 257: ...PFETCNT 1 1 where I_MAX is the maximum average current allowed to the load and 40mA represents the current ripple with some margin and the factor of 1 5 accounts for detecting error and other varia tions For strong i e low internal impedance battery it is recommended to have I_MAX 200mA I_MAX should never be set higher than 200mA to avoid reliability issues Reset with POR Hard Pin Reset or BOD res...

Page 258: ...ns 2 LPCMPHYSHI 1 RW Comparator Threshold on the High Side Reserved for internal use Should always be set to 1 1 LPCMPHYSDIS 1 RW Disable LP Mode Hysteresis in the State Machine Control Reserved for internal use Should always be set to 1 0 LNFORCECCM 0 RW Force DCDC Into CCM Mode in Low Noise Operation When this bit is set to 0 in low noise mode the zero detector is configured as zero crossing det...

Page 259: ...LNFORCECCM 1 in LN mode The configuration of this register is calculated by the allowed average reverse current I_RMAX through the equation ZDETILIMSEL I_RMAX 40mA 1 5 2 5mA NFETCNT 1 where 40mA represents the current ripple with some margin and the factor of 1 5 ac counts for detecting error and other variations When the battery can tolerate large reverse current it is recommended to have I_RMAX ...

Page 260: ... mode Note that the device will see an additional 10 μA of current draw when BYPLIMEN 1 and Bypass Mode is enabled To prevent this excess current applications should disable the Bypass Current Limit BYPLIMEN 0 once the DVDD voltage has reached the main supply voltage in Bypass Mode Reset with POR Hard Pin Reset or BOD Reset 12 10 Reserved To ensure compatibility with future devices always write bi...

Page 261: ...COMPENC1 0x2 RW Low Noise Mode Compensator C1 Trim Value LN mode compensator C1 trim 0 15pF 0 60pF in 0 15pF step Reset with POR Hard Pin Reset or BOD Reset 19 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 12 COMPENR3 0x4 RW Low Noise Mode Compensator R3 Trim Value LN mode compensator r3 trim 5 80KOhm in 5Khom steps Reset wit...

Page 262: ...ustomers should use the emlib functions for configuring this field Reset with POR Hard Pin Reset or BOD Reset 7 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 LNATT 0 RW Low Noise Mode Feedback Attenuation Low noise mode feedback attenuation Customers should use the emlib functions for configuring this field Reset with POR Hard ...

Page 263: ...nd EM4H Select Vref level Maximum available code is 8 b11100111 LPATT and LPVREFSEL set the output of the DCDC to 4 1 LPATT 30 LPVREF 2 2mV Customers should use the emlib functions for configuring this field Reset with POR Hard Pin Reset or BOD Reset 0 LPATT 0 RW Low Power Feedback Attenuation Low power feedback attenuation select Customers should use the emlib functions for configuring this field...

Page 264: ...w duty cycling of the bias This is to minimize DC bias Reset with POR Hard Pin Reset or BOD Reset 23 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 12 LPCMPHYSSE LEM234H 0x0 RW LP Mode Hysteresis Selection for EM23 and EM4H User programmable hysteresis level for the low power comparator Hysteresis voltage at the output is 4 1 ...

Page 265: ...mode RCO frequency selection 0 7 3 8 95MHz approximately 0 85MHz step when the radio is disabled 3 10MHz 1MHz step when the radio is enabled to match the clock frequency from the radio Reset with POR Hard Pin Reset or BOD Reset 10 5 24 EMU_DCDCSYNC DCDC Read Status Register Offset Bit Position 0x078 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Acces...

Page 266: ...n 15 12 FALLTHRES COARSE 0x0 RW Falling Threshold Coarse Adjust Check VMON section for programming the threshold value Reset with SYSEXTENDEDRESETn 11 8 FALLTHRESFINE 0x0 RW Falling Threshold Fine Adjust Check VMON section for programming the threshold value Reset with SYSEXTENDEDRESETn 7 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven t...

Page 267: ...x0 RW Threshold Fine Adjust Check VMON section for programming the threshold value Reset with SYSEXTENDEDRESETn 7 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 FALLWU 0 RW Fall Wakeup When set a wakeup from EM4H will take place upon a falling edge Reset with SYSEXTENDEDRESETn 2 RISEWU 0 RW Rise Wakeup When set a wakeup from EM4...

Page 268: ... Threshold Fine Adjust Check VMON section for programming the threshold value Reset with SYSEXTENDEDRESETn 7 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 FALLWU 0 RW Fall Wakeup When set a wakeup from EM4H will take place upon a falling edge Reset with SYSEXTENDEDRESETn 2 RISEWU 0 RW Rise Wakeup When set a wakeup from EM4H wil...

Page 269: ...e Reset with SYSEXTENDEDRESETn 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 4 RETDIS 0 RW EM4 IO0 Retention Disable When set the IO0 Retention will be disabled when this IO0 voltage drops below the threshold set Reset with SYSEXTEN DEDRESETn 3 FALLWU 0 RW Fall Wakeup When set a wakeup from EM4H will take place upon a falling e...

Page 270: ...ved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 0 RAMPOWERDOWN 0x0 RW RAM1 Blockset Power down RAM blockset power down in EM23 with full access in EM01 Value Mode Description 0 NONE None of the RAM blocks powered down 1 BLK Power down RAM block address range 0x20004000 0x20007FFC Reference Manual EMU Energy Management Unit silabs com Bu...

Page 271: ...o ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 0 RAMPOWERDOWN 0x0 RW RAM2 Blockset Power down RAM blockset power down in EM23 with full access in EM01 Mode Value Description NONE 0x00 None of the RAM blocks powered down BLK 0x1 Power down RAM blocks 0 3 address range 0x20040000 0x200407FF Reference Manual EMU Energy Management Unit silabs c...

Page 272: ...tage in at the output is 4 1 LPATT LPCMPHYSSEL 3 13mV Customers should use the emlib functions for configuring this field 11 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 9 8 LPCMPBIASEM01 0x3 RW LP Mode Comparator Bias Selection for EM01 Reserved for internal use Do not change Value Mode Description 0 BIAS0 Maximum load current...

Page 273: ... to It clears status bit of WDOG1 and unlocks access to it 11 WDOG0UNLOCK 0 W1 Clears Status Bit of WDOG0 and Unlocks Access to It clears status bit of WDOG0 and unlocks access to it 10 LETIMER0UNLOCK 0 W1 Clears Status Bit of LETIMER0 and Unlocks Access to It clears status bit of LETIMER0 and unlocks access to it 9 ADC0UNLOCK 0 W1 Clears Status Bit of ADC0 and Unlocks Access to It clears status b...

Page 274: ...cks Access to It clears status bit of ACMP1 and unlocks access to it 0 ACMP0UNLOCK 0 W1 Clears Status Bit of ACMP0 and Unlocks Access to It clears status bit of ACMP0 and unlocks access to it Reference Manual EMU Energy Management Unit silabs com Building a more connected world Rev 1 1 274 ...

Page 275: ...0 R Indicates If WDOG1 Powered Down During EM23 Indicates if WDOG1 powered down during EM23 Access to this peripheral locked until this bit cleared using EM23PER NORETAINCMD 11 WDOG0LOCKED 0 R Indicates If WDOG0 Powered Down During EM23 Indicates if WDOG0 powered down during EM23 Access to this peripheral locked until this bit cleared using EM23PER NORETAINCMD 10 LETIMER0LOCKED 0 R Indicates If LE...

Page 276: ...Indicates if PCNT0 powered down during EM23 Access to this peripheral locked until this bit cleared using EM23PER NORETAINCMD 1 ACMP1LOCKED 0 R Indicates If ACMP1 Powered Down During EM23 Indicates if ACMP1 powered down during EM23 Access to this peripheral locked until this bit cleared using EM23PER NORETAINCMD 0 ACMP0LOCKED 0 R Indicates If ACMP0 Powered Down During EM23 Indicates if ACMP0 power...

Page 277: ... 12 WDOG1DIS 0 RW Allow Power Down of WDOG1 During EM23 Allow power down of WDOG1 during EM23 11 WDOG0DIS 0 RW Allow Power Down of WDOG0 During EM23 Allow power down of WDOG0 during EM23 10 LETIMER0DIS 0 RW Allow Power Down of LETIMER0 During EM23 Allow power down of LETIMER0 during EM23 9 ADC0DIS 0 RW Allow Power Down of ADC0 During EM23 Allow power down of ADC0 during EM23 8 IDAC0DIS 0 RW Allow ...

Page 278: ...ower Down of ACMP1 During EM23 Allow power down of ACMP1 during EM23 0 ACMP0DIS 0 RW Allow Power Down of ACMP0 During EM23 Allow power down of ACMP0 during EM23 Reference Manual EMU Energy Management Unit silabs com Building a more connected world Rev 1 1 278 ...

Page 279: ...idual basis to all peripheral modules in addition to enable disable and configure the available oscillators The high degree of flexibility enables software to minimize energy consumption in any specific application by not wasting power on peripherals and oscillators that do not need to be active 11 2 Features Multiple clock sources available 38 MHz 40 MHz High Frequency Crystal Oscillator HFXO 1 M...

Page 280: ... CMU_HFBUSCLKEN0 GPIO HFBUSCLKGPIO HFBUSCLKBUSMATRIX 50 duty prescaler HFEXPCLK CMU_HFEXPPRESC PRESC HFBUSCLKLDMA CMU_HFBUSCLKEN0 LDMA DBGCLK AUX HFRCO CMU_ADCCTRL ADCnCLKINV CMU_ADCCTRL ADCnCLKSEL ADC_CLK ADCCLKMODE Availability of oscillators and clocks in Energy Modes Available in EM0 EM1 Available in EM0 EM1 EM2 Available in EM0 EM1 EM2 EM3 Available in EM0 EM1 EM2 EM3 EM4H Available in EM0 EM...

Page 281: ...LKLE CMU_HFBUSCLKEN0 LE Clock Gate 50 duty prescaler 2 4 CMU_LFACLKEN0 LETIMER0 LFACLKLETIMER0 PCNTnCLK PCNTn_S0 CMU_LFAPRESC0 LETIMER0 CMU_PCNTCTRL PCNTnCLKSEL LFACLKLESENSE CMU_LFAPRESC0 LESENSE CMU_LFACLKEN0 LESENSE Clock Gate Clock Gate prescaler prescaler Clock Gate prescaler Clock Gate CRYOTIMER prescaler 1024 HFCORECLKCORTEX prescaler CMU_LFEPRESC0 RTCC LFXO LFRCO ULFRCO HFCLKLE LFXO LFRCO ...

Page 282: ...clock is fed directly to the Radio Transceiver The clock received by the Radio Transceiver is therefore not affected by the selected clock source for HFSRCCLK nor by any clock prescaler 11 3 1 2 HFCORECLK High Frequency Core Clock HFCORECLK is a prescaled version of HFCLK This clock drives the Core Modules which consists of the CPU and modules that are tightly coupled to the CPU e g the cache The ...

Page 283: ...re are several selectable sources for LFACLK LFRCO LFXO and ULFRCO In addition the LFACLK can be disabled which is the default setting The selection is configured using the LFA field in CMU_LFACLKSEL The bus interface to the Low Energy A Peripherals is clocked by HFBUSCLKLE and this clock therefore needs to be enabled when programming a Low Energy LE peripheral Each Low Energy Peripheral that is c...

Page 284: ...d in CRYOTIMER_CTRL for a complete list The Cryotimer can also run in EM4 Hibernate Shutoff provided that its selected clock is kept enabled as configured in EMU_EM4CTRL 11 3 1 13 RFSENSECLK RFSENSE Clock The RFSENSE clock can be configured to use one of four different clock sources LFRCO LFXO ULFRCO or the RF Detector Clock The RFSENSE module can also run in EM4 Hibernate Shutoff provided that it...

Page 285: ...a WDOGn if it is config ured to use LFRCO as its clock source via the CLKSEL bitfield in WDOGn_CTRL while SWOSCBLOCK is set EM3 entry EM4 entry de pending on configuration in EMU_EM4CTRL LFXO Via LFXOEN in CMU_OSCENCMD Via LFXODIS in CMU_OSCENCMD Via WDOGn if it is config ured to use LFXO as its clock source via the CLKSEL bitfield in WDOGn_CTRL while SWOSCBLOCK is set EM3 entry EM4 entry de pendi...

Page 286: ...Enable LFXO LFRCO 4 EM4 entry 5 LFXO LFRCO are off in EM4 6 EM4 wakeup 7 Enable LFXO LFRCO 8 Set EM4UNLATCH in EMU_CMD 9 Enable RETAINLFXO RETAINLFRCO In summary RETAINLFXO RETAINLFRCO should either be changed once after POR and kept static or they can be changed on the fly only after asserting EM4UNLATCH Note In order to support usage of LFRCO and LFXO in EM4 their settings are automatically latc...

Page 287: ... HFRCO can be enabled and disabled by software via the CMU_OSCENCMD register The HFRCO is disabled automatically when entering EM2 EM3 or EM4 Further hardware based enabling and disabling can be performed by the LEUART when using automatic RX TX DMA wakeup as controlled by the RXDMAWU and TXDMAWU bits in the LEUARTn_CTRL register An automatic start and se lection of the HFXO will lead to an automa...

Page 288: ...ter enabling the AUXHFRCO it should not be disabled before it has been signaled to be enabled Similarly after disabling the AUXHFRCO it should not be re enabled before it has been signaled to be non enabled Typical enable and disable sequences are as follows CMU OSCENCMD CMU_OSCENCMD_AUXHFRCOEN while CMU STATUS CMU_STATUS_AUXHFRCOENS CMU_STATUS_AUXHFRCOENS CMU OSCENCMD CMU_OSCENCMD_AUXHFRCODIS whi...

Page 289: ...f LFECLK cycles as programmed in LFTIMEOUT The HFXO ready signal is asserted when both the TIMEOUT counter configured via the CMU_HFXOTIMEOUTCTRL register and the LFTIMEOUT counter configured via CMU_HFXOCTRL register have timed out as shown in Figure 11 3 CMU Deterministic HFXO startup using LFTIMEOUT on page 289 The TIMEOUT should cover the actual crystal startup time Typically the time base use...

Page 290: ...h is not ready yet the HFSRCCLK will stop for the duration of the oscilla tor start up time since the oscillator driving it is not ready This effectively stalls the Core Modules and the High Frequency Peripherals It is possible to avoid this by first enabling the target oscillator e g HFXO and then waiting for that oscillator to become ready before switching the clock source This way the system co...

Page 291: ...re 11 5 CMU Switching from HFRCO to HFXO after HFXO is ready Switching clock source for LFACLK LFBCLK and LFECLK is done by setting the LFA LFB and LFE bitfields in CMU_LFACLKSEL CMU_LFBCLKSEL and CMU_LFECLKSEL respectively To ensure no stalls in the Low Energy Peripherals the clock source should be ready before switching to it Note To save energy remember to turn off all oscillators not in use Re...

Page 292: ...RTUPCTRL and CMU_HFXOSTEADYSTATECTRL registers Configuration is required for both the startup state and the steady state of the HFXO After reaching the steady operation state of the HFXO further optimization can option ally be performed to optimize the HFXO for noise and current consumption Optimization for noise can be performed by an automatic Peak Detection Algorithm PDA Optimization for curren...

Page 293: ...Timeout configuration from CMU HFXOTIMEOUTCTRL PEAKDETTIMEOUT HFXORDY 1 HFXOPEAKDETRDY 1 HFXOPEAKDETRDY 1 PEAKDETSHUNTOPTMODE CMD HFXOSHUNTOPTRDY 1 STARTUPTIMEOUT Period Complete STEADYTIMEOUT Period Complete Crystal Oscillating Timeout configuration from CMU HFXOTIMEOUTCTRL STEADYTIMEOUT Timeout configuration from CMU HFXOTIMEOUTCTRL STEADYTIMEOUT Figure 11 7 CMU HFXO control state machine Refer ...

Page 294: ...t field in the CMU_HFXOTIMEOUTCTRL register is used to time the PDA steps and needs to be configured according to the device data sheet for the given crystal The PEAKDETEN bitfield of the CMU_HFXOSTEADYSTATECTRL register is only used during manual i e fully software controlled peak detection and is ignored during automatic or command based triggering of the PDA Note that the man ual PDA mode is no...

Page 295: ...isable or deselect the HFXO after removing all of the HFXO automatic enable or select reasons Note that if the autostart functionality is not used software can always disable or deselect the HFXO even if hardware requires the HFXO as indicated via HFXOREQ bitfield in CMU_STATUS The HFXODISERR flag will not get set in that case The HFXO is only disabled by hardware upon EM2 EM3 or EM4 entry In case...

Page 296: ...sed as HFSRCCLK at the time of automatic selection of the HFXO the LFXO remains unaffected The interaction between automatic HFXO startup and selection with startup and selection of HFRCO is shown in Figure 11 9 CMU HFRCO startup selection while awaiting automatic HFXO startup selection on page 296 and Figure 11 10 CMU Automatic HFXO start up selection while HFRCO started selected on page 297 HFXO...

Page 297: ...tatus HFXO ready EM0 EM1 Entry CMU_HFXOCTRL AUTOSTARTSELEM0EM1 0 Automatic switch to HFXO and disable of HFRCO HFRCO selected RAC wake up with CMU_HFXOCTRL AUTOSTARTRDYSELRAC 1 Figure 11 10 CMU Automatic HFXO startup selection while HFRCO started selected Reference Manual CMU Clock Management Unit silabs com Building a more connected world Rev 1 1 297 ...

Page 298: ...he LFXTAL_N pin of the LFXO oscillator If MODE is set to BUFEXTCLK an external active sine source can be used as clock source If MODE is set to DIGEXTCLK an external active CMOS source can be used as clock source The LFXO includes on chip tunable capacitance which can replace external load capacitors The TUNING bitfield of the CMU_LFXOCTRL register is used to tune the internal load capacitance con...

Page 299: ...nd disabled it should be tuned separately for both settings The HFRCO and AUXHFRCO contain a local prescaler which can be used in combination with any FREQRANGE setting These prescalers allow the output clocks to be divided by 1 2 or 4 as configured in the CLKDIV bitfield When using 11 3 2 8 RC Oscillator Calibration to tune HFRCO and AUXHFRCO to the desired frequency linear search must be used to...

Page 300: ...e sampled up counter value from CMU_CALCNT The up counter has counted the sampled value 1 cycles The ratio between the reference and the oscillator subject to the calibration can easily be found using top 1 and sample 1 Overflows of the up counter will not occur If the up counter reaches its top value before the down counter reaches 0 the up counter stays at its top value Calibration can be stoppe...

Page 301: ...ingle Calibration CONT 0 TOP 0 Calibration Started 0 Down counter Up counter Up counter sampled and CALRDY interrupt flag set Sampled value available in CMU_CALCNT Up counter sampled and CALRDY interrupt flag set Sampled value available in CMU_CALCNT Figure 11 15 Continuous Calibration CONT 1 Reference Manual CMU Clock Management Unit silabs com Building a more connected world Rev 1 1 301 ...

Page 302: ...tates when using this interface The required settings are shown in Table 11 4 LE Configuration for Operating Frequencies Low Energy Peripheral Interface on page 302 Before going to a high frequency make sure the registers in the table have the correct values When going down in frequency make sure to keep the registers at the values required by the higher frequency until after the switch has been d...

Page 303: ...nergy modes except for EM4 Shutoff but it can be retained on in that mode as well if needed The low frequency clocks LFACLK LFBCLK LFECLK WDOGnCLK RFSENSECLK and CRYOCLK are in various power domains and therefore their availability not only depends on the chosen clock source but also on the chosen energy mode as indicated in Table 11 5 Oscillator and Clock Availability in Energy Modes on page 303 ...

Page 304: ...a CMUCLKOUT0 CMUCLKOUT1 and CMUCLKOUT2 are selected via the CLKOUTSEL0 CLKOUTSEL1 and CLKOUTSEL2 fields respectively in CMU_CTRL Note that the CLKOUTSEL0 and CLKOUTSEL1 fields are also used for selecting which clock is output onto a pin as described in 11 3 5 Clock Output on a Pin In contrast with clock output on a pin however output of a clock onto PRS does not depend on any con figuration of the...

Page 305: ...ady as LFRCORDY and LFXORDY can be used as wake up interrupt 11 3 11 Protection It is possible to lock the control and command registers to prevent unintended software writes to critical clock settings This is control led by the CMU_LOCK register Reference Manual CMU Clock Management Unit silabs com Building a more connected world Rev 1 1 305 ...

Page 306: ...LFECLKSEL RW Low Frequency E Clock Select Register 0x090 CMU_STATUS R Status Register 0x094 CMU_HFCLKSTATUS R HFCLK Status Register 0x09C CMU_HFXOTRIMSTATUS R HFXO Trim Status 0x0A0 CMU_IF R Interrupt Flag Register 0x0A4 CMU_IFS W1 Interrupt Flag Set Register 0x0A8 CMU_IFC R W1 Interrupt Flag Clear Register 0x0AC CMU_IEN RW Interrupt Enable Register 0x0B0 CMU_HFBUSCLKEN0 RW High Frequency Bus Cloc...

Page 307: ...h Frequency Alternate Radio Peripheral Clock Prescaler Register 0x140 CMU_SYNCBUSY R Synchronization Busy Register 0x144 CMU_FREEZE RW Freeze Register 0x150 CMU_PCNTCTRL RWH PCNT Control Register 0x15C CMU_ADCCTRL RWH ADC Control Register 0x170 CMU_ROUTEPEN RW I O Routing Pin Enable Register 0x174 CMU_ROUTELOC0 RW I O Routing Location Register 0x178 CMU_ROUTELOC1 RW I O Routing Location Register 0...

Page 308: ...n tions 16 WSHFLE 0 RW Wait State for High Frequency LE Interface Set to allow access to LE peripherals when running HFBUSCLKLE at frequencies higher than 32 MHz 15 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 9 5 CLKOUTSEL1 0x00 RW Clock Output Select 1 Controls the clock output 1 multiplexer To actually output on the pin set ...

Page 309: ...sabled 1 ULFRCO ULFRCO directly from oscillator 2 LFRCO LFRCO directly from oscillator 3 LFXO LFXO directly from oscillator 6 HFXO HFXO directly from oscillator 7 HFEXPCLK HFEXPCLK 9 ULFRCOQ ULFRCO qualified 10 LFRCOQ LFRCO qualified 11 LFXOQ LFXO qualified 12 HFRCOQ HFRCO qualified 13 AUXHFRCOQ AUXHFRCO qualified 14 HFXOQ HFXO qualified 15 HFSRCCLK HFSRCCLK Reference Manual CMU Clock Management U...

Page 310: ...en obtained from the Device Information page entry for that band The TUNING FINE TUNING FINETUNINGEN and CLKDIV bitfields can be used to tune a specific band FREQRANGE of the oscillator to a non precon figured frequency When changing this setting there will be no glitches on the HFRCO output hence it is safe to change this setting Reference Manual CMU Clock Management Unit silabs com Building a mo...

Page 311: ...de Description 0 DIV1 Divide by 1 1 DIV2 Divide by 2 2 DIV4 Divide by 4 24 LDOHP 1 RWH HFRCO LDO High Power Mode Settings this bit puts the HFRCO LDO in high power mode 23 21 CMPBIAS 0x2 RWH HFRCO Comparator Bias Current Writing this field adjusts the HFRCO comparator bias current 20 16 FREQRANGE 0x08 RWH HFRCO Frequency Range Writing this field adjusts the HFRCO frequency range 15 14 Reserved To ...

Page 312: ...RW Locally Divide AUXHFRCO Clock Output Writing this field configures the AUXHFRCO clock output divider Value Mode Description 0 DIV1 Divide by 1 1 DIV2 Divide by 2 2 DIV4 Divide by 4 24 LDOHP 1 RW AUXHFRCO LDO High Power Mode Settings this bit puts the AUXHFRCO LDO in high power mode 23 21 CMPBIAS 0x2 RW AUXHFRCO Comparator Bias Current Writing this field adjusts the AUXHFRCO comparator bias curr...

Page 313: ...d on in EM4 then the TIMEOUT 2cy cles configuration is also allowed when re enabling the LFRCO after EM4 exit as it is still running Value Mode Description 0 2CYCLES Timeout period of 2 cycles 1 16CYCLES Timeout period of 16 cycles 2 32CYCLES Timeout period of 32 cycles 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 20 VREF...

Page 314: ... change when LFRCO is off 15 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 8 0 TUNING 0x100 RW LFRCO Tuning Value Writing this field adjusts the LFRCO frequency the higher the value the lower the frequency This field is updated with the production calibrated value during reset and the reset value might therefore vary between devi...

Page 315: ...r entry from EM2 EM3 Note that setting this bit to 1 will stall HFSRCCLK until HFXO becomes ready Allowed to change at any time 28 AUTOSTAR TEM0EM1 0 RW Automatically Start of HFXO Upon EM0 EM1 Entry From EM2 EM3 This bit enables automatic start up of the HFXO when in EM0 EM1 also after entry from EM2 EM3 without causing an automatic HFXO selection Allowed to change at any time 27 Reserved To ensu...

Page 316: ...c HFXO peak detection and shunt current optimization MANUAL mode provides direct control of IBTRIMXOCORE REGISH PEAKDETEN REGSELILOW Value Mode Description 0 AUTOCMD Automatic control of HFXO peak detection and shunt optimization se quences CMU_CMD HFXOPEAKDETSTART and HFXOSHUNTOPT START can also be used 1 CMD CMU_CMD HFXOPEAKDETSTART and HFXOSHUNTOPTSTART can be used to trigger peak detection and...

Page 317: ...ue is applied during the startup phase of the HFXO Capacitance on HFXTAL_N and HFXTAL_P pF Ctune Cpar CTUNE 8 0 X 40fF Max Ctune 25pF CLmax 12 5pF CL DNLmax 50fF 0 6ppm 12 5ppm pF 10 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 6 0 IBTRIMXOCORE 0x20 RW Sets the Startup Oscillator Core Bias Current This IBTRIMXOCORE value is appl...

Page 318: ...e devices always write bits to 0 More information in 1 2 Conven tions 19 11 CTUNE 0x168 RW Sets Oscillator Tuning Capacitance This CTUNE value is applied during the steady state phase of the HFXO as well as during the peak detection and shunt current optimization algorithms Capacitance on HFXTAL_N and HFXTAL_P pF Ctune Cpar CTUNE 8 0 X 40fF Max Ctune 25pF CLmax 12 5pF CL DNLmax 50fF 0 6ppm 12 5ppm...

Page 319: ... 1 4CYCLES Timeout period of 4 cycles 2 16CYCLES Timeout period of 16 cycles 3 32CYCLES Timeout period of 32 cycles 4 256CYCLES Timeout period of 256 cycles 5 1KCYCLES Timeout period of 1024 cycles 6 2KCYCLES Timeout period of 2048 cycles 7 4KCYCLES Timeout period of 4096 cycles 8 8KCYCLES Timeout period of 8192 cycles 9 16KCYCLES Timeout period of 16384 cycles 10 32KCYCLES Timeout period of 32768...

Page 320: ...eriod of 32 cycles 4 256CYCLES Timeout period of 256 cycles 5 1KCYCLES Timeout period of 1024 cycles 6 2KCYCLES Timeout period of 2048 cycles 7 4KCYCLES Timeout period of 4096 cycles 8 8KCYCLES Timeout period of 8192 cycles 9 16KCYCLES Timeout period of 16384 cycles 10 32KCYCLES Timeout period of 32768 cycles 3 0 STARTUPTIMEOUT 0x7 RW Wait Duration in HFXO Startup Enable Wait State Wait duration d...

Page 321: ... Reset Access Description 9 16KCYCLES Timeout period of 16384 cycles 10 32KCYCLES Timeout period of 32768 cycles Reference Manual CMU Clock Management Unit silabs com Building a more connected world Rev 1 1 321 ...

Page 322: ...096 cycles 5 8KCYCLES Timeout period of 8192 cycles 6 16KCYCLES Timeout period of 16384 cycles 7 32KCYCLES Timeout period of 32768 cycles 23 21 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 20 BUFCUR 0 RW LFXO Buffer Bias Current The default value is intended to cover all use cases and reprogramming is not recommended Do not change...

Page 323: ...in CMU_OSCENCMD Value Mode Description 0 XTAL 32768 Hz crystal oscillator 1 BUFEXTCLK An AC coupled buffer is coupled in series with LFXTAL_N pin suitable for external sinus wave 32768 Hz 2 DIGEXTCLK Digital external clock on LFXTAL_N pin Oscillator is effectively by passed 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 6 0 TUNING...

Page 324: ...as input 4 PRSCH4 PRS Channel 4 selected as input 5 PRSCH5 PRS Channel 5 selected as input 6 PRSCH6 PRS Channel 6 selected as input 7 PRSCH7 PRS Channel 7 selected as input 8 PRSCH8 PRS Channel 8 selected as input 9 PRSCH9 PRS Channel 9 selected as input 10 PRSCH10 PRS Channel 10 selected as input 11 PRSCH11 PRS Channel 11 selected as input 23 20 Reserved To ensure compatibility with future device...

Page 325: ...when calibration circuit is off Value Mode Description 0 HFCLK Select HFCLK for down counter 1 HFXO Select HFXO for down counter 2 LFXO Select LFXO for down counter 3 HFRCO Select HFRCO for down counter 4 LFRCO Select LFRCO for down counter 5 AUXHFRCO Select AUXHFRCO for down counter 6 PRS Select PRS input selected by PRSDOWNSEL as down counter 3 0 UPSEL 0x0 RW Calibration Up counter Select Select...

Page 326: ...e Reset Access Description 31 20 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 19 0 CALCNT 0x00000 RWH Calibration Counter Write top value before calibration Read calibration result from this register when Calibration Ready flag has been set Reference Manual CMU Clock Management Unit silabs com Building a more connected world Rev 1...

Page 327: ...e Disables the LFRCO LFRCOEN has higher priority if written simultaneously WARNING Do not disable the LFRCO if this oscillator is selected as the source for HFCLK When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect 6 LFRCOEN 0 W1 LFRCO Enable Enables the LFRCO When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect 5 AUXHFRCODIS 0 W...

Page 328: ...XO Shunt Current Optimization Start Starts the HFXO Shunt Current Optimization and runs it one time 4 HFXOPEAKDET START 0 W1 HFXO Peak Detection Start Starts the HFXO peak detection and runs it one time 3 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 CALSTOP 0 W1 Calibration Stop Stops the calibration counters 0 CALSTART 0 W1 C...

Page 329: ...ss W1 Name HF Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 0 HF 0x0 W1 HFCLK Select Selects the clock source for HFCLK Note that selecting an oscillator that is disabled will cause the system clock to stop Check the status register and confirm that oscillator is ready before switching If th...

Page 330: ...RCO selected as LFACLK 11 5 17 CMU_LFBCLKSEL Low Frequency B Clock Select Register Offset Bit Position 0x084 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 Access RW Name LFB Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 0 LFB 0x0 RW Clock Sel...

Page 331: ...ture devices always write bits to 0 More information in 1 2 Conven tions 2 0 LFE 0x0 RW Clock Select for LFE Selects the clock source for LFECLK When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect Value Mode Description 0 DISABLED LFECLK is disabled 1 LFRCO LFRCO selected as LFECLK 2 LFXO LFXO selected as LFECLK 4 ULFRCO ULFRCO selected as LFECLK Reference Manual...

Page 332: ...REGISH value in CMU_HFXOSTEADYSTATECTRL should be tuned up by 1 LSB 25 HFXOAMPLOW 0 R HFXO Amplitude Tuning Value Too Low HFXO oscillation amplitude is too low When using PEAKDETSHUNTOPTMODE MANUAL the IBTRIMXOCORE value in CMU_HFXOSTEADYSTATECTRL should be tuned up by 1 LSB 24 HFXOAMPHIGH 0 R HFXO Oscillation Amplitude is Too High HFXO oscillation amplitude is too high When using PEAKDETSHUNTOPTM...

Page 333: ... up time has exceeded 6 LFRCOENS 0 R LFRCO Enable Status LFRCO is enabled shows disabled status if EM4 repaint is required 5 AUXHFRCORDY 0 R AUXHFRCO Ready AUXHFRCO is enabled and start up time has exceeded 4 AUXHFRCOENS 0 R AUXHFRCO Enable Status AUXHFRCO is enabled 3 HFXORDY 0 R HFXO Ready HFXO is enabled start up and steady timeouts have been reached and the crystal is oscillating 2 HFXOENS 0 R...

Page 334: ...tion in 1 2 Conven tions 2 0 SELECTED 0x1 R HFCLK Selected Clock selected as HFCLK clock source Value Mode Description 1 HFRCO HFRCO is selected as HFCLK clock source 2 HFXO HFXO is selected as HFCLK clock source 3 LFRCO LFRCO is selected as HFCLK clock source 4 LFXO LFXO is selected as HFCLK clock source 5 HFRCODIV2 HFRCO divided by 2 is selected as HFCLK clock source 7 CLKIN0 CLKIN0 is selected ...

Page 335: ...n 1 2 Conven tions 10 7 REGISH 0xA R Value of REGISH Found By Automatic HFXO Shunt Current Opti mization Algorithm Can be used as initial value for REGISH value in the CMU_HFXOSTEADYSTATECTRL register if HFXO is to be started again 6 0 IBTRIMXOCORE 0x00 R Value of IBTRIMXOCORE Found By Automatic HFXO Peak Detec tion Algorithm Can be used as initial value for IBTRIMXOCORE in the CMU_HFXOSTEADYSTATE...

Page 336: ... Interrupt Flag Sets when LFXO clock switches phases 26 15 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 14 LFTIMEOUTERR 0 R Low Frequency Timeout Error Interrupt Flag Set when LFTIMEOUT of CMU_HFXOCTRL triggers before the combined STARTUPTIMEOUT plus STEADYTIMEOUT of the CMU_HFXOTIMEOUTCTRL register triggers 13 HFRCODIS 0 R HFRCO ...

Page 337: ...LRDY 0 R Calibration Ready Interrupt Flag Set when calibration is completed 4 AUXHFRCORDY 0 R AUXHFRCO Ready Interrupt Flag Set when AUXHFRCO is ready start up time exceeded 3 LFXORDY 0 R LFXO Ready Interrupt Flag Set when LFXO is ready start up time exceeded LFXORDY can be used as wake up interrupt 2 LFRCORDY 0 R LFRCO Ready Interrupt Flag Set when LFRCO is ready start up time exceeded LFRCORDY c...

Page 338: ... set the LFRCOEDGE interrupt flag 27 LFXOEDGE 0 W1 Set LFXOEDGE Interrupt Flag Write 1 to set the LFXOEDGE interrupt flag 26 15 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 14 LFTIMEOUTERR 0 W1 Set LFTIMEOUTERR Interrupt Flag Write 1 to set the LFTIMEOUTERR interrupt flag 13 HFRCODIS 0 W1 Set HFRCODIS Interrupt Flag Write 1 to set...

Page 339: ... 0 W1 Set AUXHFRCORDY Interrupt Flag Write 1 to set the AUXHFRCORDY interrupt flag 3 LFXORDY 0 W1 Set LFXORDY Interrupt Flag Write 1 to set the LFXORDY interrupt flag 2 LFRCORDY 0 W1 Set LFRCORDY Interrupt Flag Write 1 to set the LFRCORDY interrupt flag 1 HFXORDY 0 W1 Set HFXORDY Interrupt Flag Write 1 to set the HFXORDY interrupt flag 0 HFRCORDY 0 W1 Set HFRCORDY Interrupt Flag Write 1 to set the...

Page 340: ...nding interrupt flags This feature must be enabled globally in MSC 27 LFXOEDGE 0 R W1 Clear LFXOEDGE Interrupt Flag Write 1 to clear the LFXOEDGE interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 26 15 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven ...

Page 341: ...t flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 4 AUXHFRCORDY 0 R W1 Clear AUXHFRCORDY Interrupt Flag Write 1 to clear the AUXHFRCORDY interrupt flag Reading returns the value of the IF and clears the corresponding inter rupt flags This feature must be enabled globally in MSC 3 LFXORDY 0 R W1 Clear LFXORDY Interru...

Page 342: ...rupt Enable Enable disable the LFRCOEDGE interrupt 27 LFXOEDGE 0 RW LFXOEDGE Interrupt Enable Enable disable the LFXOEDGE interrupt 26 15 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 14 LFTIMEOUTERR 0 RW LFTIMEOUTERR Interrupt Enable Enable disable the LFTIMEOUTERR interrupt 13 HFRCODIS 0 RW HFRCODIS Interrupt Enable Enable disabl...

Page 343: ...AUXHFRCORDY 0 RW AUXHFRCORDY Interrupt Enable Enable disable the AUXHFRCORDY interrupt 3 LFXORDY 0 RW LFXORDY Interrupt Enable Enable disable the LFXORDY interrupt 2 LFRCORDY 0 RW LFRCORDY Interrupt Enable Enable disable the LFRCORDY interrupt 1 HFXORDY 0 RW HFXORDY Interrupt Enable Enable disable the HFXORDY interrupt 0 HFRCORDY 0 RW HFRCORDY Interrupt Enable Enable disable the HFRCORDY interrupt...

Page 344: ...nable Set to enable the clock for GPCRC 4 LDMA 0 RW Linked Direct Memory Access Controller Clock Enable Set to enable the clock for LDMA 3 PRS 0 RW Peripheral Reflex System Clock Enable Set to enable the clock for PRS 2 GPIO 0 RW General purpose Input Output Clock Enable Set to enable the clock for GPIO 1 CRYPTO0 0 RW Advanced Encryption Standard Accelerator 0 Clock Enable Set to enable the clock ...

Page 345: ...Converter 0 Clock Enable Set to enable the clock for VDAC0 9 ADC0 0 RW Analog to Digital Converter 0 Clock Enable Set to enable the clock for ADC0 8 I2C0 0 RW I2C 0 Clock Enable Set to enable the clock for I2C0 7 CRYOTIMER 0 RW CryoTimer Clock Enable Set to enable the clock for CRYOTIMER 6 ACMP1 0 RW Analog Comparator 1 Clock Enable Set to enable the clock for ACMP1 5 ACMP0 0 RW Analog Comparator ...

Page 346: ... Conven tions 11 5 29 CMU_LFACLKEN0 Low Frequency a Clock Enable Register 0 Async Reg Offset Bit Position 0x0E0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access RW RW Name LESENSE LETIMER0 Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 LES...

Page 347: ...le the clock for LEUART0 0 SYSTICK 0 RW Clock Enable Set to enable the clock for SYSTICK 11 5 31 CMU_LFECLKEN0 Low Frequency E Clock Enable Register 0 Async Reg Offset Bit Position 0x0F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access RW Name RTCC Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always ...

Page 348: ...ifies the clock divider for HFCLKLE Value Mode Description 0 DIV2 HFCLKLE is HFBUSCLKLE divided by 2 1 DIV4 HFCLKLE is HFBUSCLKLE divided by 4 23 13 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 8 PRESC 0x00 RW HFCLK Prescaler Specifies the clock divider for HFCLK relative to HFSRCCLK Value Description PRESC Clock division facto...

Page 349: ...e bits to 0 More information in 1 2 Conven tions 11 5 34 CMU_HFPERPRESC High Frequency Peripheral Clock Prescaler Register Offset Bit Position 0x10C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000 Access RW Name PRESC Bit Name Reset Access Description 31 17 Reserved To ensure compatibility with future devices always write bits to 0 More information...

Page 350: ...es always write bits to 0 More information in 1 2 Conven tions 11 5 36 CMU_HFEXPPRESC High Frequency Export Clock Prescaler Register Offset Bit Position 0x114 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RW Name PRESC Bit Name Reset Access Description 31 13 Reserved To ensure compatibility with future devices always write bits to 0 More in...

Page 351: ...SE LFACLK 2 2 DIV4 LFACLKLESENSE LFACLK 4 3 DIV8 LFACLKLESENSE LFACLK 8 3 0 LETIMER0 0x0 RW Low Energy Timer 0 Prescaler Configure Low Energy Timer 0 prescaler Value Mode Description 0 DIV1 LFACLKLETIMER0 LFACLK 1 DIV2 LFACLKLETIMER0 LFACLK 2 2 DIV4 LFACLKLETIMER0 LFACLK 4 3 DIV8 LFACLKLETIMER0 LFACLK 8 4 DIV16 LFACLKLETIMER0 LFACLK 16 5 DIV32 LFACLKLETIMER0 LFACLK 32 6 DIV64 LFACLKLETIMER0 LFACLK...

Page 352: ...Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 4 LEUART0 0x0 RW Low Energy UART 0 Prescaler Configure Low Energy UART 0 prescaler Value Mode Description 0 DIV1 LFBCLKLEUART0 LFBCLK 1 DIV2 LFBCLKLEUART0 LFBCLK 2 2 DIV4 LFBCLKLEUART0 LFBCLK 4 3 DIV8 LFBCLKLEUART0 LFBCLK 8 3 0 SYSTICK 0x0 Prescaler Configure p...

Page 353: ...LKRTCC LFECLK 2 2 DIV4 LFECLKRTCC LFECLK 4 11 5 40 CMU_HFRADIOALTPRESC High Frequency Alternate Radio Peripheral Clock Prescaler Register Offset Bit Position 0x138 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000 Access RW Name PRESC Bit Name Reset Access Description 31 17 Reserved To ensure compatibility with future devices always write bits to 0 M...

Page 354: ...ynchronization status of CMU_HFXOCTRL CMU_HFXOSTARTUPCTRL CMU_HFXOSTEADYSTA TECTRL CMU_HFXOTIMEOUTCTRL CMU_HFXOCTRL1 Value Description 0 CMU_HFXOCTRL CMU_HFXOSTARTUPCTRL CMU_HFXOSTEA DYSTATECTRL CMU_HFXOTIMEOUTCTRL CMU_HFXOCTRL1 are ready for update 1 CMU_HFXOCTRL CMU_HFXOSTARTUPCTRL CMU_HFXOSTEA DYSTATECTRL CMU_HFXOTIMEOUTCTRL CMU_HFXOCTRL1 are busy synchronizing new value HFXO is also BUSY when ...

Page 355: ...s ready for update 1 CMU_LFEPRESC0 is busy synchronizing new value 17 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 16 LFECLKEN0 0 R Low Frequency E Clock Enable 0 Busy Used to check the synchronization status of CMU_LFECLKEN0 Value Description 0 CMU_LFECLKEN0 is ready for update 1 CMU_LFECLKEN0 is busy synchronizing new value 15 7...

Page 356: ...scaler 0 Busy Used to check the synchronization status of CMU_LFAPRESC0 Value Description 0 CMU_LFAPRESC0 is ready for update 1 CMU_LFAPRESC0 is busy synchronizing new value 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 LFACLKEN0 0 R Low Frequency a Clock Enable 0 Busy Used to check the synchronization status of CMU_LFACLKEN0 V...

Page 357: ...0 REGFREEZE 0 RW Register Update Freeze When set the update of the Low Frequency clock control registers is postponed until this bit is cleared Use this bit to up date several registers simultaneously Value Mode Description 0 UPDATE Each write access to a Low Frequency clock control register is updated into the Low Frequency domain as soon as possible 1 FREEZE The LE Clock Control registers are no...

Page 358: ...ibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 PCNT0CLKSEL 0 RWH PCNT0 Clock Select This bit controls which clock that is used for the PCNT Value Mode Description 0 LFACLK LFACLK is clocking PCNT0 1 PCNT0S0 External pin PCNT0_S0 is clocking PCNT0 0 PCNT0CLKEN 0 RWH PCNT0 Clock Enable This bit enables disables the clock to the PCNT Reference Manual CMU Clo...

Page 359: ...write bits to 0 More information in 1 2 Conven tions 5 4 ADC0CLKSEL 0x0 RWH ADC0 Clock Select This bit controls which clock is used for ADC0 in case ADCCLKMODE in ADCn_CTRL is set to ASYNC It should only be changed when ADCCLKMODE in ADCn_CTRL is set to SYNC HFXO should never be selected as clock source for ADC0 when disabling the HFXO e g because of EM2 entry Value Mode Description 0 DISABLED ADC...

Page 360: ... future devices always write bits to 0 More information in 1 2 Conven tions 28 CLKIN0PEN 0 RW CLKIN0 Pin Enable When set the CLKIN0 pin is enabled 27 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 CLKOUT1PEN 0 RW CLKOUT1 Pin Enable When set the CLKOUT1 pin is enabled 0 CLKOUT0PEN 0 RW CLKOUT0 Pin Enable When set the CLKOUT0 pin ...

Page 361: ...the CLKOUT1 Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 0 CLKOUT0LOC 0x00 RW I O Location Decides the location of the CMU CLKOUT0 Value Mode Description 0 LOC...

Page 362: ...Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 0 CLKIN0LOC 0x00 RW I O Location Decides the location of the CLKIN0 Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 Reference Manual CMU Clock Management Unit silabs com Building a more connected ...

Page 363: ...CMU_LFXOCTRL CMU_OSCENCMD CMU_CMD CMU_DBGCLKSEL CMU_HFCLKSEL CMU_LFACLKSEL CMU_LFBCLKSEL CMU_LFECLKSEL CMU_LFRCLKSEL CMU_HFBUSCLKEN0 CMU_HFUNDIVCLKEN0 CMU_HFPERCLKEN0 CMU_HFRADIOCLKEN0 CMU_HFRADIOALTCLKEN0 CMU_HFPRESC CMU_HFCORE PRESC CMU_HFPERPRESC CMU_HFRADIOPRESC CMU_HFRADIOALTPRESC CMU_HFEXPPRESC CMU_LFACLKEN0 CMU_LFBCLKEN0 CMU_LFECLKEN0 CMU_LFRCLKEN0 CMU_LFAPRESC0 CMU_LFBPRESC0 CMU_LFEPRESC0 ...

Page 364: ...M starts up in privileged mode and the MPU is disabled after reset which means all regions in the memory map are access ble to the running application code For many applications this is sufficient and the MPU remains disabled However when using a RTOS the kernel requires protection from user code and will switch to privileged mode and create tasks in non privileged or thread mode In addition secur...

Page 365: ...ate the performance degradation associated with a partially software managed solution The PPU provides a hardware access barrier to any peripheral that is configured to be protected When an attempt is made to access a peripheral without the required privilege level the PPU detects the fault and intercepts the access No write or read of the peripheral register space occurs and an all zero value is ...

Page 366: ...ndler is entered which signals the supervisor to reprogram the regions using the SMU based on an access control list Control is then handed to Task B in non privileged mode Figure 12 2 Peripheral Access Control Example All hardware protections happen immediately in response to SMU configuration register writes without any latency cycles However since software instructions may be optimized or pipel...

Page 367: ...vilege credentials then an access fault occurs The corresponding interrupt flag in SMU_IF is asserted and the ID of the peripheral for which an unpriviliged access was attempted is captured in the PERIPHID bit field of the PPU Fault Status register SMU_PPUFS This peripheral ID is held stable until all PPU interrupt flags are cleared to ensure that the first unprivileged access that caused the faul...

Page 368: ...ag Triggered when a privilege fault occurs in the Peripheral Protection Unit 12 5 2 SMU_IFS Interrupt Flag Set Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access W1 Name PPUPRIV Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 ...

Page 369: ...ding returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 12 5 4 SMU_IEN Interrupt Enable Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access RW Name PPUPRIV Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices a...

Page 370: ...escription 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 ENABLE 0 RW Set to enable checking of peripheral access Value Description 0 Privilege Security level checking completely bypassed in the PPU 1 Behavior controlled by PPU_PATD Reference Manual SMU Security Management Unit silabs com Building a more connected world Rev 1...

Page 371: ...rite bits to 0 More information in 1 2 Conven tions 24 PCNT0 0 RW Pulse Counter 0 access control bit Access control only for PCNT0 23 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 22 LEUART0 0 RW Low Energy UART 0 access control bit Access control only for LEUART0 21 LETIMER0 0 RW Low Energy Timer 0 access control bit Access contro...

Page 372: ...dard Accelerator 0 access control bit Access control only for CRYPTO0 7 CRYOTIMER 0 RW CryoTimer access control bit Access control only for CRYOTIMER 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 CMU 0 RW Clock Management Unit access control bit Access control only for CMU 4 3 Reserved To ensure compatibility with future device...

Page 373: ...rol bit Access control only for WDOG1 6 WDOG0 0 RW Watchdog 0 access control bit Access control only for WDOG0 5 USART1 0 RW Universal Synchronous Asynchronous Receiver Transmitter 1 ac cess control bit Access control only for USART1 4 USART0 0 RW Universal Synchronous Asynchronous Receiver Transmitter 0 ac cess control bit Access control only for USART0 3 TRNG0 0 RW True Random Number Generator 0...

Page 374: ...tion 0 ACMP0 Analog Comparator 0 1 ACMP1 Analog Comparator 1 2 ADC0 Analog to Digital Converter 0 5 CMU Clock Management Unit 7 CRYOTIMER CryoTimer 8 CRYPTO0 Advanced Encryption Standard Accelerator 0 9 VDAC0 Digital to Analog Converter 0 10 PRS Peripheral Reflex System 11 EMU Energy Management Unit 12 FPUEH FPU Exception Handler 14 GPCRC General Purpose CRC 15 GPIO General purpose Input Output 16...

Page 375: ...om Number Generator 0 36 USART0 Universal Synchronous Asynchronous Receiver Transmitter 0 37 USART1 Universal Synchronous Asynchronous Receiver Transmitter 1 38 WDOG0 Watchdog 0 39 WDOG1 Watchdog 1 40 WTIMER0 Wide Timer 0 Reference Manual SMU Security Management Unit silabs com Building a more connected world Rev 1 1 375 ...

Page 376: ...y modes except EM4 Shutoff Three individually configurable Capture Compare channels are available in the RTCC These can be used to trigger interrupts generate PRS signals capture system events and to wake the device up from a low energy mode The RTCC also includes 128 bytes of general purpose storage and a Binary Coded Decimal BCD calendar mode enabling easy time and date keeping 13 2 Features 32 ...

Page 377: ...n n 0 1 2 Capture logic n CC0 Capture Compare RTCC_CCx_CCV CC1 CC2 Capture PRS Inputs Interrupt generation OF RTCC_CC_CTRL_CMOA CC0 CC1 CC2 CNT Overflow RTCC_CC2_CCV output to FRC RTCC_CTRL_COMP1TOP Clear CC1 compare match LFCLKRTCC Pre Counter RTCC_PRECNT RTCC_CC_CTRL_COMPBASE RTCC_CC_CTRL_COMPMASK Mask RTCC_CTRL_CNTTICK CCV0MATCH Clear RTCC_PRECNT RTCC_CC0_CCV 14 0 CNT PRECNT PRS output Oscillat...

Page 378: ...ll wrap around when it hits the value configured in RTCC_CC0_CCV The main counter of the RTCC RTCC_CNT has two modes normal mode and calendar mode In normal mode the main counter is available in RTCC_CNT and increments upon each tick given from the pre counter Refer to 13 3 1 1 Normal Mode for a description on how to configure the frequency of these ticks In calendar mode the counter value is avai...

Page 379: ... 68 years DIV32768 1 s 136 years By default the counter will keep counting until it reaches the top value 0xFFFFFFFF before it wraps around and continues counting from zero By setting CCV1TOP in RTCC_CTRL a Capture Compare channel 1 compare match will result in the main counter wrap ping to 0 The timer will then wrap around on a channel 1 compare match RTCC_CNT RTCC_CC1_CCV Before using the CCV1TO...

Page 380: ... Compare channel The RTCC will automatically compensate for 28 29 leap year 30 and 31 day months The day of week counter RTCC_DATE_DAYOW is a three bit counter incrementing when RTCC_TIME_HOURT overflows wrapping around every seventh day Automatic leap year correction extending the month of February from 28 to 29 days every fourth year is by default enabled but can be disabled by setting the LYEAR...

Page 381: ... as long as the registers are not locked using RTCC_LOCKKEY All RTCC registers use the immediate synchroniza tion scheme described in 4 3 1 Writing Note Writing to the RTCC_PRECNT register may alter the frequency of the ticks for the RTCC_CNT register Reference Manual RTCC Real Time Counter and Calendar silabs com Building a more connected world Rev 1 1 381 ...

Page 382: ...and RTCC_CCx_DATE in calendar mode register when an edge is detected on the selected PRS input channel The active capture edge is configured in the ICEDGE control bits In output compare mode the compare values are set by writing to the RTCC compare channel registers RTCC_CCx_CCV RTCC_CCx_TIME and RTCC_CCx_DATE in calendar mode These values will be compared to the main counter RTCC_CNT RTCC_TIME an...

Page 383: ... RTCC_CNT 16 0 RTCC_PRECNT 14 0 vs RTCC_CCx_CCV RTCC_PRECNT vs RTCC_CCx_CCV 14 0 Figure 13 5 RTCC Compare in calendar mode COMPBASE CNT on page 384 illustrates how the compare events are evaluated when in calendar mode with RTCC_CCx_CTRL_COMPBASE CNT The SECU SECT MINU MINT HOURU HOURT MONTHU and MONTHT bitfields in RTCC_CCx_TIME and RTCC_CCx_DATE are compared to the corresponding bitfields in RTC...

Page 384: ...COMPMASK 0 31 MASKED Subject to comparison 20 21 0 Figure 13 6 RTCC Compare mask illustration COMPMASK 11 Upon a compare match the respective Capture Compare interrupt flag CCx is set Additionally the event selected by the CMOA setting is generated on the corresponding PRS output This is illustrated in Figure 13 3 RTCC Compare match and PRS output illustration on page 382 13 3 3 Interrupts and PRS...

Page 385: ...cted by this lock are RTCC_CTRL RTCC_PRECNT RTCC_CNT RTCC_TIME RTCC_DATE RTCC_IEN RTCC_POWERDOWN RTCC_CCx_CTRL RTCC_CCx_CCV RTCC_CCx_TIME RTCC_CCx_DATE 13 3 6 Oscillator Failure Detection To be able to detect OSC failure the RTCC includes a security mechanism ensuring that at least three OSC cycles are detected within one period of the ULFRCO If no OSC cycles are detected the OSCFAIL interrupt fla...

Page 386: ...038 RTCC_LOCK RWH Configuration Lock Register 0x03C RTCC_EM4WUEN RW Wake Up Enable 0x040 RTCC_CC0_CTRL RW CC Channel Control Register 0x044 RTCC_CC0_CCV RWH Capture Compare Value Register 0x048 RTCC_CC0_TIME RWH Capture Compare Time Register 0x04C RTCC_CC0_DATE RWH Capture Compare Date Register 0x050 RTCC_CC1_CTRL RW CC Channel Control Register 0x054 RTCC_CC1_CCV RWH Capture Compare Value Register...

Page 387: ...he main counter is incremented with 1 for each tick 1 CALENDAR The main counter is in calendar mode 15 OSCFDETEN 0 RW Oscillator Failure Detection Enable When set the OSCFAIL interrupt flag will be set if no ticks are detected on LFCLKRTCC within one ULFRCO cycle 14 13 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 CNTTICK 0 RW C...

Page 388: ...Conven tions 5 CCV1TOP 0 RW CCV1 Top Value Enable When set the counter wraps around on a CC1 event 4 PRECCV0TOP 0 RW Pre counter CCV0 Top Value Enable When set the pre counter wraps around when PRECNT equals RTCC_CC0_CCV 14 0 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 DEBUGRUN 0 RW Debug Mode Run Enable Set this bit to keep ...

Page 389: ...Pre Counter Value Gives access to the Pre counter value of the RTCC 13 5 3 RTCC_CNT Counter Value Register Async Reg For more information about asynchronous registers see 4 3 Access to Low Energy Peripherals Asynchronous Registers Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RWH Name CNT Bit Name Reset Acces...

Page 390: ...Bit Name Reset Access Description 31 15 CNTLSB 0x00000 R Counter Value Gives access to the 17 LSBs of the main counter CNT Register will be read as zero when RTCC_CTRL_CNTMODE CALENDAR 14 0 PRECNT 0x0000 R Pre Counter Value Gives access to the pre counter PRECNT Register will be read as zero when RTCC_CTRL_CNTMODE CALENDAR Reference Manual RTCC Real Time Counter and Calendar silabs com Building a ...

Page 391: ... zero when RTCC_CTRL_CNTMODE NORMAL 15 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 14 12 MINT 0x0 RWH Minutes Tens Shows the tens part of the minute counter Register can not be written and will be read as zero when RTCC_CTRL_CNTMODE NORMAL 11 8 MINU 0x0 RWH Minutes Units Shows the unit part of the minute counter Register can not ...

Page 392: ...f the year counter Register can not be written and will be read as zero when RTCC_CTRL_CNTMODE NORMAL 15 13 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 MONTHT 0 RWH Month Tens Shows the tens part of the month counter Register can not be written and will be read as zero when RTCC_CTRL_CNTMODE NORMAL 11 8 MONTHU 0x0 RWH Month Un...

Page 393: ...verflows 8 DAYTICK 0 R Day Tick Set each time the day counter increments 7 HOURTICK 0 R Hour Tick Set each time the hour counter increments 6 MINTICK 0 R Minute Tick Set each time the minute counter increments 5 CNTTICK 0 R Main Counter Tick Set each time the main counter is updated 4 OSCFAIL 0 R Oscillator Failure Interrupt Flag Set when an oscillator failure has been detected 3 CC2 0 R Channel 2...

Page 394: ...upt flag 8 DAYTICK 0 W1 Set DAYTICK Interrupt Flag Write 1 to set the DAYTICK interrupt flag 7 HOURTICK 0 W1 Set HOURTICK Interrupt Flag Write 1 to set the HOURTICK interrupt flag 6 MINTICK 0 W1 Set MINTICK Interrupt Flag Write 1 to set the MINTICK interrupt flag 5 CNTTICK 0 W1 Set CNTTICK Interrupt Flag Write 1 to set the CNTTICK interrupt flag 4 OSCFAIL 0 W1 Set OSCFAIL Interrupt Flag Write 1 to...

Page 395: ... IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 6 MINTICK 0 R W1 Clear MINTICK Interrupt Flag Write 1 to clear the MINTICK interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 5 CNTTICK 0 R W1 Clear CNTTICK Interrupt Flag Write 1 to clear the CNTTICK interrupt flag ...

Page 396: ...K 0 RW MONTHTICK Interrupt Enable Enable disable the MONTHTICK interrupt 9 DAYOWOF 0 RW DAYOWOF Interrupt Enable Enable disable the DAYOWOF interrupt 8 DAYTICK 0 RW DAYTICK Interrupt Enable Enable disable the DAYTICK interrupt 7 HOURTICK 0 RW HOURTICK Interrupt Enable Enable disable the HOURTICK interrupt 6 MINTICK 0 RW MINTICK Interrupt Enable Enable disable the MINTICK interrupt 5 CNTTICK 0 RW C...

Page 397: ...ys write bits to 0 More information in 1 2 Conven tions 0 CLRSTATUS 0 W1 Clear RTCC_STATUS Register Write a 1 to clear the RTCC_STATUS register 13 5 13 RTCC_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name CMD Bit Name Reset Access Description 31 6 Reserved To ensure compatib...

Page 398: ...eripherals Asynchronous Registers Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RWH Name LOCKKEY Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 LOCKKEY 0x0000 RWH Configuration Lock Key Write any other v...

Page 399: ...me EM4WU Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 EM4WU 0 RW EM4 Wake up Enable Write 1 to enable wake up request write 0 to disable wake up request Reference Manual RTCC Real Time Counter and Calendar silabs com Building a more connected world Rev 1 1 399 ...

Page 400: ...el Comparison Mask The COMPMASK most significant bits of the compare value will not be subject to comparison 11 COMPBASE 0 RW Capture Compare Channel Comparison Base Configure comparison base for compare channel Value Mode Description 0 CNT RTCC_CCx_CCV is compared with RTCC_CNT register RTCC_CCx_TIME DATE compare with RTCC_TIME DATE in calendar mode 1 PRECNT Least significant bits of RTCC_CCx_CCV...

Page 401: ...tected 2 BOTH Both edges detected 3 NONE No edge detection signal is left as it is 3 2 CMOA 0x0 RW Compare Match Output Action Select output action on compare match Value Mode Description 0 PULSE A single clock cycle pulse is generated on output 1 TOGGLE Toggle output on compare match 2 CLEAR Clear output on compare match 3 SET Set output on compare match 1 0 MODE 0x0 RW CC Channel Mode These bits...

Page 402: ... 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RWH Name CCV Bit Name Reset Access Description 31 0 CCV 0x00000000 RWH Capture Compare Value Shows the Capture Compare Value for the channel Register can not be written and will be read as zero when RTCC_CTRL_CNTMODE CALENDAR Reference Manual RTCC Real Time Counter and Calendar silabs com Building a more conn...

Page 403: ...TCC_CTRL_CNTMODE NORMAL 15 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 14 12 MINT 0x0 RWH Minutes Tens Shows the tens part of the Capture Compare value for minutes Register can not be written and will be read as zero when RTCC_CTRL_CNTMODE NORMAL 11 8 MINU 0x0 RWH Minutes Units Shows the unit part of the Capture Compare value for...

Page 404: ... for months Register can not be written and will be read as zero when RTCC_CTRL_CNTMODE NORMAL 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 4 DAYT 0x0 RWH Day of Month week Tens Shows the tens part of the Capture Compare value for days Register can not be written and will be read as zero when RTCC_CTRL_CNTMODE NORMAL 3 0 DAY...

Page 405: ... Configurable timeout period from 9 to 256k watchdog clock cycles Individual selection to keep running or freeze when entering EM2 Deep Sleep or EM3 Stop Selection to keep running or freeze when entering debug mode Selection to block the CPU from entering Energy Mode 4 Selection to block the CMU from disabling the selected watchdog clock Configurable warning interrupt at 25 50 or 75 of the timeout...

Page 406: ...e is no difference between EM0 Active and EM1 Sleep The watchdog does not run in EM4 Hibernate Shutoff If EM4BLOCK in WDOGn_CTRL is set the CPU will be prevented from entering EM4 Hibernate Shutoff by software request Note If the WDOG is clocked by the LFXO or LFRCO writing the SWOSCBLOCK bit will prevent the CPU from entering EM3 Stop When running from the ULFRCO writing the SWOSCBLOCK bit will p...

Page 407: ... Figure 14 2 WDOG Warning Window and Timeout on page 407 illustrates the warning the window and the time out interrupts Also it shows where the prs rising edge needs to happen The prs edge detection feature is discussed later Timeout period Counter value Time Watchdog clear System reset Warning Irq Legal Window PRS Event Figure 14 2 WDOG Warning Window and Timeout When the watchdog is enabled it i...

Page 408: ...by software Timeout period Counter value Time PRS clear Timeout Irq Warning Irq Legal Window Figure 14 2 PRS Clearing WDOG 14 3 8 PRS Rising Edge Monitoring PRS channels can be used to monitor multiple processes If enabled every time the watch dog timer is cleared the PRS channels are checked and any channel which has not seen an event can trigger an interrupt Counter value Time wdog clear PRS 0 P...

Page 409: ...USY R Synchronization Busy Register 0x00C WDOGn_PCH0_PRSCTRL RW PRS Control Register 0x010 WDOGn_PCH1_PRSCTRL RW PRS Control Register 0x01C WDOG_IF R Watchdog Interrupt Flags 0x020 WDOG_IFS W1 Interrupt Flag Set Register 0x024 WDOG_IFC R W1 Interrupt Flag Clear Register 0x028 WDOG_IEN RW Interrupt Enable Register Reference Manual WDOG Watchdog Timer silabs com Building a more connected world Rev 1...

Page 410: ...1 DIS A timeout will not cause a watchdog reset 30 CLRSRC 0 RW Watchdog Clear Source Select watchdog clear source Value Mode Description 0 SW A write to the clear bit will clear the watchdog counter 1 PCH0 A rising edge on the PRS Channel0 will clear the watchdog counter 29 27 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 26 24 WIN...

Page 411: ...CORECLK HFCORECLK 11 8 PERSEL 0xF RW Watchdog Timeout Period Select Select watchdog timeout period Value Description 0 Timeout period of 9 watchdog clock cycles 1 Timeout period of 17 watchdog clock cycles 2 Timeout period of 33 watchdog clock cycles 3 Timeout period of 65 watchdog clock cycles 4 Timeout period of 129 watchdog clock cycles 5 Timeout period of 257 watchdog clock cycles 6 Timeout pe...

Page 412: ...on 0 EM4 can be entered by software See EMU for detailed description 1 EM4 cannot be entered by software 4 LOCK 0 RW Configuration Lock Set to lock the watchdog configuration This bit can only be cleared by reset Value Description 0 Watchdog configuration can be changed 1 Watchdog configuration cannot be changed 3 EM3RUN 0 RW Energy Mode 3 Run Enable Set to keep watchdog running in EM3 Value Descr...

Page 413: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access W1 Name CLEAR Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 CLEAR 0 W1 Watchdog Timer Clear Clear watchdog timer The bit must be written 4 watchdog cycles before the timeout Value Mode Description 0 UNCHANGED Watchdog timer is unchanged 1 C...

Page 414: ...ite bits to 0 More information in 1 2 Conven tions 3 PCH1_PRSCTRL 0 R PCH1_PRSCTRL Register Busy Set when the value written to PCH1_PRSCTRL is being synchronized 2 PCH0_PRSCTRL 0 R PCH0_PRSCTRL Register Busy Set when the value written to PCH0_PRSCTRL is being synchronized 1 CMD 0 R CMD Register Busy Set when the value written to CMD is being synchronized 0 CTRL 0 R CTRL Register Busy Set when the ...

Page 415: ...Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 0 PRSSEL 0x0 RW PRS Channel PRS Select These bits select the PRS input for the PRS channel Value Mode Description 0 PRSCH0 PRS Channel 0 selected as input 1 PRSCH1 PRS Channel 1 selected as input 2 PRSCH2 PRS Channel 2 selected as input 3 PRSCH3 PRS Channel 3 selected as input 4 PRSCH...

Page 416: ...ing Interrupt Flag Set when a WDOG clear happens before a prs event has been detected on PRS channel one 3 PEM0 0 R PRS Channel Zero Event Missing Interrupt Flag Set when a WDOG clear happens before a prs event has been detected on PRS channel zero 2 WIN 0 R WDOG Window Interrupt Flag Set when a WDOG clear happens below the window limit value 1 WARN 0 R WDOG Warning Timeout Interrupt Flag Set when...

Page 417: ...ays write bits to 0 More information in 1 2 Conven tions 4 PEM1 0 W1 Set PEM1 Interrupt Flag Write 1 to set the PEM1 interrupt flag 3 PEM0 0 W1 Set PEM0 Interrupt Flag Write 1 to set the PEM0 interrupt flag 2 WIN 0 W1 Set WIN Interrupt Flag Write 1 to set the WIN interrupt flag 1 WARN 0 W1 Set WARN Interrupt Flag Write 1 to set the WARN interrupt flag 0 TOUT 0 W1 Set TOUT Interrupt Flag Write 1 to...

Page 418: ... PEM0 interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 2 WIN 0 R W1 Clear WIN Interrupt Flag Write 1 to clear the WIN interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 1 WARN 0 R W1 Clear WARN Interrupt Flag Write 1 t...

Page 419: ...ture devices always write bits to 0 More information in 1 2 Conven tions 4 PEM1 0 RW PEM1 Interrupt Enable Enable disable the PEM1 interrupt 3 PEM0 0 RW PEM0 Interrupt Enable Enable disable the PEM0 interrupt 2 WIN 0 RW WIN Interrupt Enable Enable disable the WIN interrupt 1 WARN 0 RW WARN Interrupt Enable Enable disable the WARN interrupt 0 TOUT 0 RW TOUT Interrupt Enable Enable disable the TOUT ...

Page 420: ...rk allowing direct communication between different peripheral modules without involving the CPU Peripheral modules which send out Reflex signals are called producers The PRS routes these Reflex signals through Reflex channels to consumer peripherals which perform actions depending on the Reflex signals received The format for the Reflex signals is not given but edge triggers and other functionalit...

Page 421: ...OR ed with the selected input from the producers to form the output signal sent to the consumers listening to the channel For example when SWLEVEL n is set if a producer produces a signal of 1 this will cause a channel output of 0 15 3 1 1 Operational Mode Reflex channels can operate in two modes synchronous or asynchronous In synchronous mode Reflex signals are clocked on the HFCLK and can be use...

Page 422: ...PRS channel output OR ed with the previous PRS channel output and inverted This is shown in Figure 15 1 PRS Overview on page 421 The order of the functions is important If OR and AND are enabled at the same time AND is applied first and then OR Note that the previous and next channel options wrap around Using the ORPREV option on the first PRS channel OR s with the output of the last PRS channel L...

Page 423: ...ure Channel Pulse Level Alternate Input for DTI Available only in specific WTIMERs See data sheet for details Level Alternate Input for DTI Fault 0 Available only in specific WTIMERs See data sheet for details Level Alternate Input for DTI Fault 1 Available only in specific WTIMERs See data sheet for details Level USART RX TX Trigger Pulse Alternate Input for IrDA Level Alternate Input for RX Leve...

Page 424: ...the MCU periodically every time letting the MCU pass through a WFE instruction in its program This can help in performance critical sections where timing is known and the goal is to wait for an event then execute some code then wait for an event then execute some code and so on 15 3 5 DMA Request on PRS Up to two independent DMA requests can be generated by the PRS The PRS signals triggering the D...

Page 425: ...ds to be fetched either by the CPU or DMA PRS TIMER0 ADC0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 Start single conv Overflow Figure 15 3 TIMER0 Overflow Starting ADC0 Single Conversions Through PRS Channel 5 15 4 Register Map The offset register address is relative to the registers base address Offset Name Type Description 0x000 PRS_SWPULSE W1 Software Pulse Register 0x004 PRS_SWLEVEL RW Software Level Re...

Page 426: ...ion See bit 0 9 CH9PULSE 0 W1 Channel 9 Pulse Generation See bit 0 8 CH8PULSE 0 W1 Channel 8 Pulse Generation See bit 0 7 CH7PULSE 0 W1 Channel 7 Pulse Generation See bit 0 6 CH6PULSE 0 W1 Channel 6 Pulse Generation See bit 0 5 CH5PULSE 0 W1 Channel 5 Pulse Generation See bit 0 4 CH4PULSE 0 W1 Channel 4 Pulse Generation See bit 0 3 CH3PULSE 0 W1 Channel 3 Pulse Generation See bit 0 2 CH2PULSE 0 W1...

Page 427: ... Software Level See bit 0 9 CH9LEVEL 0 RW Channel 9 Software Level See bit 0 8 CH8LEVEL 0 RW Channel 8 Software Level See bit 0 7 CH7LEVEL 0 RW Channel 7 Software Level See bit 0 6 CH6LEVEL 0 RW Channel 6 Software Level See bit 0 5 CH5LEVEL 0 RW Channel 5 Software Level See bit 0 4 CH4LEVEL 0 RW Channel 4 Software Level See bit 0 3 CH3LEVEL 0 RW Channel 3 Software Level See bit 0 2 CH2LEVEL 0 RW C...

Page 428: ...ble When set GPIO output from PRS channel 9 is enabled 8 CH8PEN 0 RW CH8 Pin Enable When set GPIO output from PRS channel 8 is enabled 7 CH7PEN 0 RW CH7 Pin Enable When set GPIO output from PRS channel 7 is enabled 6 CH6PEN 0 RW CH6 Pin Enable When set GPIO output from PRS channel 6 is enabled 5 CH5PEN 0 RW CH5 Pin Enable When set GPIO output from PRS channel 5 is enabled 4 CH4PEN 0 RW CH4 Pin Ena...

Page 429: ...e Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More informati...

Page 430: ...5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 0 CH0LOC 0x00 RW I O Location Decides the location of the channel I O pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LO...

Page 431: ...Bit Name Reset Access Description Reference Manual PRS Peripheral Reflex System silabs com Building a more connected world Rev 1 1 431 ...

Page 432: ...n Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 16 CH6LOC 0x00 RW I O Location Decides the location ...

Page 433: ...ocation of the channel I O pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 0 CH4LOC 0x00 RW I O Location Decides the location of the channel I O pin Value Mode Description 0 LO...

Page 434: ... LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 16 CH10LOC 0x00 RW I O Location Decides the location of the channel I O pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 ...

Page 435: ...6 Location 16 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 0 CH8LOC 0x00 RW I O Location Decides the location of the channel I O pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 L...

Page 436: ...e Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 selected 11 PRSCH11 PRS Channel 11 ...

Page 437: ...S PRSREQ0 Value Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 selected 11 PRSCH11 P...

Page 438: ...S PRSREQ1 Value Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 selected 11 PRSCH11 P...

Page 439: ...bit 0 9 CH9VAL 0 R Channel 9 Current Value See bit 0 8 CH8VAL 0 R Channel 8 Current Value See bit 0 7 CH7VAL 0 R Channel 7 Current Value See bit 0 6 CH6VAL 0 R Channel 6 Current Value See bit 0 5 CH5VAL 0 R Channel 5 Current Value See bit 0 4 CH4VAL 0 R Channel 4 Current Value See bit 0 3 CH3VAL 0 R Channel 3 Current Value See bit 0 2 CH2VAL 0 R Channel 2 Current Value See bit 0 1 CH1VAL 0 R Chann...

Page 440: ...tput is OR ed with the previous channel output 26 INV 0 RW Invert Channel If set channel output is inverted 25 STRETCH 0 RW Stretch Channel Output If set stretches channel output to ensure that the target clock domain sees it 24 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 20 EDSEL 0x0 RW Edge Detect Select Select edge detec...

Page 441: ... Energy Timer 0 0b0001111 PCNT0 Pulse Counter 0 0b0010010 CMU Clock Management Unit 0b0011000 VDAC0 Digital to Analog Converter 0 0b0011010 CRYOTIMER CryoTimer 0b0110000 USART0 Universal Synchronous Asynchronous Receiver Transmitter 0 0b0110001 USART1 Universal Synchronous Asynchronous Receiver Transmitter 1 0b0111100 TIMER0 Timer 0 0b0111101 TIMER1 Timer 1 0b0111110 WTIMER0 Wide Timer 0 0b1000011...

Page 442: ... 0b001 ADC0SCAN ADC scan conversion done ADC0SCAN Asynchronous SOURCESEL 0b0000111 LESENSEL 0b000 LESENSESCANRES0 LESENSE SCANRES register bit 0 LESENSESCANRES0 Asynchro nous 0b001 LESENSESCANRES1 LESENSE SCANRES register bit 1 LESENSESCANRES1 Asynchro nous 0b010 LESENSESCANRES2 LESENSE SCANRES register bit 2 LESENSESCANRES2 Asynchro nous 0b011 LESENSESCANRES3 LESENSE SCANRES register bit 3 LESENS...

Page 443: ... LESENSE 0b000 LESENSEMEASACT LESENSE Measurement active LESENSEMEASACT Asynchronous SOURCESEL 0b0001011 RTCC 0b001 RTCCCCV0 RTCC Compare 0 RTCCCCV0 Asynchronous 0b010 RTCCCCV1 RTCC Compare 1 RTCCCCV1 Asynchronous 0b011 RTCCCCV2 RTCC Compare 2 RTCCCCV2 Asynchronous SOURCESEL 0b0001100 GPIOL 0b000 GPIOPIN0 GPIO pin 0 GPIOPIN0 Asynchronous 0b001 GPIOPIN1 GPIO pin 1 GPIOPIN1 Asynchronous 0b010 GPIOPI...

Page 444: ...UTMODE mode in OPACTRL VDAC0OPA0 Asynchronous 0b011 VDAC0OPA1 OPA1 warmedup or outputvalid based on OPA1PRSOUTMODE mode in OPACTRL VDAC0OPA1 Asynchronous SOURCESEL 0b0011010 CRYOTIMER 0b000 CRYOTIMERPERIOD CRYOTIMER Output CRYOTIMERPERIOD Asynchronous SOURCESEL 0b0110000 USART0 0b000 USART0IRTX USART 0 IRDA out USART0IRTX 0b001 USART0TXC USART 0 TX complete USART0TXC 0b010 USART0RXDATAV USART 0 RX...

Page 445: ...Capture 2 TIMER1CC2 0b101 TIMER1CC3 Timer 1 Compare Capture 3 TIMER1CC3 SOURCESEL 0b0111110 WTIMER0 0b000 WTIMER0UF Timer 2 Underflow WTIMER0UF 0b001 WTIMER0OF Timer 2 Overflow WTIMER0OF 0b010 WTIMER0CC0 Timer 2 Compare Capture 0 WTIMER0CC0 0b011 WTIMER0CC1 Timer 2 Compare Capture 1 WTIMER0CC1 0b100 WTIMER0CC2 Timer 2 Compare Capture 2 WTIMER0CC2 SOURCESEL 0b1000011 CM4 0b000 CM4TXEV CM4TXEV 0b001...

Page 446: ...code quadrature encoded inputs in EM0 Active down to EM3 Stop It can run from the internal LFACLK while counting pulses on the PCNTn_S0IN pin Or alternately the PCNTn_S0IN pin may be used as an external clock source that runs both the PCNT counter and register access 16 2 Features 16 bit counter with reload register Auxiliary counter for counting a single direction Single input oversampling up dow...

Page 447: ...IN input may be inverted so that falling edges are counted by setting the EDGE bit in the PCNTn_CTRL register If S1CDIR in the PCNTn_CTRL register is cleared PCNTn_S0IN is the only observed input in this mode The PCNTn_S0IN input is sampled by the LFACLK and the number of detected positive or negative edges on PCNTn_S0IN appears in PCNTn_CNT The counter may be configured to count down by setting t...

Page 448: ...nchronous quadrature decoding The externally clocked mode supports 1X quadrature decoding whereas the oversampling mode supports 1X 2X and 4X quadrature decoding These modes are described in detail in 16 3 1 4 Externally Clocked Quadrature Decoder Mode and 16 3 1 5 Oversampling Quadrature Decoder Mode Reference Manual PCNT Pulse Counter silabs com Building a more connected world Rev 1 1 448 ...

Page 449: ...1 Figure 16 2 PCNT Quadrature Coding If PCNTn_S0IN leads PCNTn_S1IN in phase the direction is clockwise and if it lags in phase the direction is counter clockwise De fault behavior is illustrated by Figure 16 2 PCNT Quadrature Coding on page 449 The counter direction may be read from the DIR bit in the PCNTn_STATUS register Additionally the DIRCNG interrupt in the PCNTn_IF register is generated wh...

Page 450: ...puts Control Status S1IN posedge S1IN negedge Count Enable CNTDIR status bit 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 0 Note PCNTn_S1IN is sampled on both edges of PCNTn_S0IN Reference Manual PCNT Pulse Counter silabs com Building a more connected world Rev 1 1 450 ...

Page 451: ... both inputs PCNTn_S0IN and PCNTn_S1IN Table 16 2 PCNT OVSQUAD 1X 2X and 4X Mode Counter Control Function on page 451 outlines the increment or decrement of the counter based on the Quadrature Mode selected Note The decoding behavior of OVSQUAD1X mode is slightly different compared to EXTCLKQUAD mode also 1X mode In the EX TCLKQUAD mode the counter is updated only on the posedge of S0IN input Howe...

Page 452: ...interrupt in the PCNTn_IF is generated when the direction change is detected When a change is detected the DIR bit in the PCNTn_STATUS register must be read to determine the new direction In the oversampling quadrature decoder modes the maximum input toggle frequency supported is 8KHz For frequencies of 8KHz and higher incorrect decoding occurs The different decoding modes and the counter updates ...

Page 453: ...ed if the current and previous state transition of the rotation are in the same direction These state transitions are quadrature decoder mode specific The highlighted state transitions in Figure 16 3 PCNT State Transitions for Different Oversampling Quadrature Decoder Modes on page 452 are the ones considered for the different quadrature decoder modes Figure 16 7 PCNT Oversampling Quadrature Decod...

Page 454: ...re it might overflow or under flow removing the problem Figure 16 8 PCNT Hysteresis behavior of Counter on page 454 illustrates the hysteresis behavior TOP TOP 2 Overflow wrap Overflow continue cnt Underflow warp underflow continue cnt COUNTER MIN VAL MAX VAL Overflow continue cnt underflow continue cnt Figure 16 8 PCNT Hysteresis behavior of Counter Given a starting value of 0 for the counter the...

Page 455: ...ovement The value of the auxili ary counter can be read from the PCNTn_AUXCNT register Overflows on the auxiliary counter happen when the auxiliary counter passes the top value of the pulse counter configured in PCNTn_TOP In that event the AUXOF interrupt flag is set and the auxiliary counter wraps to 0 As the auxiliary counter the main counter can be configured to count only on certain events Thi...

Page 456: ...upt is set and the PRS output from the pulse counter is set The PRS output will remain set until the next compare and clear event Triggered compare and clear is intended for use when the pulse counter is configured to count up In this mode PCNTn_CNT will not wrap to 0 when hitting PCNTn_TOP it will keep counting In addition the counter will not overflow it will rather stop counting just setting th...

Page 457: ...ernal clock The clock selection is configured by the PCNT0CLKSEL bit in the CMU_PCNTCTRL in the Clock Management Unit CMU 11 CMU Clock Management Unit The de fault clock source is the LFACLK This PCNT module may also use PCNTn_S0IN as an external clock to clock the counter EXTCLKSINGLE mode and to sample PCNTn_S1IN EXTCLKQUAD mode Setup hold and max frequency constraints for PCNTn_S0IN and PCNTn_S...

Page 458: ... PRS output and the CNT DIR PRS output The TCC PRS is generated on compare match of TCC event The CNT OF UF combined PRS is generated when the counter overflow or under flows The CNT DIR PRS is a level PRS and indicates the current direction of count of counter CNT Note S0PRSEN S1PRSEN S0PRSSEL S1PRSSEL should only be altered when RSTEN in PCNTn_CTRL is set 16 3 10 Interrupts The interrupt generat...

Page 459: ... Direction Change Interrupt DIRCNG Generation on page 459 Standard async handshake interface PCNTn_S0IN PCNTn_S1IN Interrupt X X Invalid pulse generated when the shaft changes direction n 1 n 2 n 3 n 2 PCNTn_CNT n Delay from the shaft physically changed direction until the counter direction is changed and the interrupt is generated Figure 16 13 PCNT Direction Change Interrupt DIRCNG Generation Ref...

Page 460: ... both PCNTs are in sync with each other Configure PCNT0 registers eg PCNT0_INPUT PCNT0_CTRL PCNT0_OVSCFG etc Wait for PCNT0_SYCNBUSY to be cleared to ensure the registers are synchronized to the asynchronous clock domain Hold PCNT0 in sw reset by setting PCNT0_CTRL_RSTEN Configure PCNT1_CTRL to EXTCLKSINLE mode with S1CDIR and CNTDIR bit set Configure INPUT to accept prs_ufof and prs_dir of PCNT0 ...

Page 461: ...CNTn_IF R Interrupt Flag Register 0x01C PCNTn_IFS W1 Interrupt Flag Set Register 0x020 PCNTn_IFC R W1 Interrupt Flag Clear Register 0x024 PCNTn_IEN RW Interrupt Enable Register 0x02C PCNTn_ROUTELOC0 RW I O Routing Location Register 0x040 PCNTn_FREEZE RW Freeze Register 0x044 PCNTn_SYNCBUSY R Synchronization Busy Register 0x064 PCNTn_AUXCNT R Auxiliary Counter Value Register 0x068 PCNTn_INPUT RW PC...

Page 462: ...To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 29 26 TCCPRSSEL 0x0 RW TCC PRS Channel Select Select PRS channel used as compare and clear trigger Value Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS C...

Page 463: ...med on every 4th LFA cycle 3 DIV8 Compare and clear performed on every 8th LFA cycle 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 17 16 TCCMODE 0x0 RW Sets the Mode for Triggered Compare and Clear Selects whether compare and clear should be triggered on each LFA clock or from PRS Value Mode Description 0 DISABLED Triggered comp...

Page 464: ...events 2 DOWN Only counts down on down count events 3 NONE Never counts 9 S1CDIR 0 RW Count Direction Determined By S1 S1 gives the direction of counting when in the OVSSINGLE or EXTCLKSINGLE modes When S1 is high the count direc tion is given by CNTDIR and when S1 is low the count direction is the opposite 8 HYST 0 RW Enable Hysteresis When hysteresis is enabled the PCNT will always overflow and ...

Page 465: ...T 0 RW Enable Digital Pulse Width Filter The filter passes all high and low periods that are at least FILTLEN 5 clock cycles wide This filter is only available in OVSSINGLE OVSQUAD1X 4X modes 2 0 MODE 0x0 RW Mode Select Selects the mode of operation The corresponding clock source must be selected from the CMU Value Mode Description 0 DISABLE The module is disabled 1 OVSSINGLE Single input LFACLK o...

Page 466: ...into TOP 0 LCNTIM 0 W1 Load CNT Immediately Load PCNTn_TOP into PCNTn_CNT on the next counter clock cycle 16 5 3 PCNTn_STATUS Status Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name DIR Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More ...

Page 467: ...Tn_TOP Top Value Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00FF Access R Name TOP Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 TOP 0x00FF R Counter Top Value When counting down this value is reloaded ...

Page 468: ... 2 1 0 Reset 0 0 0 0 0 0 Access R R R R R R Name OQSTERR TCC AUXOF DIRCNG OF UF Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 OQSTERR 0 R Oversampling Quadrature State Error Interrupt Set in the Oversampling Quadrature Mode when incorrect state transition occurs 4 TCC 0 R Triggered Compare I...

Page 469: ...on in 1 2 Conven tions 5 OQSTERR 0 W1 Set OQSTERR Interrupt Flag Write 1 to set the OQSTERR interrupt flag 4 TCC 0 W1 Set TCC Interrupt Flag Write 1 to set the TCC interrupt flag 3 AUXOF 0 W1 Set AUXOF Interrupt Flag Write 1 to set the AUXOF interrupt flag 2 DIRCNG 0 W1 Set DIRCNG Interrupt Flag Write 1 to set the DIRCNG interrupt flag 1 OF 0 W1 Set OF Interrupt Flag Write 1 to set the OF interrup...

Page 470: ...pt flags This feature must be enabled globally in MSC 3 AUXOF 0 R W1 Clear AUXOF Interrupt Flag Write 1 to clear the AUXOF interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 2 DIRCNG 0 R W1 Clear DIRCNG Interrupt Flag Write 1 to clear the DIRCNG interrupt flag Reading returns the value of the IF and clears th...

Page 471: ...s to 0 More information in 1 2 Conven tions 5 OQSTERR 0 RW OQSTERR Interrupt Enable Enable disable the OQSTERR interrupt 4 TCC 0 RW TCC Interrupt Enable Enable disable the TCC interrupt 3 AUXOF 0 RW AUXOF Interrupt Enable Enable disable the AUXOF interrupt 2 DIRCNG 0 RW DIRCNG Interrupt Enable Enable disable the DIRCNG interrupt 1 OF 0 RW OF Interrupt Enable Enable disable the OF interrupt 0 UF 0 ...

Page 472: ...es the location of the PCNT S1IN input pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC1...

Page 473: ... of the PCNT S0IN input pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 1...

Page 474: ...eset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 REGFREEZE 0 RW Register Update Freeze When set the update of the PCNT clock domain is postponed until this bit is cleared Use this bit to update several regis ters simultaneously Value Mode Description 0 UPDATE Each write access to a PCNT register is updat...

Page 475: ...OPB is being synchronized 1 CMD 0 R CMD Register Busy Set when the value written to CMD is being synchronized 0 CTRL 0 R CTRL Register Busy Set when the value written to CTRL is being synchronized 16 5 14 PCNTn_AUXCNT Auxiliary Counter Value Register Offset Bit Position 0x064 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access R Name AUXCNT Bit...

Page 476: ...PRS channel as input to S1IN Value Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 se...

Page 477: ... 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x00 Access RW RW Name FLUTTERRM FILTLEN Bit Name Reset Access Description 31 13 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 FLUTTERRM 0 RW Flutter Remove When set removes flutter from Quaddecoder inputs S0IN and S1IN Available only in ...

Page 478: ... the way from 10 kbit s up to 1 Mbit s Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant sys tem The interface provided to software by the I2C module allows precise control of the transmission process and highly automated transfers Automatic recognition of slave addresses is provided in all energy modes except EM4 17 2 Features True multi master capabil...

Page 479: ...mit Shift Register I2Cn_SDA Receive Buffer 2 level FIFO Receive Shift Register I2 C Control and Status Peripheral Bus I2Cn_SCL Pin Ctrl Symbol Generator Receive Controller Clock Generator Address Recognizer Figure 17 1 I2C Overview Reference Manual I2C Inter Integrated Circuit Interface silabs com Building a more connected world Rev 1 1 479 ...

Page 480: ...on the bus including other masters Both the bus lines are open drain The maximum value of the pull up resistor can be calculated as a function of the maximal rise time tr for the given bus speed and the estimated bus capacitance Cb as shown in Figure 17 3 I2C Pull up Resistor Equation on page 480 Rp max tr 0 8473 x Cb Figure 17 3 I2C Pull up Resistor Equation The maximal rise times for 100 kHz 400...

Page 481: ...OP condition Figure 17 4 I2C START and STOP Conditions The START and STOP conditions are easily identifiable bus events as they are the only conditions on the bus where a transition is allowed on SDA while SCL is high During the actual data transmission SDA is only allowed to change while SCL is low and must be stable while SCL is high One bit is transferred per clock pulse on the I2C bus as shown...

Page 482: ...tes in a bus transfer is unrestricted The master ends the transmission after a N ACK by sending a STOP condition on the bus After a STOP condition any master wishing to initiate a transfer on the bus can try to gain control of it If the current master wishes to make another transfer immediately after the current it can start a new transfer directly by transmitting a repeated START condition Sr ins...

Page 483: ...rite to the slave The second byte contains the eight least signifi cant bits of the slave address When a slave receives a 10 bit address it must acknowledge both the address bytes if they match the address of the slave When performing a master transmitter operation the master transmits the two address bytes and then the remaining data as shown in Figure 17 9 I2C Master Transmitter Slave Receiver w...

Page 484: ...ures should be taken if while the slave is enabled the user cannot guarantee that an address match will not occur at the exact time of slave disable or slave configuration change Worst case consequences for an address match while disabling slave or changing configuration is that the slave may end up in an undefined state To reset the slave back to a known state the EN bit in I2Cn_CTRL must be rese...

Page 485: ... byte has been transmitted a new byte is loaded into the shift register if available in the transmit buffer If the transmit buffer is empty then the shift register also remains empty The TXC flag in I2Cn_STA TUS and the TXC interrupt flags in I2Cn_IF are then set signaling that the transmit shift register is out of data TXC is cleared when new data becomes available but the TXC interrupt flag must...

Page 486: ...e more byte The data can be fetched from the buffer in two ways I2Cn_RXDATA gives access to the received byte if two bytes are received then the one received first is fetched first I2Cn_RXDOUBLE makes it possible to read the two received bytes simultaneously If an attempt is made to read more bytes from the buffer than available the RXUF interrupt flag in I2Cn_IF is set to signal the underflow and...

Page 487: ...its it immediately but if the buffer is empty the master holds the I2C bus while waiting for software to write the address to the transmit buffer After the address has been transmitted a sequence of bytes can be read from or written to the slave depending on the value of the R W bit bit 0 in the address byte If the bit was cleared the master has entered a master transmitter role where it now trans...

Page 488: ... transmission proceed Waiting for idle Idle busy 57 B3 9B 0 57 S ADDR R A N ADDR W A N DATA P Sr X Arb lost 1 97 D7 DF 9F A N A N DATA P Sr Arb lost ADDR R Arb lost ADDR match ADDR W Arb lost ADDR match ADDR X Arb lost no match 1 71 Master receiver Master transmitter Arbitration lost Slave transmitter Slave receiver 0 57 1 93 0 1 Bus state event Transmitted by self Received from slave START condit...

Page 489: ...t in I2Cn_CMD PSTOP is set STOP pending in I2Cn_STATUS ABORT 2 Set the ABORT command bit in I2Cn_CMD Never the transmission is abor ted CONT 3 Set the CONT command bit in I2Cn_CMD PCONT is set in I2Cn_STATUS CONT pending NACK 4 Set the NACK command bit in I2Cn_CMD PNACK is set in I2Cn_STATUS NACK pending ACK 5 Set the ACK command bit in I2Cn_CMD AUTOACK is set in I2Cn_CTRL or PACK is set in I2Cn_S...

Page 490: ...tire MCU the I2C bus is assumed to be busy when coming out of a reset and the BUSY flag in I2Cn_STATUS is thus set To be able to carry through master operations on the I2C bus the bus must be idle The bus goes idle when a STOP condition is detected on the bus but on buses with little activity the time before the I2C module de tects that the bus is idle can be significant There are two ways of assu...

Page 491: ... can send a STOP and then a START as soon as possible If the master wishes to make another transfer immediately after the current the preferred way is to start a new transfer directly by transmitting a repeated START instead of a STOP followed by a START This is so because if a STOP is sent out then any master wishing to initiate a transfer on the bus can try to gain control of it If a NACK was re...

Page 492: ...nterrupt flag None 0xD7 Data transmitted ACK received ACK interrupt flag BUSHOLD interrupt flag TXDATA DATA will be sent STOP STOP will be sent Bus will be released START Repeated start condition will be sent STOP START STOP will be sent and the bus released Then a START will be sent when the bus becomes idle 0xDF Data transmitted NACK received NACK BUSHOLD inter rupt flag CONT TXDATA DATA will be...

Page 493: ...oth then the ACK NACK is transmitted and the reception is ended If START in I2Cn_CMD is set alone a repea ted start condition is transmitted after the ACK NACK If STOP in I2Cn_CMD is set a stop condition is sent regardless of whether START is set If START is set in this case it is set as pending As when operating as a master transmitter arbitration can be lost as a master receiver When this happen...

Page 494: ...be re leased ACK NACK START ACK NACK will be sent and then a repeated start condition ACK NACK STOP START ACK NACK will be sent and the bus will be re leased Then a START will be sent when the bus becomes idle Stop received MSTOP interrupt flag None START START will be sent when bus becomes idle Arbitration lost ARBLOST interrupt flag None START START will be sent when bus becomes idle Reference M...

Page 495: ...ransmission Status Bit Description BUSY Set whenever there is activity on the bus Whether or not this module is responsible for the activity cannot be determined by this byte MASTER Set when operating as a master Cleared at all other times TRANSMITTER Set when operating as a transmitter either a master transmitter or a slave transmitter Cleared at all other times BUSHOLD Set when the bus is held b...

Page 496: ...e should be addressed with is defined in the I2Cn_SADDR register In addition to the address a mask must be specified telling the address comparator which bits of an incoming address to compare with the ad dress defined in I2Cn_SADDR The mask is defined in I2Cn_SADDRMASK and for every zero in the mask the corresponding bit in the slave address is treated as a don t care i e the 0 masked bits are ig...

Page 497: ... not standard I2C howev er If the master responds with an ACK it may expect another byte of data and data should be made available in the transmit buffer If data is not available the bus is held until data is available If the response is a NACK however this is an indication of that the master has received enough bytes and wishes to end the transmis sion The slave now automatically goes idle unless...

Page 498: ...ONT TXDATA DATA will be transmitted Stop received SSTOP interrupt flag None The slave goes idle START START will be sent when bus becomes idle Arbitration lost ARBLOST interrupt flag None The slave goes idle START START will be sent when the bus becomes idle Reference Manual I2C Inter Integrated Circuit Interface silabs com Building a more connected world Rev 1 1 498 ...

Page 499: ...her the slave is participating in the transmission or not as long as SLAVE in I2Cn_CTRL is set and a STOP condition is detected If arbitration is lost at any time during transmission the ARBLOST interrupt flag in I2Cn_IF is set the bus is released and the slave goes idle See Table 17 8 I2C Slave Receiver on page 499 for more information Table 17 8 I2C Slave Receiver I2Cn_STATE Description I2Cn_IF ...

Page 500: ... should NACK it When the master is operating as a master transmitter the data bytes will follow after the second address byte When the master is operating as a master receiver however a repeated START condition is sent after the second address byte The address sent after this repeated START is equal to the first of the address bytes transmitted previously but now with the R W byte set and only the...

Page 501: ...ring the transmission of a general call address i e during the transmission of the STOP condition which should never happen during normal operation this is a good indication of SDA lockup Detection of SCL lockups can be done using the timeout functionality defined in 17 3 12 6 Clock Low Timeout 17 3 12 5 Bus Idle Timeout When SCL has been high for a significant amount of time this is a good indica...

Page 502: ... simultaneously to the transmit buffer using the DMA DMA_USEBURSTS needs to be set to 1 for the selected DMA channel This ensures that the transfer is made to the transmit buffer only when both buffer elements are empty For performing a DMA write to the I2Cn_TXDATA register DMA_USEBURSTC needs to be set to 1 for the selected DMA channel This ensures that a DMA transfer is made even when the transm...

Page 503: ...E R a Receive Buffer Double Data Register 0x024 I2Cn_RXDATAP R Receive Buffer Data Peek Register 0x028 I2Cn_RXDOUBLEP R Receive Buffer Double Data Peek Register 0x02C I2Cn_TXDATA W Transmit Buffer Data Register 0x030 I2Cn_TXDOUBLE W Transmit Buffer Double Data Register 0x034 I2Cn_IF R Interrupt Flag Register 0x038 I2Cn_IFS W1 Interrupt Flag Set Register 0x03C I2Cn_IFC R W1 Interrupt Flag Clear Reg...

Page 504: ...d mode at 100 kHz this results in a 50us timeout 2 80PCC Timeout after 80 prescaled clock cycles In standard mode at 100 kHz this results in a 100us timeout 3 160PCC Timeout after 160 prescaled clock cycles In standard mode at 100 kHz this results in a 200us timeout 4 320PCC Timeout after 320 prescaled clock cycles In standard mode at 100 kHz this results in a 400us timeout 5 1024PCC Timeout after...

Page 505: ... a 200us timeout 11 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 9 8 CLHR 0x0 RW Clock Low High Ratio Determines the ratio between the low and high parts of the clock signal generated on SCL as master Value Mode Description 0 STANDARD The ratio between low period and high period counters Nlow Nhigh is 4 4 1 ASYMMETRIC The ratio...

Page 506: ... data is available for transmission Value Description 0 A stop must be sent manually when no more data is to be transmitted 1 The master automatically sends a STOP when no more data is availa ble for transmission 2 AUTOACK 0 RW Automatic Acknowledge Set to enable automatic acknowledges Value Description 0 Software must give one ACK command for each ACK transmitted on the I2C bus 1 Addresses that a...

Page 507: ...When used in combination with STOP a STOP condition is sent as soon as possible before aborting the transmission The stop condition is subject to clock synchronization 4 CONT 0 W1 Continue Transmission Set to continue transmission after a NACK has been received 3 NACK 0 W1 Send NACK Set to transmit a NACK the next time an acknowledge is required 2 ACK 0 W1 Send ACK Set to transmit an ACK the next ...

Page 508: ...smitted or received 6 DATAACK Data ack nack transmitted or received 4 BUSHOLD 0 R Bus Held Set if the bus is currently being held by this I2C module 3 NACKED 0 R Nack Received Set if a NACK was received and STATE is ADDRACK or DATAACK 2 TRANSMITTER 0 R Transmitter Set when operating as a master transmitter or a slave transmitter When cleared the system may be operating as a master receiver a slave...

Page 509: ...ffer Level Indicates the level of the transmit buffer Set when the transmit buffer is empty and cleared when it is full 6 TXC 0 R TX Complete Set when a transmission has completed and no more data is available in the transmit buffer Cleared when a new transmis sion starts 5 PABORT 0 R Pending Abort An abort is pending and will be transmitted as soon as possible 4 PCONT 0 R Pending Continue A conti...

Page 510: ...lave is enabled 17 5 6 I2Cn_SADDR Slave Address Register Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RW Name ADDR Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 1 ADDR 0x00 RW Slave Address Specifies the sla...

Page 511: ... exact address specified by ADDR 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 17 5 8 I2Cn_RXDATA Receive Buffer Data Register Actionable Reads Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access R Name RXDATA Bit Name Reset Access Description 31 8 Rese...

Page 512: ...cess 7 0 RXDATA0 0x00 R RX Data 0 First byte read from buffer Buffer is emptied on read access 17 5 10 I2Cn_RXDATAP Receive Buffer Data Peek Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access R Name RXDATAP Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write ...

Page 513: ...mptied on read access 7 0 RXDATAP0 0x00 R RX Data 0 Peek First byte read from buffer Buffer is not emptied on read access 17 5 12 I2Cn_TXDATA Transmit Buffer Data Register Offset Bit Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access W Name TXDATA Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future ...

Page 514: ...Name TXDATA1 TXDATA0 Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 8 TXDATA1 0x00 W TX Data Second byte to write to buffer 7 0 TXDATA0 0x00 W TX Data First byte to write to buffer Reference Manual I2C Inter Integrated Circuit Interface silabs com Building a more connected world Rev 1 1 514...

Page 515: ...Set on each bus idle timeout The timeout value can be set in the BITO bit field in the I2Cn_CTRL register 13 RXUF 0 R Receive Buffer Underflow Interrupt Flag Set when data is read from the receive buffer through the I2Cn_RXDATA register while the receive buffer is empty It is also set when data is read through the I2Cn_RXDOUBLE while the buffer is not full 12 TXOF 0 R Transmit Buffer Overflow Inte...

Page 516: ...fer Completed Interrupt Flag Set when the transmit shift register becomes empty and there is no more data in the transmit buffer 2 ADDR 0 R Address Interrupt Flag Set when incoming address is accepted i e own address or general call address is received 1 RSTART 0 R Repeated START Condition Interrupt Flag Set when a repeated start condition is detected 0 START 0 R START Condition Interrupt Flag Set...

Page 517: ...rupt Flag Write 1 to set the CLTO interrupt flag 14 BITO 0 W1 Set BITO Interrupt Flag Write 1 to set the BITO interrupt flag 13 RXUF 0 W1 Set RXUF Interrupt Flag Write 1 to set the RXUF interrupt flag 12 TXOF 0 W1 Set TXOF Interrupt Flag Write 1 to set the TXOF interrupt flag 11 BUSHOLD 0 W1 Set BUSHOLD Interrupt Flag Write 1 to set the BUSHOLD interrupt flag 10 BUSERR 0 W1 Set BUSERR Interrupt Fl...

Page 518: ...DR Interrupt Flag Write 1 to set the ADDR interrupt flag 1 RSTART 0 W1 Set RSTART Interrupt Flag Write 1 to set the RSTART interrupt flag 0 START 0 W1 Set START Interrupt Flag Write 1 to set the START interrupt flag Reference Manual I2C Inter Integrated Circuit Interface silabs com Building a more connected world Rev 1 1 518 ...

Page 519: ...value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 14 BITO 0 R W1 Clear BITO Interrupt Flag Write 1 to clear the BITO interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 13 RXUF 0 R W1 Clear RXUF Interrupt Flag Write 1 to clear the RXUF interrupt flag Read...

Page 520: ...2 Conven tions 3 TXC 0 R W1 Clear TXC Interrupt Flag Write 1 to clear the TXC interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 2 ADDR 0 R W1 Clear ADDR Interrupt Flag Write 1 to clear the ADDR interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must b...

Page 521: ...TOP 0 RW SSTOP Interrupt Enable Enable disable the SSTOP interrupt 15 CLTO 0 RW CLTO Interrupt Enable Enable disable the CLTO interrupt 14 BITO 0 RW BITO Interrupt Enable Enable disable the BITO interrupt 13 RXUF 0 RW RXUF Interrupt Enable Enable disable the RXUF interrupt 12 TXOF 0 RW TXOF Interrupt Enable Enable disable the TXOF interrupt 11 BUSHOLD 0 RW BUSHOLD Interrupt Enable Enable disable t...

Page 522: ...e the START interrupt 17 5 18 I2Cn_ROUTEPEN I O Routing Pin Enable Register Offset Bit Position 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access RW RW Name SCLPEN SDAPEN Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 SCLPEN 0 RW SCL ...

Page 523: ...ocation of the I2C SCL pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18...

Page 524: ...e I2C SDA pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Locati...

Page 525: ...cation 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Location 28 29 LOC29 Location 29 30 LOC30 Location 30 31 LOC31 Location 31 Reference Manual I2C Inter Integrated Circuit Interface silabs com Building a more connected world Rev 1 1 525 ...

Page 526: ...lti processor mode allows the USART to remain idle when not addressed Triple buffering and DMA sup port makes high data rates possible with minimal CPU intervention and it is possible to transmit and receive large frames while the MCU remains in EM1 Sleep 18 1 Introduction The Universal Synchronous Asynchronous serial Receiver and Transmitter USART is a very flexible serial I O module It supports ...

Page 527: ...processor mode Synchronous mode supports All 4 SPI clock polarity phase configurations Master and slave mode Data can be transmitted LSB first or MSB first Configurable number of data bits 4 16 plus the parity bit if enabled HW parity bit generation and check Configurable number of stop bits in asynchronous mode 0 5 1 1 5 2 HW collision detection Multi processor mode IrDA modulator SmartCard ISO78...

Page 528: ...fer 2 level FIFO TX Shift Register U S n_TX RX Buffer 2 level FIFO RX Shift Register UART Control and status Peripheral Bus Baud rate generator USn_CLK Pin ctrl USn_CS U S n_RX IrDA modulator IrDA demodulator RXBLOCK PRS inputs USn_CTS USn_RTS TIMECMP2 Timer TIMECMP1 TIMECMP0 Auto Baud Detection Figure 18 1 USART Overview Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitt...

Page 529: ... page 529 Full duplex and half duplex communication is supported in both asynchronous and synchronous mode Table 18 1 USART Asynchronous Vs Synchronous Mode SYNC Communication Mode Supported Protocols 0 Asynchronous RS 232 RS 485 w external driver IrDA ISO 7816 1 Synchronous SPI MicroWire 3 wire Table 18 2 USART Pin Usage on page 529 explains the functionality of the different USART pins when the ...

Page 530: ...e Format The number of data bits in a frame is set by DATABITS in USARTn_FRAME see Table 18 3 USART Data Bits on page 530 and the number of stop bits is set by STOPBITS in USARTn_FRAME see Table 18 4 USART Stop Bits on page 530 Whether or not a parity bit should be included and whether it should be even or odd is defined by PARITY also in USARTn_FRAME For communication to be possible all parties o...

Page 531: ...d Handling When parity bits are enabled hardware automatically calculates and inserts any parity bits into outgoing frames and verifies the re ceived parity bits in incoming frames This is true for both asynchronous and synchronous modes even though it is mostly used in asynchronous communication The possible parity modes are defined in Table 18 5 USART Parity Bits on page 531 When even pari ty is...

Page 532: ...ck cycle Given a desired baud rate brdesired the clock divider USARTn_CLKDIV can be calculated by using Figure 18 4 USART Desired Baud Rate on page 532 USARTn_CLKDIV 256 x fHFPERCLK oversample x brdesired 1 Figure 18 4 USART Desired Baud Rate Table 18 7 USART Baud Rates 4MHz Peripheral Clock With 20 Bit CLKDIV on page 532 shows a set of desired baud rates and how accurately the USART is able to ge...

Page 533: ...iated by writing data to the transmit buffer using one of the methods described in 18 3 2 6 Trans mit Buffer Operation When the transmission shift register is empty and ready for new data a frame from the transmit buffer is loaded into the shift register and if the transmitter is enabled transmission begins When the frame has been transmitted a new frame is loa ded into the shift register if avail...

Page 534: ...uffer Operation When writing more frames to the transmit buffer than there is free space for the TXOF interrupt flag in USARTn_IF will be set indicat ing the overflow The data already in the transmit buffer is preserved in this case and no data is written In addition to the interrupt flag TXC in USARTn_IF and status flag TXC in USARTn_STATUS which are set when the transmission is complete TXBL in ...

Page 535: ...tting AUTOTRI If AUTOTRI is set TXTRI is always read as 0 Note When in SmartCard mode with repeat enabled none of the actions except generate break will be performed until the frame is trans mitted without failure Generation of a break in SmartCard mode with repeat enabled will cause the USART to detect a NACK on every frame 18 3 2 8 Data Reception Data reception is enabled by setting RXEN in USAR...

Page 536: ...ARTn_RXDOUBLEX pull two frames out of the buffer If an attempt is done to read more frames from the buffer than what is available the RXUF interrupt flag in USARTn_IF is set to signal the underflow and the data read from the buffer is undefined Frames can be read from the receive buffer without removing the data by using USARTn_RXDATAXP and USARTn_RXDOUBLEXP USARTn_RXDATAXP gives access the first ...

Page 537: ...re data is loaded into the receive buffer even when RXBLOCK is set This is when an ad dress frame is received when operating in multi processor mode See 18 3 2 20 Multi Processor Mode for more information Frames received containing framing or parity errors will not result in the FERR and PERR interrupt flags in USARTn_IF being set while RXBLOCK in USARTn_STATUS is set Hardware recognition is not a...

Page 538: ...8 Majority vote can be disabled by setting MVDIS in USARTn_CTRL If the value of the start bit is found to be high the reception of the frame is aborted filtering out false start bits possibly generated by noise on the input 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 Idle Start bit Bit 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 13 7 12 OVS 0 OVS 1 0 1 2 3 4 5 6 1 OVS 2 1 2 3 4 1 2 3 4 ...

Page 539: ...RXDATAX USARTn_RXDATAXP USARTn_RXDOUBLEX or USARTn_RXDOUBLEXP registers If ERRSTX in USARTn_CTRL is set the transmitter is disabled on received parity and framing errors If ERRSRX in USARTn_CTRL is set the receiver is disabled on parity and framing errors 18 3 2 13 Framing Error and Break Detection A framing error is the result of an asynchronous frame where the stop bit was sampled to a value of ...

Page 540: ... output again Whether or not the output is tristated at a given time can be read from TXTRI in USARTn_STATUS If TXTRI is set when transmitting data the data is shifted out of the shift register but is not put out on U S n_TX When operating a half duplex data bus it is common to have a bus master which first transmits a request to one of the bus slaves then receives a reply In this case the frame t...

Page 541: ...1 or TCMPVAL2 for the TX sequencer USn_CS is immediately deasserted when the transmitter becomes disabled Figure 18 10 USART Half Duplex Communication with External Driver on page 541 shows an example configuration where USn_CS is used to automatically enable and disable an external driver USART RX TX µC CS Figure 18 10 USART Half Duplex Communication with External Driver The USn_CS output is acti...

Page 542: ...en writing two bytes at a time using USARTn_TXDOUBLE Write CTRL Write CTRL Write CTRL TX buffer element 1 TX buffer element 0 Shift register Peripheral Bus 0 1 2 3 4 5 6 7 0 1 2 0 1 2 0 1 2 3 4 5 6 7 Figure 18 11 USART Transmission of Large Frames As shown in Figure 18 11 USART Transmission of Large Frames on page 542 frame transmission control bits are taken from the sec ond element in FIFO The t...

Page 543: ...gardless of the value of RXBLOCK in USARTn_STATUS Multi processor mode is enabled by setting MPM in USARTn_CTRL and the value of the 9th bit in address frames can be set in MPAB Note that the receiver must be enabled for address frames to be detected The receiver can be blocked however preventing data from being loaded into the receive buffer while looking for address frames Figure 18 14 USART Mul...

Page 544: ...n USARTn_CTRL must be set and the receiver enabled The data sampled by the receiv er is then continuously compared with the data output by the transmitter If they differ the CCF interrupt flag in USARTn_IF is set The collision check includes all bits of the transmitted frames The CCF interrupt flag is set once for each bit sampled by the receiver that differs from the bit output by the transmitter...

Page 545: ...e Figure 18 16 USART ISO 7816 Data Frame With Error on page 545 It holds the line low for one bit period before it releases the line In this case the guard time is exten ded by one bit period before a new transmission can start resulting in a total of 3 stop bits S 0 1 2 3 4 5 6 7 P Stop Start or idle Stop or idle ISO 7816 Frame with error Stop NAK Figure 18 16 USART ISO 7816 Data Frame With Error...

Page 546: ... detection can be performed 18 3 3 1 Frame Format The frames used in synchronous mode need no start and stop bits since a single clock is available to all parts participating in the com munication Parity bits cannot be used in synchronous mode The USART supports frame lengths of 4 to 16 bits per frame Larger frames can be simulated by transmitting multiple smaller frames i e a 22 bit frame can be ...

Page 547: ... on the trailing edge If CLKPHA is set however data is set up on the leading clock edge and sampled on the trailing edge In addition to this the polarity of the clock signal can be changed by setting CLKPOL in USARTn_CTRL which also defines the idle state of the clock This results in four different modes which are summarized in Table 18 8 USART SPI Modes on page 547 Figure 18 20 USART SPI Timing o...

Page 548: ...goes to slave mode 18 3 3 5 AUTOTX A synchronous master is required to transmit data to a slave in order to receive data from the slave In some cases only a few words are transmitted and a lot of data is then received from the slave In that case one solution is to keep feeding the TX with data to trans mit but that consumes system bandwidth Instead AUTOTX can be used When AUTOTX in USARTn_CTRL is ...

Page 549: ...used for regular synchronous transfers I2S mode uses a separate word clock When operating in mono mode with only one channel of data the word clock pulses once at the start of each new word In stereo mode the word clock toggles at the start of new words and also gives away whether the transmitted word is for the left or right audio channel A word transmitted while the word clock is low is for the ...

Page 550: ...22 USART Standard I2S Waveform Reduced Accuracy on page 550 The first figure shows a waveform transmitted with full accuracy The wordlength can be configured to 32 bit 16 bit or 8 bit using FORMAT in USARTn_I2SCTRL In the second figure I2S data is transmitted with re duced accuracy i e the data transmitted has less bits than what is possible in the bus format Note that the msb of a word transmitte...

Page 551: ...LSB USn_CS word select Right channel Left channel Left channel Figure 18 24 USART Right Justified I2S Waveform In mono mode the word select signal pulses at the beginning of each word instead of toggling for each word Mono I2S waveform is shown in Figure 18 25 USART Mono I2S Waveform on page 551 USn_CLK USn_CS word select USn_TX USn_RX MSB Left channel Right channel Right channel LSB MSB Figure 18...

Page 552: ...buffer is full and the RX shift register is full regardless of the state of DBGHALT or chip halt Additional incoming data is discarded When DBGHALT is set RTS deasserts on RX buffer full or when chip halt is high However a low pulse detected on chip halt will keep RTS asserted when no frame is being received At the start of frame reception RTS will deas sert if chip halt is high and DBGHALT is set...

Page 553: ...an come from one of the following sources Transmit buffer and shift register empty No data to send Transmit buffer has room for more data This does not check the TXBIL for half full For DMA use it is either full or empty Transmit buffer has room for RIGHT I2S data Only used in I2S mode Even though there are two sources for write requests to the DMA only one should be used at a time since the reque...

Page 554: ... com parator is still enabled the counter continues counting By default the counter will count up to 256 and stop unless a RESTARTEN is set in one of the USARTn_TIMECMPn registers By using RESTARTEN and an interval programmed into TCMPVAL an interval timer can be set up The TSTART field needs to be changed to DISABLE to stop the interval timer The timer stops running once all of the compa rators a...

Page 555: ...T Timer Block Diagram The following sections will go into more details on programming the various usage cases Table 18 10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn Application TSTARTn TSTOPn TCMPVALn Other Response Timeout TSTART0 TXEOF TSTOP0 RXACT TCMPVAL0 0x08 TCMP0 in USARTn_IEN Receiver Timeout TSTART1 RXEOF TSTOP1 RXACT TCMPVAL1 0x08 TCMP1 in USARTn_IEN Large Receiver ...

Page 556: ...20 TCMPVAL1 0x0C TXARX0EN in USARTn_TRIGCTRL TCMP0 in USARTn_IEN Table 18 10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 555 shows some examples of how the USART timer can be programmed for various applications The following sections will describe more details for each applications shown in the table 18 3 10 1 Response Timeout Response Timeout is when a UART master sen...

Page 557: ...tion until the desired timeout is reached Once the RX start bit is detected comparator 1 will be disabled If TIMERRESTARTED in USARTn_STATUS is clear the TCMP1 interrupt is the first interrupt after RXEOF RX RX RECEIVER TIMEOUT T C M P n I N T Figure 18 28 USART RX Timeout 18 3 10 3 Break Detect LIN bus and half duplex UARTs can take advantage of the timer configured for break detection where RX i...

Page 558: ...0 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 555 for details on setting up this example For this example in Figure 18 30 USART TXSEQ Timing on page 558 ICS is set to TCMP2 in USARTn_TIMING To keep CS asserted during the inter character space set AUTOCS in USARTn_CTRL There are a few small pre set timing values provided for TX sequence timing Using these preset timing ...

Page 559: ... TXARX0EN in USARTn_TRIGCTRL to start the timer TSTART0 in USARTn_TIMECMP0 is set to RXEOF which enables the transitter of the timer delay For this example TCMPVAL in USARTn_TIMECMP0 is set to 0x20 to create a 32 baud time delay between the end of the RX frame and the start of the TX frame The break detect is configured by setting TSTART1 to RXACT to detect the start bit and setting TSTOP1 to RXAC...

Page 560: ...odula tor The width of the pulses generated by the IrDA modulator is set by configuring IRPW in USARTn_IRCTRL Four pulse widths are availa ble each defined relative to the configured bit period as listed in Table 18 11 USART IrDA Pulse Widths on page 560 Table 18 11 USART IrDA Pulse Widths IRPW Pulse width OVS 0 Pulse width OVS 1 Pulse width OVS 2 Pulse width OVS 3 00 1 16 1 8 1 6 1 4 01 2 16 2 8 ...

Page 561: ...ter 0x038 USARTn_TXDOUBLEX W TX Buffer Double Data Extended Register 0x03C USARTn_TXDOUBLE W TX Buffer Double Data Register 0x040 USARTn_IF R Interrupt Flag Register 0x044 USARTn_IFS W1 Interrupt Flag Set Register 0x048 USARTn_IFC R W1 Interrupt Flag Clear Register 0x04C USARTn_IEN RW Interrupt Enable Register 0x050 USARTn_IRCTRL RW IrDA Control Register 0x058 USARTn_INPUT RW USART Input Register ...

Page 562: ... long as RX is not full If TX is empty underflows are generated 28 BYTESWAP 0 RW Byteswap in Double Accesses Set to switch the order of the bytes in double accesses Value Description 0 Normal byte order 1 Byte order swapped 27 26 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 25 SSSEARLY 0 RW Synchronous Slave Setup Early Setup data...

Page 563: ...SmartCard Mode Use this bit to enable or disable SmartCard mode 17 AUTOTRI 0 RW Automatic TX Tristate When enabled TXTRI is set by hardware whenever the transmitter is idle and TXTRI is cleared by hardware when trans mission starts Value Description 0 The output on U S n_TX when the transmitter is idle is defined by TXINV 1 U S n_TX is tristated whenever the transmitter is idle 16 AUTOCS 0 RW Auto...

Page 564: ...hile in master mode Value Mode Description 0 NOACTION No action taken 1 GOTOSLAVEMODE Go to slave mode 10 MSBF 0 RW Most Significant Bit First Decides whether data is sent with the least significant bit first or the most significant bit first Value Description 0 Data is sent with the least significant bit first 1 Data is sent with the most significant bit first 9 CLKPHA 0 RW Clock Edge for Setup S...

Page 565: ...frames to tell whether the frame is an address frame or a data frame Value Description 0 The 9th bit of incoming frames has no special function 1 An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 2 CCEN 0 RW Collision Check Enable Enables collision checking on data when operating in hal...

Page 566: ... Name Reset Access Description 1 The USART operates in synchronous mode Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected world Rev 1 1 566 ...

Page 567: ...he first stop bit only 11 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 9 8 PARITY 0x0 RW Parity Bit Mode Determines whether parity bits are enabled and whether even or odd parity should be used Only available in asynchro nous mode Value Mode Description 0 NONE Parity bits are not used 2 EVEN Even parity are used Parity bits are...

Page 568: ...ains 10 data bits 8 ELEVEN Each frame contains 11 data bits 9 TWELVE Each frame contains 12 data bits 10 THIRTEEN Each frame contains 13 data bits 11 FOURTEEN Each frame contains 14 data bits 12 FIFTEEN Each frame contains 15 data bits 13 SIXTEEN Each frame contains 16 data bits Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected worl...

Page 569: ...lected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 selected 11 PRSCH11 PRS Channel 11 selected 15 13 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 RXATX2EN 0 RW Enable Receive Trigger Afte...

Page 570: ...ger the transmitter after TCMP0VAL bit times to force a minimum response delay 6 AUTOTXTEN 0 RW AUTOTX Trigger Enable When set AUTOTX is enabled as long as the PRS channel selected by TSEL has a high value 5 TXTEN 0 RW Transmit Trigger Enable When set the PRS channel selected by TSEL sets TXEN enabling the transmitter on positive trigger edges 4 RXTEN 0 RW Receive Trigger Enable When set the PRS c...

Page 571: ...lear RXBLOCK resulting in all incoming frames being loaded into the receive buffer 6 RXBLOCKEN 0 W1 Receiver Block Enable Set to set RXBLOCK resulting in all incoming frames being discarded 5 MASTERDIS 0 W1 Master Disable Set to disable master mode clearing the MASTER status bit and putting the USART in slave mode 4 MASTEREN 0 W1 Master Enable Set to enable master mode setting the MASTER status bi...

Page 572: ... set a TCMP event counter variable in memory to 0x1 to indicate the first TCMP interrupt of the sequence 13 TXIDLE 1 R TX Idle Set when TX idle 12 RXFULLRIGHT 0 R RX Full of Right Data When set the entire RX buffer contains right data Only used in I2S mode 11 RXDATAVRIGHT 0 R RX Data Right When set reading RXDATA or RXDATAX gives right data Else left data is read Only used in I2S mode 10 TXBSRIGHT...

Page 573: ...nsmitter is enabled 0 RXENS 0 R Receiver Enable Status Set when the receiver is enabled 18 5 6 USARTn_CLKDIV Clock Control Register Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x00000 Access RW RWH Name AUTOBAUDEN DIV Bit Name Reset Access Description 31 AUTOBAUDEN 0 RW AUTOBAUD Detection Enable Detects the baud rate based...

Page 574: ...h future devices always write bits to 0 More information in 1 2 Conven tions 8 0 RXDATA 0x000 R RX Data Use this register to access data read from the USART Buffer is cleared on read access 18 5 8 USARTn_RXDATA RX Buffer Data Register Actionable Reads Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access R Name RXDATA Bit ...

Page 575: ...ous mode only 29 25 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 24 16 RXDATA1 0x000 R RX Data 1 Second frame read from buffer 15 FERR0 0 R Data Framing Error 0 Set if data in buffer has a framing error Can be the result of a break condition 14 PERR0 0 R Data Parity Error 0 Set if data in buffer has a parity error asynchronous mod...

Page 576: ... 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x000 Access R R R Name FERRP PERRP RXDATAP Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 FERRP 0 R Data Framing Error Peek Set if data in buffer has a framing error Can be the result of a break condition 14 PERRP 0 R Data ...

Page 577: ...de only 29 25 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 24 16 RXDATAP1 0x000 R RX Data 1 Peek Second frame read from FIFO 15 FERRP0 0 R Data Framing Error 0 Peek Set if data in buffer has a framing error Can be the result of a break condition 14 PERRP0 0 R Data Parity Error 0 Peek Set if data in buffer has a parity error asynch...

Page 578: ...fter transmission 13 TXBREAK 0 W Transmit Data as Break Set to send data as a break Recipient will see a framing error or a break condition depending on its configuration and the value of TXDATA 12 TXTRIAT 0 W Set TXTRI After Transmission Set to tristate transmitter by setting TXTRI after transmission 11 UBRXAT 0 W Unblock RX After Transmission Set to clear RXBLOCK after transmission unblocking th...

Page 579: ...Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0 TXDATA 0x00 W TX Data This frame will be added to TX buffer Only 8 LSB can be written using this register 9th bit and control bits will be cleared Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected wor...

Page 580: ...r RXBLOCK after transmission unblocking the receiver 26 25 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 24 16 TXDATA1 0x000 W TX Data Second frame to write to FIFO 15 RXENAT0 0 W Enable RX After Transmission Set to enable reception after transmission 14 TXDISAT0 0 W Clear TXEN After Transmission Set to disable transmitter and rele...

Page 581: ...DATA0 Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 8 TXDATA1 0x00 W TX Data Second frame to write to buffer 7 0 TXDATA0 0x00 W TX Data First frame to write to buffer Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected world R...

Page 582: ...a 11 SSM 0 R Slave Select in Master Mode Interrupt Flag Set when the device is selected as a slave when in master mode 10 MPAF 0 R Multi Processor Address Frame Interrupt Flag Set when a multi processor address frame is detected 9 FERR 0 R Framing Error Interrupt Flag Set when a frame with a framing error is received while RXBLOCK is cleared 8 PERR 0 R Parity Error Interrupt Flag Set when a frame ...

Page 583: ...uffer Level Interrupt Flag Set when buffer becomes empty if buffer level is set to 0x0 or when the number of empty TX buffer elements equals speci fied buffer level 0 TXC 0 R TX Complete Interrupt Flag This interrupt is set after a transmission when both the TX buffer and shift register are empty Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a m...

Page 584: ...LE Interrupt Flag Write 1 to set the TXIDLE interrupt flag 12 CCF 0 W1 Set CCF Interrupt Flag Write 1 to set the CCF interrupt flag 11 SSM 0 W1 Set SSM Interrupt Flag Write 1 to set the SSM interrupt flag 10 MPAF 0 W1 Set MPAF Interrupt Flag Write 1 to set the MPAF interrupt flag 9 FERR 0 W1 Set FERR Interrupt Flag Write 1 to set the FERR interrupt flag 8 PERR 0 W1 Set PERR Interrupt Flag Write 1 ...

Page 585: ...uture devices always write bits to 0 More information in 1 2 Conven tions 0 TXC 0 W1 Set TXC Interrupt Flag Write 1 to set the TXC interrupt flag Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected world Rev 1 1 585 ...

Page 586: ...he IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 12 CCF 0 R W1 Clear CCF Interrupt Flag Write 1 to clear the CCF interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 11 SSM 0 R W1 Clear SSM Interrupt Flag Write 1 to clear the SSM interrupt flag Reading returns the ...

Page 587: ...e IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 3 RXFULL 0 R W1 Clear RXFULL Interrupt Flag Write 1 to clear the RXFULL interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 2 1 Reserved To ensure compatibility with future devices always write bits to 0 More informa...

Page 588: ... Interrupt Enable Enable disable the TCMP0 interrupt 13 TXIDLE 0 RW TXIDLE Interrupt Enable Enable disable the TXIDLE interrupt 12 CCF 0 RW CCF Interrupt Enable Enable disable the CCF interrupt 11 SSM 0 RW SSM Interrupt Enable Enable disable the SSM interrupt 10 MPAF 0 RW MPAF Interrupt Enable Enable disable the MPAF interrupt 9 FERR 0 RW FERR Interrupt Enable Enable disable the FERR interrupt 8 P...

Page 589: ...DATAV Interrupt Enable Enable disable the RXDATAV interrupt 1 TXBL 0 RW TXBL Interrupt Enable Enable disable the TXBL interrupt 0 TXC 0 RW TXC Interrupt Enable Enable disable the TXC interrupt Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected world Rev 1 1 589 ...

Page 590: ...H3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 selected 11 PRSCH11 PRS Channel 11 selected 7 IRPRSEN 0 RW IrDA PRS Channel Enable Enable the PRS channel selected by IRPRSSEL as input to IrDA module inste...

Page 591: ... 16 for OVS 0 and 1 8 for OVS 1 1 TWO IrDA pulse width is 2 16 for OVS 0 and 2 8 for OVS 1 2 THREE IrDA pulse width is 3 16 for OVS 0 and 3 8 for OVS 1 3 FOUR IrDA pulse width is 4 16 for OVS 0 and 4 8 for OVS 1 0 IREN 0 RW Enable IrDA Module Enable IrDA module and rout USART signals through it Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a mor...

Page 592: ...nput to CLK Value Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 selected 11 PRSCH11...

Page 593: ...nnel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 selected 11 PRSCH11 PRS Channel 11 selected Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected world Rev 1 1 593 ...

Page 594: ...rd 16 bit data 6 W16D8 16 bit word 8 bit data 7 W8D8 8 bit word 8 bit data 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 4 DELAY 0 RW Delay on I2S Data Set to add a one cycle delay between a transition on the word clock and the start of the I2S word Should be set for stand ard I2S format 3 DMASPLIT 0 RW Separate DMA Request for...

Page 595: ...eset Access Description 0 EN 0 RW Enable I2S Mode Set the U S ART in I2S mode Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected world Rev 1 1 595 ...

Page 596: ...he end of transmission for TCMPVAL0 baud times 6 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud times 7 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud times 27 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 26 24 ICS 0x0 RW Inter character Spacing Inter character spacing after each TX fram...

Page 597: ...P2 CS is asserted before the start of transmission for TCMPVAL2 baud times 19 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 18 16 TXDELAY 0x0 RW TX Frame Start Delay Number of baud times to delay the start of frame transmission When using USART_TIMECMPn normally set TSTART to DISABLE to stop general timer and to prevent unwanted in...

Page 598: ...register will contin ue transmitting the next TXBUFn data will not load into the TX shift register Value Description 0 Ingore CTS 1 Stop transmitting when CTS is negated 1 CTSINV 0 RW CTS Pin Inversion When set the CTS pin polarity is inverted Value Description 0 The USn_CTS pin is low true 1 The USn_CTS pin is high true 0 DBGHALT 0 RW Debug Halt Value Description 0 Continue to transmit until TX b...

Page 599: ... source which disables comparator 0 Value Mode Description 0 TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and trig gers a TCMP0 event 1 TXST Comparator 0 is disabled at the start of transmission 2 RXACT Comparator 0 is disabled on RX going going Active default low 3 RXACTN Comparator 0 is disabled on RX going Inactive 19 Reserved To ensure compatibility with future devices always...

Page 600: ...TCMPVAL 0x00 RW Timer Comparator 0 When the timer equals TCMPVAL this signals a TCMP0 event and sets the TCMP0 flag This event can also be used to enable various USART functionality A value of 0x00 represents 256 baud times Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected world Rev 1 1 600 ...

Page 601: ...e source which disables comparator 1 Value Mode Description 0 TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and trig gers a TCMP1 event 1 TXST Comparator 1 is disabled at TX start TX Engine 2 RXACT Comparator 1 is disabled on RX going going Active default low 3 RXACTN Comparator 1 is disabled on RX going Inactive 19 Reserved To ensure compatibility with future devices always write...

Page 602: ...TCMPVAL 0x00 RW Timer Comparator 1 When the timer equals TCMPVAL this signals a TCMP1 event and sets the TCMP1 flag This event can also be used to enable various USART functionality A value of 0x00 represents 256 baud times Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected world Rev 1 1 602 ...

Page 603: ...e source which disables comparator 2 Value Mode Description 0 TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and trig gers a TCMP2 event 1 TXST Comparator 2 is disabled at TX start TX Engine 2 RXACT Comparator 2 is disabled on RX going going Active default low 3 RXACTN Comparator 2 is disabled on RX going Inactive 19 Reserved To ensure compatibility with future devices always write...

Page 604: ...TCMPVAL 0x00 RW Timer Comparator 2 When the timer equals TCMPVAL this signals a TCMP2 event and sets the TCMP2 flag This event can also be used to enable various USART functionality A value of 0x00 represents 256 baud times Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected world Rev 1 1 604 ...

Page 605: ...nabled 4 CTSPEN 0 RW CTS Pin Enable When set the CTS pin of the USART is enabled Value Description 0 The USn_CTS pin is disabled 1 The USn_CTS pin is enabled 3 CLKPEN 0 RW CLK Pin Enable When set the CLK pin of the USART is enabled Value Description 0 The USn_CLK pin is disabled 1 The USn_CLK pin is enabled 2 CSPEN 0 RW CS Pin Enable When set the CS pin of the USART is enabled Value Description 0 ...

Page 606: ... set the RX MISO pin of the USART is enabled Value Description 0 The U S n_RX MISO pin is disabled 1 The U S n_RX MISO pin is enabled Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected world Rev 1 1 606 ...

Page 607: ...of the USART CLK pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18...

Page 608: ...ption 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 L...

Page 609: ...ption 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 L...

Page 610: ...ion 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LOC19 Location 19 20 LOC...

Page 611: ...ation 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Location 28 29 LOC29 Location 29 30 LOC30 Location 30 31 LOC31 Location 31 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected world Rev 1 1 611 ...

Page 612: ...the USART RTS pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Lo...

Page 613: ...in Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Location 18 19 LO...

Page 614: ...5 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Location 28 29 LOC29 Location 29 30 LOC30 Location 30 31 LOC31 Location 31 Reference Manual USART Universal Synchronous Asynchronous Receiver Transmitter silabs com Building a more connected world Rev 1 1 614 ...

Page 615: ...when the system is in low energy mode EM2 Deep Sleep with most core functionality turned off the LEUART can wait for an incoming UART frame while having an extremely low energy consumption When a UART frame is completely received the CPU can quickly be woken up Alternatively multiple frames can be transferred via the Direct Memory Access DMA module into RAM memory before waking up the CPU Received...

Page 616: ... or odd HW parity bit generation and check Configurable number of stop bits 1 or 2 Capable of sleep mode wake up on received frame Either wake up on any received byte or Wake up only on specified start and signal frames Supports transmission and reception in EM0 Active EM1 Sleep and EM2 Deep Sleep with Full DMA support Specified start frame can start reception automatically IrDA modulator pulse ge...

Page 617: ...Register LEUn_RX UART Control and status Peripheral Bus TX Baud rate generator RX Baud rate generator Start frame STARTFRAME RX Wakeup SYNC Pulse extend Pulse gen Signal frame SIGFRAME Start frame interrupt RXBLOCK LEUn_TX Figure 19 1 LEUART Overview Reference Manual LEUART Low Energy Universal Asynchronous Receiver Transmitter silabs com Building a more connected world Rev 1 1 617 ...

Page 618: ... in a low idle state a high start bit inverted data and parity bits and low stop bits INV should only be changed while the receiver is disabled 19 3 1 1 Parity Bit Calculation and Handling Hardware automatically inserts parity bits into outgoing frames and checks the parity bits of incoming frames The possible parity modes are defined in Table 19 1 LEUART Parity Bit on page 618 When even parity is...

Page 619: ...et of desired baud rates and the closest baud rates reachable by the LEUART with a 32 768 kHz clock source It also shows the average baud rate error Table 19 2 LEUART Baud Rates Desired baud rate LEUARTn_CLKDIV LEUARTn_CLKDIV 256 Actual Baud Rate Error 300 27704 108 21875 300 0217 0 01 600 13728 53 625 599 8719 0 02 1200 6736 26 3125 1199 744 0 02 2400 3240 12 65625 2399 487 0 02 4800 1488 5 8125 ...

Page 620: ...rted Transmission of this frame will be completed An overview of the operation of the transmitter is shown in Figure 19 5 LEUART Transmitter Overview on page 620 LEUn_TX Transmit shift register TXENS d0 d8 control d0 d2 d4 d6 d8 d7 d5 d3 d1 control TXDATA TXDATAX BIT8DV Transmit buffer 0 Figure 19 5 LEUART Transmitter Overview 19 3 4 2 Frame Transmission Control The transmission control bits which...

Page 621: ...S and the RXDATAV interrupt flag in LEUARTn_IF are set Both the RXDATAV status flag and the RXDATAV interrupt flag are cleared by hardware when data is no longer available i e when data has been read out of the buffer Data can be read from receive buffer using either LEUARTn_RXDATA or LEUARTn_RXDATAX LEUARTn_RXDATA gives access to the 8 least significant bits of the received frame while LEUARTn_RX...

Page 622: ... at that time The overflow interrupt flag RXOF in LEUARTn_IF will be set if a frame in the receive shift register waiting to be loaded into the receive buffer is overwritten by an incoming frame even though RXBLOCK is set 19 3 5 3 Data Sampling The receiver samples each incoming bit as close as possible to the middle of the bit period Except for the start bit only a single sam ple is taken of each...

Page 623: ...lts in the STARTF interrupt flag in LEUARTn_IF being set regardless of the value of SFUBRX in LEUARTn_CTRL This allows an interrupt to be made when the start frame is detected When 8 data bit frame formats are used only the 8 least significant bits of LEUARTn_STARTFRAME are compared to incoming frames The full length of LEUARTn_STARTFRAME is used when operating with frames consisting of 9 data bit...

Page 624: ...nfigured incoming frame An address frame with a parity error or a framing error is not detected as an address frame The Start Signal and address frames should not be set to match the same frame since each of these uses separate synchronization to the peripherial clock domain 19 3 6 Loopback The LEUART receiver samples LEUn_RX by default and the transmitter drives LEUn_TX by default This is not the...

Page 625: ...tup the driver must be controlled by a GPIO Figure 19 10 LEUART Half Duplex Communication with External Driver on page 625 shows an example configuration using an external driv er LEUART RX TX µC GPIO Figure 19 10 LEUART Half Duplex Communication with External Driver 19 3 7 3 Two Data links Some limited devices only support half duplex communication even though two data links are available In this...

Page 626: ...nd Transmit buffer empty In some cases it may be sensible to temporarily stop DMA access to the LEUART when a parity or framing error has occurred This is enabled by setting ERRSDMA in LEUARTn_CTRL When this bit is set the DMA controller will not get requests from the receive buffer if a framing error or parity error is detected in the received byte The ERRSDMA bit applies only to the RX DMA When ...

Page 627: ... must also be shorter than half a UART bit period At 2400 baud or lower the pulse generator is able to generate RZI pulses compatible with the IrDA physical layer specification The external IrDA device must generate pulses of sufficient length for successful two way communication PULSEFILT in the LEUARTn_PULSECTRL register can be used to extend the minimum receive pulse width from 2 clock periods ...

Page 628: ...Register 0x024 LEUARTn_TXDATAX W Transmit Buffer Data Extended Register 0x028 LEUARTn_TXDATA W Transmit Buffer Data Register 0x02C LEUARTn_IF R Interrupt Flag Register 0x030 LEUARTn_IFS W1 Interrupt Flag Set Register 0x034 LEUARTn_IFC R W1 Interrupt Flag Clear Register 0x038 LEUARTn_IEN RW Interrupt Enable Register 0x03C LEUARTn_PULSECTRL RW Pulse Control Register 0x040 LEUARTn_FREEZE RW Freeze Re...

Page 629: ...PLE Transmission of new frames are delayed by three bit periods 13 TXDMAWU 0 RW TX DMA Wakeup Set to wake the DMA controller up when in EM2 and space is available in the transmit buffer Value Description 0 While in EM2 the DMA controller will not get requests about space be ing available in the transmit buffer 1 DMA is available in EM2 for the request about space available in the transmit buffer 1...

Page 630: ...ve buffer 7 LOOPBK 0 RW Loopback Enable Set to connect receiver to LEUn_TX instead of LEUn_RX Value Description 0 The receiver is connected to and receives data from LEUn_RX 1 The receiver is connected to and receives data from LEUn_TX 6 ERRSDMA 0 RW Clear RX DMA on Error When set RX DMA requests will be cleared on framing and parity errors Value Description 0 Framing and parity errors have no eff...

Page 631: ... bits are automatically generated and checked by hardware 1 DATABITS 0 RW Data Bit Mode This register sets the number of data bits Value Mode Description 0 EIGHT Each frame contains 8 data bits 1 NINE Each frame contains 9 data bits 0 AUTOTRI 0 RW Automatic Transmitter Tristate When set LEUn_TX is tristated whenever the transmitter is inactive Value Description 0 LEUn_TX is held high when the tran...

Page 632: ...ft register 6 CLEARTX 0 W1 Clear TX Set to clear transmit buffer and the TX shift register 5 RXBLOCKDIS 0 W1 Receiver Block Disable Set to clear RXBLOCK resulting in all incoming frames being loaded into the receive buffer 4 RXBLOCKEN 0 W1 Receiver Block Enable Set to set RXBLOCK resulting in all incoming frames being discarded 3 TXDIS 0 W1 Transmitter Disable Set to disable transmission 2 TXEN 0 ...

Page 633: ...ffer Set when the transmit buffer is empty and cleared when it is full 3 TXC 0 R TX Complete Set when a transmission has completed and no more data is available in the transmit buffer Cleared when a new transmis sion starts 2 RXBLOCK 0 R Block Incoming Data When set the receiver discards incoming frames An incoming frame will not be loaded into the receive buffer if this bit is set at the instant ...

Page 634: ...0 2 will always be 0 2 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 19 5 5 LEUARTn_STARTFRAME Start Frame Register Async Reg For more information about asynchronous registers see 4 3 Access to Low Energy Peripherals Asynchronous Registers Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 635: ...t Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x000 Access R R R Name FERR PERR RXDATA Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 FERR 0 R Receive Data Framing Error Set if data in buffer has a framing error Can be t...

Page 636: ... 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x000 Access R R R Name FERRP PERRP RXDATAP Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 FERRP 0 R Receive Data Framing Error Peek Set if data in buffer has a framing error Can be the result of a break condi...

Page 637: ...ectly after transmission has competed Value Description 0 The transmitter is not disabled after the frame has been transmitted 1 The transmitter is disabled clearing TXENS after the frame has been transmitted 13 TXBREAK 0 W Transmit Data as Break Set to send data as a break Recipient will see a framing error or a break condition depending on its configuration and the value of TXDATA Value Descript...

Page 638: ...2 1 0 Reset 0x00 Access W Name TXDATA Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0 TXDATA 0x00 W TX Data This frame will be added to the transmit buffer Only 8 LSB can be written using this register 9th bit and control bits will be cleared Reference Manual LEUART Low Energy Universal Asyn...

Page 639: ...ince they use different synchronizers 7 FERR 0 R Framing Error Interrupt Flag Set when a frame with a framing error is received while RXBLOCK is cleared 6 PERR 0 R Parity Error Interrupt Flag Set when a frame with a parity error is received while RXBLOCK is cleared 5 TXOF 0 R TX Overflow Interrupt Flag Set when a write is done to the transmit buffer while it is full The data already in the transmi...

Page 640: ...lag 8 MPAF 0 W1 Set MPAF Interrupt Flag Write 1 to set the MPAF interrupt flag 7 FERR 0 W1 Set FERR Interrupt Flag Write 1 to set the FERR interrupt flag 6 PERR 0 W1 Set PERR Interrupt Flag Write 1 to set the PERR interrupt flag 5 TXOF 0 W1 Set TXOF Interrupt Flag Write 1 to set the TXOF interrupt flag 4 RXUF 0 W1 Set RXUF Interrupt Flag Write 1 to set the RXUF interrupt flag 3 RXOF 0 W1 Set RXOF ...

Page 641: ... the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 6 PERR 0 R W1 Clear PERR Interrupt Flag Write 1 to clear the PERR interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 5 TXOF 0 R W1 Clear TXOF Interrupt Flag Write 1 to clear the TXOF interrupt flag Reading return...

Page 642: ... STARTF interrupt 8 MPAF 0 RW MPAF Interrupt Enable Enable disable the MPAF interrupt 7 FERR 0 RW FERR Interrupt Enable Enable disable the FERR interrupt 6 PERR 0 RW PERR Interrupt Enable Enable disable the PERR interrupt 5 TXOF 0 RW TXOF Interrupt Enable Enable disable the TXOF interrupt 4 RXUF 0 RW RXUF Interrupt Enable Enable disable the RXUF interrupt 3 RXOF 0 RW RXOF Interrupt Enable Enable d...

Page 643: ...n in 1 2 Conven tions 5 PULSEFILT 0 RW Pulse Filter Enable a one cycle pulse filter for pulse extender Value Description 0 Filter is disabled Pulses must be at least 2 cycles long for reliable de tection 1 Filter is enabled Pulses must be at least 3 cycles long for reliable de tection 4 PULSEEN 0 RW Pulse Generator Extender Enable Filter LEUART output through pulse generator and the LEUART input t...

Page 644: ...ven tions 0 REGFREEZE 0 RW Register Update Freeze When set the update of the LEUART logic from registers is postponed until this bit is cleared Use this bit to update several registers simultaneously Value Mode Description 0 UPDATE Each write access to a LEUART register is updated into the Low Fre quency domain as soon as possible 1 FREEZE The LEUART is not updated with the new written value Refer...

Page 645: ... Busy Set when the value written to TXDATA is being synchronized 5 TXDATAX 0 R TXDATAX Register Busy Set when the value written to TXDATAX is being synchronized 4 SIGFRAME 0 R SIGFRAME Register Busy Set when the value written to SIGFRAME is being synchronized 3 STARTFRAME 0 R STARTFRAME Register Busy Set when the value written to STARTFRAME is being synchronized 2 CLKDIV 0 R CLKDIV Register Busy S...

Page 646: ...vices always write bits to 0 More information in 1 2 Conven tions 1 TXPEN 0 RW TX Pin Enable When set the TX pin of the LEUART is enabled Value Description 0 The LEUn_TX pin is disabled 1 The LEUn_TX pin is enabled 0 RXPEN 0 RW RX Pin Enable When set the RX pin of the LEUART is enabled Value Description 0 The LEUn_RX pin is disabled 1 The LEUn_RX pin is enabled Reference Manual LEUART Low Energy U...

Page 647: ...e mapping between location and physical pins Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LO...

Page 648: ...n and physical pins Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 ...

Page 649: ...ation 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Location 28 29 LOC29 Location 29 30 LOC30 Location 30 31 LOC31 Location 31 Reference Manual LEUART Low Energy Universal Asynchronous Receiver Transmitter silabs com Building a more connected world Rev 1 1 649 ...

Page 650: ...s always write bits to 0 More information in 1 2 Conven tions 3 0 RXPRSSEL 0x0 RW RX PRS Channel Select Select PRS channel as input to RX Value Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Ch...

Page 651: ...ntrol or work as a frequency gen erator The timer can also count events and control other peripherals through the PRS which offloads the CPU and reduces energy consumption 20 1 Introduction The general purpose timer has 3 or 4 compare capture channels for input capture and compare Pulse Width Modulation PWM output The TIMER and WTIMER peripherals are identical except for the timer width A TIMER is...

Page 652: ...ise filtering on capture inputs Output Compare Compare output toggle pulse on compare match Immediate update of compare registers PWM Up count PWM Up down count PWM Predictable initial PWM output state configured by SW Buffered compare register to ensure glitch free update of compare values Clock sources HFPERCLKTIMERn 10 bit Prescaler External pin Peripheral Reflex System Debug mode Configurable ...

Page 653: ...Rs Wide TIMERs are 32 bit variants of the TIMER WTIMER module 20 3 1 Counter Modes The timer consists of a counter that can be configured to the following modes 1 Up count Counter counts up until it reaches the value in TIMERn_TOP where it is reset to 0 before counting up again 2 Down count The counter starts at the value in TIMERn_TOP and counts down When it reaches 0 it is reloaded with the valu...

Page 654: ...r through either an external pin or PRS input This is done through the input logic for the Com pare Capture Channel 0 The Timer Counter allows individual actions start stop reload to be taken for rising and falling input edges This is configured in the RISEA and FALLA fields in TIMERn_CTRL The reload value is 0 in up count and up down count mode and TOP in down count mode The RUNNING bit in TIMERn...

Page 655: ...a higher frequency than fHFPERCLK 3 when running from a pin input or a PRS input with FILT enabled in TIMERn_CCx_CTRL When running from PRS without FILT the frequency can be as high as fHFPERCLK Note that when clocking the timer from the same pulse that triggers a start through RISEA FALLA in TIMERn_CTRL the starting pulse will not update the Counter Value 20 3 1 6 Underflow Overflow From Neighbor...

Page 656: ...et been written to the TIMERn_TOP register see Figure 20 5 TIMER WTIMER TOP Value Update Functionality on page 656 Note When writing to TIMERn_TOP register directly the TIMERn_TOPB register value will be invalidated and the TOPBV flag will be cleared This prevents TIMERn_TOP register from being immediately updated by an existing valid TIMERn_TOPB value during the next update event TOP APB Write TO...

Page 657: ...onnected to an external interrupt and trigger a counter reset from the interrupt service routine By connecting a periodic signal from another timer as input capture on Com pare Capture Channel 2 it is also possible to calculate speed and acceleration Note In Quadrature Decoder mode overflow and underflow triggers an update event Counter Controlled by TIMERn_CTRL Compare Capture channel 1 Controlle...

Page 658: ...Mode In X4 Decoding mode the counter increments or decrements on every edge of Channel A and Channel B see Figure 20 9 TIMER WTIMER X4 Decoding Mode on page 658 and Table 20 2 TIMER WTIMER Counter Response in X4 Decoding Mode on page 658 Table 20 2 TIMER WTIMER Counter Response in X4 Decoding Mode Opposite Channel Channel A Channel B Rising Falling Rising Falling Channel A 0 Decrement Increment Ch...

Page 659: ...ic on page 659 Compare Capture channels 0 and 1 are the inputs for the Quadrature Decoder Mode The input channel can be filtered before it is used which requires the input to remain stable for 5 cycles in a row before the input is propagated to the output TIMn_CCx PRS channels PRSSEL INSEL Filter FILT ICEDGE Input Capture x Figure 20 11 TIMER WTIMER Input Pin Logic 20 3 2 2 Compare Capture Registe...

Page 660: ...o TIMERn_CCx_CCV from TIMERn_CCx_CCVB if it contains valid data The CC value can be read without altering the FIFO contents by reading TIMERn_CCx_CCVP TIMERn_CCx_CCVB can also be read without altering the FIFO contents The ICV flag in TIMERn_STATUS indicates if there is a valid unread capture in TIMERn_CCx_CCV In this mode TIMERn_CCx_CCV is read only In the case where a capture is triggered while ...

Page 661: ...661 For period capture the Compare Capture Channel should then be set to input capture on a rising edge of the same input signal To capture the width of a high pulse the Compare Capture Channel should be set to capture on a falling edge of the input signal To measure the low pulse width of a signal opposite polarities should be chosen 0 Input CNT Clear Start Input Capture frequency capture Input C...

Page 662: ...mpare output is delayed by one cycle to allow for full 0 to 100 PWM generation If occurring in the same cycle match action will have priority over overflow or underflow action The input selected through PRSSEL INSEL and FILTSEL in TIMERn_CCx_CTRL for the CC channel will also be sampled on com pare match and the result is found in the CCPOL bits in TIMERn_STATUS It is also possible to configure the...

Page 663: ... written to TIMERn_CCx_CCV on the next update event This func tionality ensures glitch free PWM outputs The CCVBV flag in TIMERn_STATUS indicates whether the TIMERn_CCx_CCVB register contains data that has not yet been written to the TIMERn_CCx_CCV register Note that when writing 0 to TIMERn_CCx_CCVB in up down count mode the CCV value is updated when the timer counts from 0 to 1 Thus the compare ...

Page 664: ...fFRG fHFPERCLK 2 PRESC 1 x TOP 1 x 2 Figure 20 18 TIMER WTIMER Up count Frequency Generation Equation The figure below provides cycle accurate timing and event generation information for frequency generation 0 TIMERn_TOP TIMERn_CCx_CCV 1 2 3 4 TIMERn_CCx Figure 20 19 TIMER WTIMER Up count Frequency Generation Detail 20 3 2 8 Pulse Width Modulation PWM In PWM mode TIMERn_CCx_CCV is buffered to avoi...

Page 665: ...igure 20 20 TIMER WTIMER Up count PWM Generation RPWMup log TOP 1 log 2 Figure 20 21 TIMER WTIMER Up count PWM Resolution Equation The PWM frequency is given by Figure 20 22 TIMER WTIMER Up count PWM Frequency Equation on page 665 fPWMup down fHFPERCLK 2 PRESC x TOP 1 Figure 20 22 TIMER WTIMER Up count PWM Frequency Equation The high duty cycle is given by Figure 20 23 TIMER WTIMER Up count Duty C...

Page 666: ...solution is given by Figure 20 26 TIMER WTIMER 2x PWM Resolution Equation on page 666 RPWM2xmode log TOP 2 1 log 2 Figure 20 26 TIMER WTIMER 2x PWM Resolution Equation The PWM frequency is given by Figure 20 27 TIMER WTIMER 2x Mode PWM Frequency Equation Up count on page 666 fPWM2xmode fHFPERCLK floor TOP 2 1 Figure 20 27 TIMER WTIMER 2x Mode PWM Frequency Equation Up count The high duty cycle is ...

Page 667: ...Resolution Equation The PWM frequency is given by Figure 20 31 TIMER WTIMER Up Down count PWM Frequency Equation on page 667 fPWMup down fHFPERCLK 2 PRESC 1 x TOP Figure 20 31 TIMER WTIMER Up Down count PWM Frequency Equation The high duty cycle is given by Figure 20 32 TIMER WTIMER Up Down count Duty Cycle Equation on page 667 DSup down CCVx TOP Figure 20 32 TIMER WTIMER Up Down count Duty Cycle ...

Page 668: ...wo equations based on the CCVx values Figure 20 37 TIMER WTIMER 2x Mode Duty Cycle Equation for CCVx 1 or CCVx even on page 668 and Figure 20 38 TIMER WTIMER 2x Mode Duty Cycle Equation for all other CCVx odd values on page 668 DS2xmode CCVx 2 floor TOP 2 4 Figure 20 37 TIMER WTIMER 2x Mode Duty Cycle Equation for CCVx 1 or CCVx even DS2xmode CCVx 2 CCVx floor TOP 2 4 Figure 20 38 TIMER WTIMER 2x ...

Page 669: ...riple half bridge setup UH VH and WH and the complementary outputs connected to the respective low side transistors UL VL WL shown in Figure 20 40 TIMER WTIMER Triple Half Bridge on page 669 Transistors used in such a bridge often do not open close instantaneously and using the exact complementary inputs for the high and low side of a half bridge may result in situations where both gates are open ...

Page 670: ...es share prescaler value The prescaler divides the HFPERCLKTIMERn by a configurable factor between 1 and 1024 which is set in the DTPRESC field in TIMER0_DTTIME The rising and falling edge dead times are configured in DTRISET and DTFALLT in TIM ER0_DTTIME to any number between 1 64 HFPERCLKTIMER0 cycles The DTAR and DTFATS bits in TIMER0_DTCTRL control the DTI output behavior when the timer stops ...

Page 671: ...ired that the primary outputs are active high while the complementary outputs are active low This can be accomplished by manipulating the DTCINV bit of the TIMER0_DTCTRL register which inverts the polarity of the complementary outputs relative to the primary outputs As an example DTIPOL 0 and DTCINV 0 results in outputs with opposite phase and active high states Similarly DTIPOL 1 and DTCINV 1 res...

Page 672: ... a fault occurs the bit representing the fault source is set in TIMER0_DTFAULT register and the outputs from the DTI unit are set to a well defined state The following options are available and can be enabled by configuring DTFACT in TIMER0_DTFC Set outputs to inactive level Clear outputs Tristate outputs With the first option enabled the output state in case of a fault depends on the polarity set...

Page 673: ... occur The different DMA requests are cleared when certain acknowledge conditions are met see Table 20 4 TIMER WTIMER DMA Events on page 673 Events which clear the DMA requests do not clear interrupt flags Software must still manually clear the interrupt flag if interrupts are in use If DMACLRACT is set in TIMERn_CTRL the DMA request is cleared when the triggered DMA channel is active without havi...

Page 674: ...rol Register 0x064 TIMERn_CC0_CCV RWH a CC Channel Value Register 0x068 TIMERn_CC0_CCVP R CC Channel Value Peek Register 0x06C TIMERn_CC0_CCVB RWH CC Channel Buffer Register TIMERn_CCx_CTRL RW CC Channel Control Register TIMERn_CCx_CCV RWH a CC Channel Value Register TIMERn_CCx_CCVP R CC Channel Value Peek Register TIMERn_CCx_CCVB RWH CC Channel Buffer Register 0x090 TIMERn_CC3_CTRL RW CC Channel ...

Page 675: ...rack the polarity of the inputs 27 24 PRESC 0x0 RW Prescaler Setting These bits select the prescaling factor Value Mode Description 0 DIV1 The HFPERCLK is undivided 1 DIV2 The HFPERCLK is divided by 2 2 DIV4 The HFPERCLK is divided by 4 3 DIV8 The HFPERCLK is divided by 8 4 DIV16 The HFPERCLK is divided by 16 5 DIV32 The HFPERCLK is divided by 32 6 DIV64 The HFPERCLK is divided by 64 7 DIV128 The ...

Page 676: ...ction These bits select the action taken in the counter when a falling edge occurs on the input Value Mode Description 0 NONE No action 1 START Start counter without reload 2 STOP Stop counter without reload 3 RELOADSTART Reload and start counter 9 8 RISEA 0x0 RW Timer Rising Input Edge Action These bits select the action taken in the counter when a rising edge occurs on the input Value Mode Descr...

Page 677: ... is not started stopped reloaded by other timers 1 Timer is started stopped reloaded by other timers 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 0 MODE 0x0 RW Timer Mode These bits set the counting mode for the Timer Note when Quadrature Decoder Mode is selected MODE b11 the CLKSEL is don t care The Timer is clocked by the De...

Page 678: ... Name STOP START Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 STOP 0 W1 Stop Timer Set this bit to stop timer 0 START 0 W1 Start Timer Set this bit to start timer Reference Manual TIMER WTIMER Timer Counter silabs com Building a more connected world Rev 1 1 678 ...

Page 679: ...apture in TIMERn_CC2_CCV In Compare PWM mode this bit indicates the polarity of the selected input to CC channel 2 These bits are cleared when CCMODE is written to 0b00 Off Value Mode Description 0 LOWRISE CC2 polarity low level rising edge 1 HIGHFALL CC2 polarity high level falling edge 25 CCPOL1 0 R CC1 Polarity In Input Capture mode this bit indicates the polarity of the edge that triggered cap...

Page 680: ...t capture mode and are cleared when CCMODE is written to 0b00 Off Value Description 0 TIMERn_CC1_CCV does not contain a valid capture value FIFO emp ty 1 TIMERn_CC1_CCV contains a valid capture value FIFO not empty 16 ICV0 0 R CC0 Input Capture Valid This bit indicates that TIMERn_CC0_CCV contains a valid capture value These bits are only used in input capture mode and are cleared when CCMODE is w...

Page 681: ...nt 8 CCVBV0 0 R CC0 CCVB Valid This field indicates that the TIMERn_CC0_CCVB registers contain data which have not been written to TIMERn_CC0_CCV These bits are only used in output compare PWM mode and are cleared when CCMODE is written to 0b00 Off Value Description 0 TIMERn_CC0_CCVB does not contain valid data 1 TIMERn_CC0_CCVB contains valid data which will be written to TIMERn_CC0_CCV on the ne...

Page 682: ...f TIMERn_CC1_CCVB 8 ICBOF0 0 R CC Channel 0 Input Capture Buffer Overflow Interrupt Flag This bit indicates that a new capture value has pushed an unread value out of TIMERn_CC0_CCVB 7 CC3 0 R CC Channel 3 Interrupt Flag This bit indicates that there has been an interrupt event on Compare Capture channel 3 6 CC2 0 R CC Channel 2 Interrupt Flag This bit indicates that there has been an interrupt ev...

Page 683: ...g Write 1 to set the ICBOF1 interrupt flag 8 ICBOF0 0 W1 Set ICBOF0 Interrupt Flag Write 1 to set the ICBOF0 interrupt flag 7 CC3 0 W1 Set CC3 Interrupt Flag Write 1 to set the CC3 interrupt flag 6 CC2 0 W1 Set CC2 Interrupt Flag Write 1 to set the CC2 interrupt flag 5 CC1 0 W1 Set CC1 Interrupt Flag Write 1 to set the CC1 interrupt flag 4 CC0 0 W1 Set CC0 Interrupt Flag Write 1 to set the CC0 int...

Page 684: ...terrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 7 CC3 0 R W1 Clear CC3 Interrupt Flag Write 1 to clear the CC3 interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 6 CC2 0 R W1 Clear CC2 Interrupt Flag Write 1 to clear th...

Page 685: ...ponding interrupt flags This feature must be enabled globally in MSC 0 OF 0 R W1 Clear OF Interrupt Flag Write 1 to clear the OF interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC Reference Manual TIMER WTIMER Timer Counter silabs com Building a more connected world Rev 1 1 685 ...

Page 686: ...ICBOF1 Interrupt Enable Enable disable the ICBOF1 interrupt 8 ICBOF0 0 RW ICBOF0 Interrupt Enable Enable disable the ICBOF0 interrupt 7 CC3 0 RW CC3 Interrupt Enable Enable disable the CC3 interrupt 6 CC2 0 RW CC2 Interrupt Enable Enable disable the CC2 interrupt 5 CC1 0 RW CC1 Interrupt Enable Enable disable the CC1 interrupt 4 CC0 0 RW CC0 Interrupt Enable Enable disable the CC0 interrupt 3 Rese...

Page 687: ...ue These bits hold the TOP value for the counter 20 5 9 TIMERn_TOPB Counter Top Value Buffer Register Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name TOPB Bit Name Reset Access Description 31 0 TOPB 0x00000000 RW Counter Top Value Buffer These bits hold the TOP buffer value Reference Manual TIMER WTIMER...

Page 688: ...et Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 TIMERLOCKKEY 0x0000 RWH Timer Lock Key Write any other value than the unlock code to lock TIMERn_CTRL TIMERn_CMD TIMERn_TOP TIMERn_CNT TIMERn_CCx_CTRL and TIMERn_CCx_CCV from editing Write the unlock code to unlock When reading the register bit 0 is set ...

Page 689: ... Enable Enable disable CC channel 1 complementary dead time insertion output connection to pin 8 CDTI0PEN 0 RW CC Channel 0 Complementary Dead Time Insertion Pin Enable Enable disable CC channel 0 complementary dead time insertion output connection to pin 7 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 CC3PEN 0 RW CC Channel 3 ...

Page 690: ... O Location Decides the location of the CC3 pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17...

Page 691: ...tion of the CC2 pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 ...

Page 692: ...ion of the CC1 pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 L...

Page 693: ...on of the CC0 pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 Lo...

Page 694: ...C24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Location 28 29 LOC29 Location 29 30 LOC30 Location 30 31 LOC31 Location 31 Reference Manual TIMER WTIMER Timer Counter silabs com Building a more connected world Rev 1 1 694 ...

Page 695: ...cation Decides the location of the CDTI2 pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LO...

Page 696: ...ion of the CDTI1 pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18...

Page 697: ...on of the CDTI0 pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LOC18 ...

Page 698: ...C24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Location 28 29 LOC29 Location 29 30 LOC30 Location 30 31 LOC31 Location 31 Reference Manual TIMER WTIMER Timer Counter silabs com Building a more connected world Rev 1 1 698 ...

Page 699: ...scription 0 PIN TIMERnCCx pin is selected 1 PRS PRS input selected by PRSSEL is selected 28 PRSCONF 0 RW PRS Configuration Select PRS pulse or level Value Mode Description 0 PULSE Each CC event will generate a one HFPERCLK cycle high pulse 1 LEVEL The PRS channel will follow CC out 27 26 ICEVCTRL 0x0 RW Input Capture Event Control These bits control when a Compare Capture PRS output pulse and inte...

Page 700: ...Channel 3 selected as input 4 PRSCH4 PRS Channel 4 selected as input 5 PRSCH5 PRS Channel 5 selected as input 6 PRSCH6 PRS Channel 6 selected as input 7 PRSCH7 PRS Channel 7 selected as input 8 PRSCH8 PRS Channel 8 selected as input 9 PRSCH9 PRS Channel 9 selected as input 10 PRSCH10 PRS Channel 10 selected as input 11 PRSCH11 PRS Channel 11 selected as input 15 14 Reserved To ensure compatibility...

Page 701: ...t Compare and PWM mode When this bit is set in Compare or PWM mode the output is set high when the counter is disabled When counting resumes this value will represent the initial value for the output If the bit is cleared the output will be cleared when the counter is disabled 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 OUTIN...

Page 702: ...ntents of the TIMERn_CCx_CCVB register will be written to TIMERn_CCx_CCV in the next cycle In compare mode this fields holds the compare value 20 5 17 TIMERn_CCx_CCVP CC Channel Value Peek Register Offset Bit Position 0x068 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name CCVP Bit Name Reset Access Description 31 0 CCVP 0x00000000...

Page 703: ... 0x00000000 RWH CC Channel Value Buffer In Input Capture mode this field holds the last capture value if the TIMERn_CCx_CCV register already contains an earlier unread capture value In Output Compare or PWM mode this field holds the CC buffer value which will be written to TIMERn_CCx_CCV on an update event if TIMERn_CCx_CCVB contains valid data Reference Manual TIMER WTIMER Timer Counter silabs co...

Page 704: ... DTAR 0 RW DTI Always Run This is used only for DTI channel 0 It Allows DTI channel 0 to keep running even when timer is stopped This is useful when its input source is PRS However here the undivided HFPERCLK is always used regardless of the programmed val ue in DTPRESC 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 4 DTPRSSEL 0...

Page 705: ...tive polarity for outputs 1 DTDAS 0 RW DTI Automatic Start up Functionality Configure DTI restart on debugger exit Value Mode Description 0 NORESTART No DTI restart on debugger exit 1 RESTART DTI restart on debugger exit 0 DTEN 0 RW DTI Enable Enable disable DTI Reference Manual TIMER WTIMER Timer Counter silabs com Building a more connected world Rev 1 1 705 ...

Page 706: ...T 0x00 RW DTI Rise time Set time span for the rising edge Value Description DTRISET Rise time of DTRISET 1 prescaled HFPERCLK cycles 7 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 0 DTPRESC 0x0 RW DTI Prescaler Setting Select prescaler for DTI Value Mode Description 0 DIV1 The HFPERCLK is undivided 1 DIV2 The HFPERCLK is divid...

Page 707: ...Bit Name Reset Access Description Reference Manual TIMER WTIMER Timer Counter silabs com Building a more connected world Rev 1 1 707 ...

Page 708: ... DTPRS1FSEL as a fault source 24 DTPRS0FEN 0 RW DTI PRS 0 Fault Enable Set this bit to 1 to enable PRS source 0 PRS channel determined by DTPRS0FSEL as a fault source 23 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 17 16 DTFA 0x0 RW DTI Fault Action Select fault action Value Mode Description 0 NONE No action on fault 1 INACTIVE...

Page 709: ...TPRS0FSEL 0x0 RW DTI PRS Fault Source 0 Select Select PRS channel for fault source 0 Value Mode Description 0 PRSCH0 PRS Channel 0 selected as fault source 0 1 PRSCH1 PRS Channel 1 selected as fault source 1 2 PRSCH2 PRS Channel 2 selected as fault source 2 3 PRSCH3 PRS Channel 3 selected as fault source 3 4 PRSCH4 PRS Channel 4 selected as fault source 4 5 PRSCH5 PRS Channel 5 selected as fault s...

Page 710: ...ut from the DTI 4 DTOGCDTI1EN 0 RW DTI CDTI1 Output Generation Enable This bit enables disables output generation for the CDTI1 output from the DTI 3 DTOGCDTI0EN 0 RW DTI CDTI0 Output Generation Enable This bit enables disables output generation for the CDTI0 output from the DTI 2 DTOGCC2EN 0 RW DTI CC2 Output Generation Enable This bit enables disables output generation for the CC2 output from th...

Page 711: ... is set to 1 The TIMER0_DTFAULTC register can be used to clear fault bits 2 DTDBGF 0 R DTI Debugger Fault This bit is set to 1 if a debugger fault has occurred and DTDBGFEN is set to 1 The TIMER0_DTFAULTC register can be used to clear fault bits 1 DTPRS1F 0 R DTI PRS 1 Fault This bit is set to 1 if a PRS 1 fault has occurred and DTPRS1FEN is set to 1 The TIMER0_DTFAULTC register can be used to cle...

Page 712: ...y with future devices always write bits to 0 More information in 1 2 Conven tions 3 TLOCKUPFC 0 W1 DTI Lockup Fault Clear Write 1 to this bit to clear core lockup fault 2 DTDBGFC 0 W1 DTI Debugger Fault Clear Write 1 to this bit to clear debugger fault 1 DTPRS1FC 0 W1 DTI PRS1 Fault Clear Write 1 to this bit to clear PRS 1 fault 0 DTPRS0FC 0 W1 DTI PRS0 Fault Clear Write 1 to this bit to clear PRS...

Page 713: ...0 LOCKKEY 0x0000 RWH DTI Lock Key Write any other value than the unlock code to lock TIMERn_ROUTE TIMERn_DTCTRL TIMERn_DTTIME and TIMERn_DTFC from editing Write the unlock code to unlock When reading the register bit 0 is set when the lock is ena bled Mode Value Description Read Operation UNLOCKED 0 TIMER DTI registers are unlocked LOCKED 1 TIMER DTI registers are locked Write Operation LOCK 0 Loc...

Page 714: ...for timing and output generation when most of the device is powered down allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum The LETIMER can be used to output a variety of waveforms with minimal software intervention It can also be connected to the Real Time Counter RTC using PRS and can be configured to start counting on compare matches f...

Page 715: ...SW PRS event Figure 21 1 LETIMER Overview 21 3 1 Timer The timer is started by setting command bit START in LETIMERn_CMD and stopped by setting the STOP command bit in the same register RUNNING in LETIMERn_STATUS is set as long as the timer is running The timer can also be started on external signals such as a compare match from the Real Time Counter If START and STOP are set at the same time STOP...

Page 716: ...e control of the operation of the timer including defining the number of times the counter should wrap around Four different repeat modes are available see Table 21 1 LETIMER Repeat Modes on page 716 Table 21 1 LETIMER Repeat Modes REPMODE Mode Description 0b00 Free running The timer runs until it is stopped 0b01 One shot The timer runs as long as LETI MERn_REP0 0 LETIMERn_REP0 is de cremented at ...

Page 717: ...OP 0 Wait for positive clock edge If COMP0TOP TOP COMP0 Else TOP 0xFFFF TOP Figure 21 2 LETIMER State Machine for Free running Mode Note that the CLEAR command bit in LETIMERn_CMD always has priority over other changes to LETIMERn_CNT When the clear command is used LETIMERn_CNT is set to 0 and an underflow event will not be generated when LETIMERn_CNT wraps around to the top value or 0xFFFF Since ...

Page 718: ... event occurs the timer decrement will not occur and the new value is assigned LETIMERn_REP0 can be written while the timer is running to allow the timer to run for longer periods at a time without stopping Figure 21 3 LETIMER One shot Repeat State Machine on page 718 RUNNING YES CNT 0 CNT CNT 1 NO REP0 2 YES NO STOP 1 REP0 0 CNT TOP If START REP0 REP0 1 If STOP RUNNING 0 Else if START RUNNING 1 E...

Page 719: ...value 6 6 times with period 200 then 3 times with period 50 A state machine for the buffered repeat mode is shown in Figure 21 4 LETIMER Buffered Repeat State Machine on page 719 REP1USED shown in the state machine is an internal variable that keeps track of whether the value in LETIMERn_REP1 has been loa ded into LETIMERn_REP0 or not The purpose of this is that a value written to LETIMERn_REP1 sh...

Page 720: ...puts at the same time The state machine for this repeat mode can be seen in Figure 21 5 LETIMER Double Repeat State Machine on page 720 RUNNING YES CNT 0 CNT CNT 1 NO REP0 2 And REP1 2 YES NO STOP 1 REP0 0 CNT TOP If REP0 0 REP0 REP0 1 If REP1 0 REP1 REP1 1 If STOP RUNNING 0 Else if START RUNNING 1 End if START 0 STOP 0 Wait for positive clock edge YES If COMP0TOP TOP COMP0 Else TOP 0xFFFF TOP NO ...

Page 721: ...RTMODE None Rising Falling Both PRS_START PRS_IN 11 0 PRSSTOPSEL LFACLKLETIMERn Synchronizer Edge Detect PRSSTOPMODE None Rising Falling Both PRS_STOP PRS_IN 11 0 PRSCLEARSEL LFACLKLETIMERn Synchronizer Edge Detect PRSCLEARMODE None Rising Falling Both PRS_CLEAR PRSSTARTEN PRSSTOPEN PRSCLEAREN Figure 21 7 LETIMER PRS Input Triggers 21 3 3 9 Debug If DEBUGRUN in LETIMERn_CTRL is cleared the LETIMER...

Page 722: ...ess of the state of the corresponding LETIMERn_REPx registers They will only be set active if the LETIMERn_REPx registers are nonzero however Note For free running mode LETIMERn_REP0 0 for output generation to be enabled The polarity of the outputs can be set individually by configuring OPOL0 and OPOL1 in LETIMERn_CTRL When these are cleared their respective outputs have a low idle value and a hig...

Page 723: ...oggles generated on the output CNT COMP0 3 3 3 2 3 1 3 0 3 3 3 2 3 1 3 0 3 3 3 2 3 1 3 0 Initial configuration UFIF UFIF UFIF Int flags set LFACLKLETIMERn LETn_O0 UFOA0 01 LETn_O0 UFOA0 10 LETn_O0 UFOA0 00 REP0 3 3 3 3 2 2 2 2 1 1 1 1 Stop REP0IF 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 0 3 Figure 21 9 LETIMER Repeated Counting Using the Double repeat mode output c...

Page 724: ... PRS channel 0 and LETn_O1 can be rout ed to PRS channel 1 Enabling the PRS connection can be done by setting SOURCESEL to LETIMERx and SIGSEL to LETIMERxCHn in PRS_CHx_CTRL The PRS register description can be found in 15 5 Register Description 21 3 6 Examples This section presents a couple of usage examples for the LETIMER Reference Manual LETIMER Low Energy Timer silabs com Building a more conne...

Page 725: ...ware does not have to update the registers between each pulse train For the example in Figure 21 11 LETIMER Triggered Operation on page 725 the initial values cause the LETIMER to generate two pulses with 3 cycle periods or a single pulse 3 cycles wide every time the LETIMER is started After the output has been generated the LETIMER stops and is ready to be triggered again CNT TOP0 TOP1 REP0 REP1 ...

Page 726: ... 2u REP0IF LFACLKLETIMERn LETn_O0 UFOA0 01 LETn_O1 UFOA0 10 Pulse Seq 1 Pulse Seq 2 Pulse Seq 3 4 4 4 4 4 4 2 2 2 2 2 0 0 2u Figure 21 12 LETIMER Continuous Operation The first two sequences are loaded into the LETIMER before the timer is started LETIMERn_COMP0 is set to 2 cycles 1 and LETIMERn_REP0 is set to 3 for the first sequence and the second sequence is loaded into the buffer registers i e ...

Page 727: ...FOA1 in LETIMERn_CTRL to 3 In PWM mode the output is set idle on timer un derflow and active on LETIMERn_COMP1 match so if for instance COMP0TOP 1 and OPOL0 0 in LETIMERn_CTRL LETI MERn_COMP0 determines the PWM period and LETIMERn_COMP1 determines the active period The PWM period in PWM mode is LETIMERn_COMP0 1 There is no special handling of the case where LETIMERn_COMP1 LE TIMERn_COMP0 so if LET...

Page 728: ...P0 RWH Repeat Counter Register 0 0x01C LETIMERn_REP1 RWH Repeat Counter Register 1 0x020 LETIMERn_IF R Interrupt Flag Register 0x024 LETIMERn_IFS W1 Interrupt Flag Set Register 0x028 LETIMERn_IFC R W1 Interrupt Flag Clear Register 0x02C LETIMERn_IEN RW Interrupt Enable Register 0x034 LETIMERn_SYNCBUSY R Synchronization Busy Register 0x040 LETIMERn_ROUTEPEN RW I O Routing Pin Enable Register 0x044 ...

Page 729: ...n 0 LETIMER is frozen in debug mode 1 LETIMER is running in debug mode 11 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 9 COMP0TOP 0 RW Compare Value 0 is Top Value When set the counter is cleared in the clock cycle after a compare match with compare channel 0 Value Description 0 The top value of the LETIMER is 65535 0xFFFF 1 Th...

Page 730: ... is toggled on CNT underflow 2 PULSE LETn_O0 is held active for one LFACLKLETIMER0 clock cycle on CNT underflow The output then returns to its idle value as defined by OPOL0 3 PWM LETn_O0 is set idle on CNT underflow and active on compare match with COMP1 1 0 REPMODE 0x0 RW Repeat Mode Allows the repeat counter to be enabled and disabled Value Mode Description 0 FREE When started the LETIMER count...

Page 731: ...put 0 Set to drive toggle output 0 to its idle value 2 CLEAR 0 W1 Clear LETIMER Set to clear LETIMER 1 STOP 0 W1 Stop LETIMER Set to stop LETIMER 0 START 0 W1 Start LETIMER Set to start LETIMER 21 5 3 LETIMERn_STATUS Status Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name RUNNING Bit Name Reset Access Des...

Page 732: ...n_COMP0 Compare Value Register 0 Async Reg For more information about asynchronous registers see 4 3 Access to Low Energy Peripherals Asynchronous Registers Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RWH Name COMP0 Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices alw...

Page 733: ...Compare Value 1 Compare and optionally buffered top value for LETIMER 21 5 7 LETIMERn_REP0 Repeat Counter Register 0 Async Reg For more information about asynchronous registers see 4 3 Access to Low Energy Peripherals Asynchronous Registers Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RWH Name REP0 Bit Name Reset ...

Page 734: ...3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 Access R R R R R Name REP1 REP0 UF COMP1 COMP0 Bit Name Reset Access Description 31 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 4 REP1 0 R Repeat Counter 1 Interrupt Flag Set when repeat counter 1 reaches zero 3 REP0 0 R Repeat Counter 0 Interrupt Flag...

Page 735: ...ys write bits to 0 More information in 1 2 Conven tions 4 REP1 0 W1 Set REP1 Interrupt Flag Write 1 to set the REP1 interrupt flag 3 REP0 0 W1 Set REP0 Interrupt Flag Write 1 to set the REP0 interrupt flag 2 UF 0 W1 Set UF Interrupt Flag Write 1 to set the UF interrupt flag 1 COMP1 0 W1 Set COMP1 Interrupt Flag Write 1 to set the COMP1 interrupt flag 0 COMP0 0 W1 Set COMP0 Interrupt Flag Write 1 t...

Page 736: ...REP0 interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 2 UF 0 R W1 Clear UF Interrupt Flag Write 1 to clear the UF interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 1 COMP1 0 R W1 Clear COMP1 Interrupt Flag Write 1 to ...

Page 737: ...COMP1 0 RW COMP1 Interrupt Enable Enable disable the COMP1 interrupt 0 COMP0 0 RW COMP0 Interrupt Enable Enable disable the COMP0 interrupt 21 5 13 LETIMERn_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name CMD Bit Name Reset Access Description 31 2 Reserved To ensure compatib...

Page 738: ...with future devices always write bits to 0 More information in 1 2 Conven tions 1 OUT1PEN 0 RW Output 1 Pin Enable When set output 1 of the LETIMER is enabled Value Description 0 The LETn_O1 pin is disabled 1 The LETn_O1 pin is enabled 0 OUT0PEN 0 RW Output 0 Pin Enable When set output 0 of the LETIMER is enabled Value Description 0 The LETn_O0 pin is disabled 1 The LETn_O0 pin is enabled Referenc...

Page 739: ...es the location of the LETIMER OUT1 pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 L...

Page 740: ...of the LETIMER OUT0 pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 LO...

Page 741: ...OC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Location 28 29 LOC29 Location 29 30 LOC30 Location 30 31 LOC31 Location 31 Reference Manual LETIMER Low Energy Timer silabs com Building a more connected world Rev 1 1 741 ...

Page 742: ...falling edge of the selected PRS input can clear the LETIMER 25 24 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 23 22 PRSSTOPMODE 0x0 RW PRS Stop Mode Determines mode for PRS input stop Value Mode Description 0 NONE PRS cannot stop the LETIMER 1 RISING Rising edge of selected PRS input can stop the LETIMER 2 FALLING Falling edge o...

Page 743: ...8 selected as input 9 PRSCH9 PRS Channel 9 selected as input 10 PRSCH10 PRS Channel 10 selected as input 11 PRSCH11 PRS Channel 11 selected as input 11 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 9 6 PRSSTOPSEL 0x0 RW PRS Stop Select Determines which PRS input can stop the LETIMER Value Mode Description 0 PRSCH0 PRS Channel 0 ...

Page 744: ...elected as input 2 PRSCH2 PRS Channel 2 selected as input 3 PRSCH3 PRS Channel 3 selected as input 4 PRSCH4 PRS Channel 4 selected as input 5 PRSCH5 PRS Channel 5 selected as input 6 PRSCH6 PRS Channel 6 selected as input 7 PRSCH7 PRS Channel 7 selected as input 8 PRSCH8 PRS Channel 8 selected as input 9 PRSCH9 PRS Channel 9 selected as input 10 PRSCH10 PRS Channel 10 selected as input 11 PRSCH11 ...

Page 745: ... is a 32 bit counter which operates on a low frequency oscillator and is capable of running in all energy modes It can provide periodic wakeup events and PRS signals which can be used to wake up peripherals from any energy mode The CRYOTIMER provides a very wide range of periods for the interrupts facilitating flexible ultra low energy operation Because of its simplicity the CRYOTIMER is a lower e...

Page 746: ... Block Overview on page 746 Interrupt Wakeup Event Counter PRS Prescaler PRESC PERIODSEL Edge Detector LFXO LFRCO ULFRCO CRYOCLK OSCSEL Figure 22 1 CRYOTIMER Block Overview Reference Manual CRYOTIMER Ultra Low Energy Timer Counter silabs com Building a more connected world Rev 1 1 746 ...

Page 747: ...145 6 hours DIV8 244 µs 12 days DIV16 488 µs 24 days DIV32 977 µs 48 days DIV64 1 95 ms 97 days DIV128 3 91 ms 194 days The 32 bit counter value of the CRYOTIMER can be read using the CRYOTIMER_CNT register The PRS output pulses of the CRYOTIMER are 1 CRYOCLK clock cycle wide However if the PRESC and PERIODSEL are both set to 0 the width of these pulses will be half CRYOCLK time period The CRYOTIM...

Page 748: ...Duration 0x008 CRYOTIMER_CNT R Counter Value 0x00C CRYOTIMER_EM4WUEN RW Wake Up Enable 0x010 CRYOTIMER_IF R Interrupt Flag Register 0x014 CRYOTIMER_IFS W1 Interrupt Flag Set Register 0x018 CRYOTIMER_IFC R W1 Interrupt Flag Clear Register 0x01C CRYOTIMER_IEN RW Interrupt Enable Register Reference Manual CRYOTIMER Ultra Low Energy Timer Counter silabs com Building a more connected world Rev 1 1 748 ...

Page 749: ...by 16 5 DIV32 LF Oscillator frequency divided by 32 6 DIV64 LF Oscillator frequency divided by 64 7 DIV128 LF Oscillator frequency divided by 128 4 2 OSCSEL 0x0 RW Select Low Frequency Oscillator These bits select the low frequency oscillator for the CRYOTIMER operation This field should be set after the oscillator to be selected is ready Value Mode Description 0 DISABLED Output is driven low 1 LF...

Page 750: ... Pre scaled clock cycles 6 Wakeup event after 64 Pre scaled clock cycles 7 Wakeup event after 128 Pre scaled clock cycles 8 Wakeup event after 256 Pre scaled clock cycles 9 Wakeup event after 512 Pre scaled clock cycles 10 Wakeup event after 1k Pre scaled clock cycles 11 Wakeup event after 2k Pre scaled clock cycles 12 Wakeup event after 4k Pre scaled clock cycles 13 Wakeup event after 8k Pre scal...

Page 751: ...t Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name CNT Bit Name Reset Access Description 31 0 CNT 0x00000000 R Counter Value These bits hold the Counter value 22 5 4 CRYOTIMER_EM4WUEN Wake Up Enable Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset ...

Page 752: ...t when the Wakeup event Interrupt occurs 22 5 6 CRYOTIMER_IFS Interrupt Flag Set Register Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access W1 Name PERIOD Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 PERIOD 0 W1 Se...

Page 753: ...eturns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 22 5 8 CRYOTIMER_IEN Interrupt Enable Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access RW Name PERIOD Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices al...

Page 754: ...is operating at low frequencies and with low total power consumption Using DMA and a timer the VDAC can be used to generate waveforms without any CPU intervention The VDAC is available down to Energy Mode 3 23 1 Introduction The Voltage Digital to Analog Converter VDAC can convert a digital value to an analog output voltage The VDAC is fully differential rail to rail with 12 bit resolution It has ...

Page 755: ...DAC_CLK cycles Individual refresh enable for each channel Interrupt generation on buffer empty or finished conversion Separate interrupt flags for each channel PRS output pulse on finished conversion Separate line for each channel DMA request on buffer empty Separate request for each channel Support for offset and gain calibration Output to dedicated pins or APORT bus Internal connections to ADC a...

Page 756: ...N AVDD IOVDD 2 V MIN AVDD IOVDD 23 3 3 Enabling and Disabling a Channel A VDAC channel is enabled by writing 1 to the CHxEN and disabled by writing 1 to CHxDIS in VDACn_CMD The channel enabled status can be read by polling the CHxENS bit in VDACn_STATUS This bit will go high immediately following a write to CHxEN After disabling a channel the CHxENS bit will stay high until the VDAC channel is com...

Page 757: ...ed to PRS or SWPRS a conversion can be started by an incoming pulse on the PRS channel selected in PRSSEL in VDACn_CHxCTRL The PRSASYNC bit in VDACn_CHxCTRL determines if the VDAC expects a PRS pulse coming from a synchronous or asynchronous PRS producer If TRIGMODE is programmed to REFRESH or SWREFRESH a conversion will start on an overflow of the internal refresh timer See 23 3 10 Refresh Timer ...

Page 758: ...nd configuring the APORTOUTSEL field to select the desired APORT The VDAC outputs also have direct internal connections to ADCs and ACMPs These outputs are always enabled and can be selected by configuring the input selection for the ADC ACMP In sample off mode the VDAC will only drive the output for the duration programmed in SETTLETIME in VDACn_OPAx_TIMER regis ter for each incoming conversion t...

Page 759: ...as an internal clock prescaler which can divide the input clock by any factor between 1 and 128 by setting the PRESC field in VDACn_CTRL The resulting DAC_CLK is used by the converter core and the frequency is given by Figure 23 4 VDAC Clock Prescaling on page 759 fDAC_CLK fIN_CLK PRESC 1 Figure 23 4 VDAC Clock Prescaling where fIN_CLK is the input clock frequency The fDAC_CLK must be programmed t...

Page 760: ...el s in order to use sine generation mode The TRIGMODE bitfield needs to be programmed to PRS for any channel used for sine genera tion mode The other trigger modes are not supported The SINE wave will be output on channel 0 and therefore requires that this channel is enabled by writing 1 to CH0EN in the VDACn_CMD register If DIFF is set in VDACn_CTRL the sine wave will be output on both channels ...

Page 761: ...ompletely standalone For a detailed description see the OPAMP chapter 23 3 19 Calibration The VDAC contains a calibration register VDACn_CAL where calibration values for both offset and gain correction can be written The required gain calibration values depend on the chosen reference and on whether the main or alternative VDAC output is used The Device Information page provides the required trim v...

Page 762: ...tion A change in any of these might require a re calibration VDACn_CTRL REFSEL VDACn_OPAx_OUT MAINOUTEN VDACn_OPAx_OUT ALTOUTEN VDACn_OPAx_CTRL DRIVESTRENGTH 23 3 20 Warmup Mode If the WARMUPMODE field in VDACn_CTRL is set to KEEPINSTANDBY the VDAC keeps internal bias currents running between con versions It does not reduce the startup time but it can help reduce noise from the VDAC to other analo...

Page 763: ...al Amplifier APORT Conflict Status Register 0x0A8 VDACn_OPA0_CTRL RW Operational Amplifier Control Register 0x0AC VDACn_OPA0_TIMER RW Operational Amplifier Timer Control Register 0x0B0 VDACn_OPA0_MUX RW Operational Amplifier Mux Configuration Register 0x0B4 VDACn_OPA0_OUT RW Operational Amplifier Output Configuration Register 0x0B8 VDACn_OPA0_CAL RW Operational Amplifier Calibration Register 0x0C0...

Page 764: ...bits to 0 More information in 1 2 Conven tions 28 WARMUPMODE 0 RW Warm up Mode Select Warm up Mode for DAC Value Mode Description 0 NORMAL DAC is shut off after each sample off conversion 1 KEEPINSTANDBY DAC is kept in standby mode between sample off conversions 27 26 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 25 24 REFRESHPERIO...

Page 765: ...eference 1 2V5LN Internal low noise 2 5 V bandgap reference 2 1V25 Internal 1 25 V bandgap reference 3 2V5 Internal 2 5 V bandgap reference 4 VDD AVDD reference 6 EXT External pin reference 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 6 CH0PRESCRST 0 RW Channel 0 Start Reset Prescaler Select if prescaler determining DAC_CLK rate...

Page 766: ...atibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 DIFF 0 RW Differential Mode Select single ended or differential mode Value Description 0 Single ended output 1 Differential output Reference Manual VDAC Digital to Analog Converter silabs com Building a more connected world Rev 1 1 766 ...

Page 767: ... 0 R OPA1 Warm Status OPA1 is warm and output is enabled In PRS triggered mode this status flag is not used and remains 0 24 OPA0WARM 0 R OPA0 Warm Status OPA0 is warm and output is enabled In PRS triggered mode this status flag is not used and remains 0 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 OPA1ENS 0 R OPA1 Enable...

Page 768: ...it is set when there is space for new data in CH1DATA 2 CH0BL 1 R Channel 0 Buffer Level This bit is set when there is space for new data in CH0DATA 1 CH1ENS 0 R Channel 1 Enabled Status This bit is set when channel 1 is enabled 0 CH0ENS 0 R Channel 0 Enabled Status This bit is set when channel 0 is enabled Reference Manual VDAC Digital to Analog Converter silabs com Building a more connected worl...

Page 769: ...5 triggers a conversion 6 PRSCH6 PRS ch 6 triggers a conversion 7 PRSCH7 PRS ch 7 triggers a conversion 8 PRSCH8 PRS ch 8 triggers a conversion 9 PRSCH9 PRS ch 9 triggers a conversion 10 PRSCH10 PRS ch 10 triggers a conversion 11 PRSCH11 PRS ch 11 triggers a conversion 11 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 8 PRSASYNC 0...

Page 770: ... Channel 0 is triggered by LESENSE 3 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 CONVMODE 0 RW Conversion Mode Configure conversion mode Value Mode Description 0 CONTINUOUS DAC channel 0 is set in continuous mode 1 SAMPLEOFF DAC channel 0 is set in sample off mode Reference Manual VDAC Digital to Analog Converter silabs com B...

Page 771: ...5 triggers a conversion 6 PRSCH6 PRS ch 6 triggers a conversion 7 PRSCH7 PRS ch 7 triggers a conversion 8 PRSCH8 PRS ch 8 triggers a conversion 9 PRSCH9 PRS ch 9 triggers a conversion 10 PRSCH10 PRS ch 10 triggers a conversion 11 PRSCH11 PRS ch 11 triggers a conversion 11 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 8 PRSASYNC 0...

Page 772: ... Channel 1 is triggered by LESENSE 3 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 CONVMODE 0 RW Conversion Mode Configure conversion mode Value Mode Description 0 CONTINUOUS DAC channel 1 is set in continuous mode 1 SAMPLEOFF DAC channel 1 is set in sample off mode Reference Manual VDAC Digital to Analog Converter silabs com B...

Page 773: ... OPA1DIS 0 W1 OPA1 Disable Disables OPA1 18 OPA1EN 0 W1 OPA1 Enable Enables OPA1 17 OPA0DIS 0 W1 OPA0 Disable Disables OPA0 16 OPA0EN 0 W1 OPA0 Enable Enables OPA0 15 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 CH1DIS 0 W1 DAC Channel 1 Disable Disables DAC Channel 1 2 CH1EN 0 W1 DAC Channel 1 Enable Enables DAC Channel 1 1 C...

Page 774: ...RS triggered mode the negative edge of the PRS pulse came before the OPA output was valid 20 OPA0PRSTIME DERR 0 R OPA0 PRS Trigger Mode Error Interrupt Flag Indicates that in TIMED PRS triggered mode the negative edge of the PRS pulse came before the OPA output was valid 19 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 17 OPA1AP...

Page 775: ... 0 data underflow 3 CH1OF 0 R Channel 1 Data Overflow Interrupt Flag Indicates channel 1 data overflow 2 CH0OF 0 R Channel 0 Data Overflow Interrupt Flag Indicates channel 0 data overflow 1 CH1CD 0 R Channel 1 Conversion Done Interrupt Flag Indicates channel 1 conversion complete 0 CH0CD 0 R Channel 0 Conversion Done Interrupt Flag Indicates channel 0 conversion complete Reference Manual VDAC Digi...

Page 776: ... bits to 0 More information in 1 2 Conven tions 21 OPA1PRSTIME DERR 0 W1 Set OPA1PRSTIMEDERR Interrupt Flag Write 1 to set the OPA1PRSTIMEDERR interrupt flag 20 OPA0PRSTIME DERR 0 W1 Set OPA0PRSTIMEDERR Interrupt Flag Write 1 to set the OPA0PRSTIMEDERR interrupt flag 19 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 17 OPA1APORTC...

Page 777: ...t the CH1OF interrupt flag 2 CH0OF 0 W1 Set CH0OF Interrupt Flag Write 1 to set the CH0OF interrupt flag 1 CH1CD 0 W1 Set CH1CD Interrupt Flag Write 1 to set the CH1CD interrupt flag 0 CH0CD 0 W1 Set CH0CD Interrupt Flag Write 1 to set the CH0CD interrupt flag Reference Manual VDAC Digital to Analog Converter silabs com Building a more connected world Rev 1 1 777 ...

Page 778: ...PRSTIMEDERR Interrupt Flag Write 1 to clear the OPA1PRSTIMEDERR interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 20 OPA0PRSTIME DERR 0 R W1 Clear OPA0PRSTIMEDERR Interrupt Flag Write 1 to clear the OPA0PRSTIMEDERR interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flag...

Page 779: ...eading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 2 CH0OF 0 R W1 Clear CH0OF Interrupt Flag Write 1 to clear the CH0OF interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 1 CH1CD 0 R W1 Clear CH1CD Interrupt Flag Write 1 to clear the CH...

Page 780: ...ure devices always write bits to 0 More information in 1 2 Conven tions 21 OPA1PRSTIME DERR 0 RW OPA1PRSTIMEDERR Interrupt Enable Enable disable the OPA1PRSTIMEDERR interrupt 20 OPA0PRSTIME DERR 0 RW OPA0PRSTIMEDERR Interrupt Enable Enable disable the OPA0PRSTIMEDERR interrupt 19 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 17 ...

Page 781: ... CH1CD interrupt 0 CH0CD 0 RW CH0CD Interrupt Enable Enable disable the CH0CD interrupt 23 5 10 VDACn_CH0DATA Channel 0 Data Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x800 Access RWH Name DATA Bit Name Reset Access Description 31 12 Reserved To ensure compatibility with future devices always write bits to 0 More ...

Page 782: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x800 0x800 Access W W Name CH1DATA CH0DATA Bit Name Reset Access Description 31 28 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 27 16 CH1DATA 0x800 W Channel 1 Data Data written to this register will be written to DATA in VDACn_CH1DATA 15 ...

Page 783: ...ompatibility with future devices always write bits to 0 More information in 1 2 Conven tions 13 8 GAINERRTRIM 0x20 RW Gain Error Trim Value This register contains the fine gain error trim for CH0 and coarse gain error trim for CH1 Program with Device Information value found in DEVINFO_VDACnMAINCAL or DEVINFO_VDACnALTCAL depending on chosen reference and choice of main versus alternative output usa...

Page 784: ...PORT3Y is Requested Reports if the bus connected to APORT3Y is being requested from the APORT 6 APORT3XREQ 0 R 1 If the Bus Connected to APORT3X is Requested Reports if the bus connected to APORT3X is being requested from the APORT 5 APORT2YREQ 0 R 1 If the Bus Connected to APORT2Y is Requested Reports if the bus connected to APORT2Y is being requested from the APORT 4 APORT2XREQ 0 R 1 If the Bus ...

Page 785: ... connected to APORT3Y is is also being requested by another peripheral 6 APORT3XCONFLICT 0 R 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral Reports if the bus connected to APORT3X is is also being requested by another peripheral 5 APORT2YCONFLICT 0 R 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral Reports if the bus connected to APORT2Y is is also...

Page 786: ...ction the external device mastering the bus has configured for the APORT bus Value Description 0 Bus mastering enabled 1 Bus mastering disabled 20 APORTXMASTER DIS 0 RW APORT Bus Master Disable Determines if the OPAx will request the APORT bus X with POSSEL NEGSEL or APORTOUTSEL This bit allows multiple APORT connected devices to monitor the same APORT bus simultaneously by allowing the OPAx to no...

Page 787: ...A 11 PRSCH11 PRS ch 11 triggers OPA 9 PRSMODE 0 RW OPAx PRS Trigger Mode PRS trigger mode of OPA Value Mode Description 0 PULSED PULSED trigger is considered a regular asynchronous pulse that starts OPA warmup sequence The end of warmup sequence is controlled by timeout settings in OPAxTIMER 1 TIMED TIMED trigger is considered a pulse long enough to provide OPA warmup sequence The end of warmup se...

Page 788: ...arity when input is low 2 INCBW 1 RW OPAx Unity Gain Bandwidth Scale Unity gain bandwidth scale Value Description 0 No scaling 1 When set the unity gain bandwidth will be scaled by factor of 2 5 use ful to make OPA operate faster for closed loop gain setting greater than 3x 1 0 DRIVESTRENGTH 0x2 RW OPAx Operation Mode Selects OPAx operation mode Value Description 0 Lower accuracy with Low drive st...

Page 789: ...01 RW OPAx Output Settling Timeout Value Number of clock cycles to drive the output 15 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 14 8 WARMUPTIME 0x07 RW OPAx Warmup Time Count Value OPAx warmup timeout value 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 5 0 ...

Page 790: ... 23 21 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 20 GAIN3X 1 RW OPAx Dedicated 3x Gain Resistor Ladder Selects gain of 3x Value Description 0 Disables 3x gain ladder 1 Enables and sets the gain to 3x If this is set to 1 RESSEL will only be used externally by other opamps By default this is set to 1 for dac to work properly For ...

Page 791: ...63 Select APORT1YCH31 APORT2YCH0 80 Select APORT2YCH0 APORT2YCH2 81 Select APORT2YCH2 APORT2YCH4 82 Select APORT2YCH3 APORT2YCH30 95 Select APORT2YCH30 APORT3YCH1 112 Select APORT3YCH1 APORT3YCH3 113 Select APORT3YCH3 APORT3YCH5 114 Select APORT3YCH5 APORT3YCH31 127 Select APORT3YCH31 APORT4YCH0 144 Select APORT4YCH0 APORT4YCH2 145 Select APORT4YCH2 APORT4YCH4 146 Select APORT4YCH4 APORT4YCH30 159...

Page 792: ...Select APORT3XCH0 APORT3XCH2 97 Select APORT3XCH2 APORT3XCH4 98 Select APORT3XCH4 APORT3XCH30 111 Select APORT3XCH30 APORT4XCH1 128 Select APORT4XCH1 APORT4XCH3 129 Select APORT4XCH3 APORT4XCH5 130 Select APORT4XCH5 APORT4XCH31 143 Select APORT4XCH31 DISABLE 240 Input disabled DAC 241 DAC as input POSPAD 242 POS PAD as input OPANEXT 243 NEXTOUT x 1 as input For OPA0 not applicable OPATAP 244 OPAxT...

Page 793: ...T1YCH1 48 Select APORT1YCH1 APORT1YCH3 49 Select APORT1YCH3 APORT1YCH5 50 Select APORT1YCH5 APORT1YCH31 63 Select APORT1YCH31 APORT2YCH0 80 Select APORT2YCH0 APORT2YCH2 81 Select APORT2YCH2 APORT2YCH4 82 Select APORT2YCH3 APORT2YCH30 95 Select APORT2YCH30 APORT3YCH1 112 Select APORT3YCH1 APORT3YCH3 113 Select APORT3YCH3 APORT3YCH5 114 Select APORT3YCH5 APORT3YCH31 127 Select APORT3YCH31 APORT4YCH0...

Page 794: ... OPAx Main and Alternative Output Short Set this to short circuit main and alternative outputs This will keep the outputs shorted even when the VDAC is disabled 2 APORTOUTEN 0 RW OPAx Aport Output Enable Set this to enable aport output of OPAx 1 ALTOUTEN 0 RW OPAx Alternative Output Enable Set this to enable alternative output of OPAx 0 MAINOUTEN 1 RW OPAx Main Output Enable Set this to enable mai...

Page 795: ...2 Conven tions 18 17 GM3 0x0 RW Gm3 Trim Value Gm trim code of OPAMP stage 3 Additional trim for OPAMP stage 3 Program with value obtained from Device Information page DEVINFO_OPAxCALn depending on OPAMP number and chosen DRIVESTRENGTH 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 13 GM 0x4 RW Gm Trim Value Gm trim value comm...

Page 796: ...nsation Cap Cm1 Trim Value Program with value obtained from Device Information page DEVINFO_OPAxCALn depending on OPAMP number and chosen DRIVESTRENGTH Reference Manual VDAC Digital to Analog Converter silabs com Building a more connected world Rev 1 1 796 ...

Page 797: ...le general purpose opamps suitable for simple filters and buffer applications The 2 opamps can be configured to support various operational amplifier functions through a network of muxes with possibilities of selecting ranges of on chip non inverting and inverting gain configurations and selecting between outputs to various destinations The opamps can also be config ured with external feedback in ...

Page 798: ...24 1 OPAMP System Overview There is a set of input muxes for each opamp making it possible to select various input sources A more detailed view of the 2 opamps including the mux network is shown in Figure 24 2 OPAMP Overview on page 799 The POSSEL mux connected to the positive input makes it possible to select a pin another opamp output or tap from the resistor network Similarly the NEGSEL mux on ...

Page 799: ...3Y APORT4Y Figure 24 2 OPAMP Overview 24 3 1 Opamp Configuration Since two of the 2 OPAMPs OPA0 OPA1 are part of the VDAC the opamp configuration registers are located in the VDAC Each OPAMP can be enabled by setting OPAxEN in VDACn_CMD and can be disabled by setting OPAxDIS in VDACn_CMD The ena bled status of each OPAMP can be read by polling the OPAxENS bit in VDACn_STATUS OPAxENS goes high imme...

Page 800: ...AMP Warmup Time DRIVESTRENGTH WARMUPTIME µs 0 100 1 85 2 8 3 6 24 3 1 3 Settle Time After an opamp is enabled and the warmed up time has elapsed the output settles externally The settle period is programmable with SETTLETIME in VDACn_OPAx_TIME The OPAxOUTVALID bit in VDACn_STATUS is set when the settle period has completed When in use by the VDAC the default settling time is used The settling peri...

Page 801: ...of input muxes The mux connected to the positive input is configured by the POSSEL bit field in the VDACn_OPAx_MUX register Similarly the mux connected to the negative input is configured by setting the NEGSEL bit field in VDACn_OPAx_MUX The input into the resistor ladder can be configured by setting the RESINMUX bit field in VDACn_OPAx_MUX 24 3 1 8 Output Configuration Each opamp has three output...

Page 802: ...h the NEGMUX of the ADC See 26 3 7 Input Selection in the ADC chapter for information on how to configure the ADC input mux In addition OPA0 and OPA1 are internally routed to both the POSMUX and NEGMUX of ACMP See 25 3 6 Input Selection in the ACMP chapter for information on how to configure the ACMP input mux The main and alternate outputs of each opamp can be shorted together by setting the SHOR...

Page 803: ...ore the output to opamp is valid The interrupt flag is enabled by the OPAx ERRPRSMODE bit in VDACn_IEN An interrupt can also be requested when an APORT bus conflict occurs if the OPAxAPORTCONFLICT interrupt flag in VDACn_IF is set and enabled through by the OPAxAPORTCONFLICT bit in VDACn_IEN One of two aynchronous PRS outputs can be enabled for each opamp by setting PRSOUTMODE in VDACn_OPAx_CTRL I...

Page 804: ...uration OPA Bitfields OPA Configuration OPAx POSSEL OPATAP NEXTOUT POSPADx APORT 1 4 X OPAx NEGSEL UG OPAx RESINMUX DISABLE 24 3 4 3 Inverting Input PGA Figure 24 5 Inverting Input PGA Overview on page 804 shows the inverting input PGA configuration In this mode the negative input is connected to the resistor ladder by setting the NEGSEL bit field to OPATAP in the VDACn_OPAx_MUX register This sett...

Page 805: ...Cn_OPAx_OUT register R1 R2 VIN VOUT VOUT VIN 1 R2 R1 Figure 24 6 Non inverting PGA Overview Table 24 7 Non inverting PGA Configuration OPA Bitfields OPA Configuration OPAx POSSEL NEXTOUT POSPADx APORT 1 4 X OPAx NEGSEL OPATAP OPAx RESINMUX VSS NEGPAD 24 3 4 5 Cascaded Inverting PGA This mode enables the opamp signals to be internally configured to cascade two or more opamps in inverting mode as sh...

Page 806: ...n OPA0 POSSEL POSPAD0 APORT 1 4 X OPA0 NEGSEL OPATAP OPA0 RESINMUX NEGPAD0 OPA1 POSSEL POSPAD1 APORT 1 4 X OPA1 NEGSEL OPATAP OPA1 RESINMUX OPANEXT OPA2 POSSEL POSPAD2 APORT 1 4 X OPA2 NEGSEL OPATAP OPA2 RESINMUX OPANEXT 24 3 4 6 Cascaded Non inverting PGA This mode enables the opamp signals to be internally configured to cascade two or more opamps in non inverting mode as shown in Figure 24 8 Cas...

Page 807: ...p Differential Amplifier Overview on page 808 When using OPA0 and OPA1 the positive input of OPA0 can be connected to any input by setting the POSSEL bit field in VDACn_OPA0_MUX The OPA0 feedback path must be configured for unity gain by setting the NEGSEL bit field to UG in VDACn_OPA0_MUX In addition the OPA0 RESINMUX bit field must be set to DIS ABLED The OPA0 NEXTOUT output must be connected to...

Page 808: ...s to be internally configured to form a three opamp differential amplifier as shown in Figure 24 10 Three Op amp Differential Amplifier Overview on page 809 For both OPA0 and OPA1 the positive input can be connected to any input by configuring the OPA0 POSSEL and OPA1 POSSEL bitfields in VDACn_OPA0_MUX and VDACn_OPA1_MUX respectiv ley The OPA0 and OPA1 feedback paths must be configured for unity g...

Page 809: ...uration OPA OPA Bitfields OPA Configuration OPA0 POSSEL POSPAD0 APORT 1 4 X OPA0 NEGSEL UG OPA0 RESINMUX DISABLE OPA1 POSSEL POSPAD1 APORT 1 4 X OPA1 NEGSEL UG OPA1 RESINMUX DISABLE OPA2 POSSEL OPATAP OPA2 NEGSEL OPATAP OPA2 RESINMUX OPANEXT 24 3 4 9 Instrumentation Amplifier OPA0 and OPA1 can form a fully differential instrumentation amplifier by setting RESINMUX to CENTER for both opamps in VDAC...

Page 810: ... to drive pins through the alternative output network or the APORT The ADC can sample pins that the opamps are driving through the APORT R1 R2 VIP VOUTP VIP 1 R2 R1 or VOUTP VIP Unity Gain VOUTN VIN 1 R2 R1 or VOUTN VIN Unity Gain R1 R2 VIN Figure 24 12 Dual Buffer ADC Driver Overview Table 24 14 Dual Buffer ADC Driver Configuration OPA OPA Bitfields OPA Configuration OPAx POSSEL POSPADx APORT 1 4...

Page 811: ... 23 4 Register Map in the VDAC chapter 24 5 Register Description The register description of the opamp can be found in 23 5 Register Description in the VDAC chapter Reference Manual OPAMP Operational Amplifier silabs com Building a more connected world Rev 1 1 811 ...

Page 812: ...le as 100 nA the ACMP can wake up the system when input signals pass the threshold The analog compa rator can compare two analog signals or one analog signal and a highly configurable internal reference 25 1 Introduction The Analog Comparator compares the voltage of two analog inputs and outputs a digital signal indicating which input voltage is higher Inputs can either be from internal references...

Page 813: ...p references Selectable hysteresis 8 values Values can be positive or negative Dividable references have scale for both both output values allowing for even larger hysteresis Selectable response time Asynchronous interrupt generation on selectable edges Rising edge Falling edge Both edges Operational in EM0 Active down to EM3 Stop Dedicated capacitive sense mode with up to 8 inputs Adjustable inte...

Page 814: ...ESSEL VDAC0 channel 0 OPA0 VDAC0 channel 1 OPA1 Figure 25 1 ACMP Overview The comparator has two analog inputs one positive and one negative When the comparator is active the output indicates which of the two input voltages is higher When the voltage on the positive input is higher than the voltage on the negative input the digital output is high and vice versa The output of the comparator can be ...

Page 815: ...will be detected EM1 can still be entered during warm up After the warm up period is completed interrupts will be detected in EM2 and EM3 25 3 3 Response Time There is a delay from when the input voltage changes polarity to when the output toggles This delay is called the response time and can be altered by increasing or decreasing the bias current to the comparator through the BIASPROG and FULLBI...

Page 816: ...ut a 1 if POSSEL NEGSEL HYST There are two hysteresis registers ACMPn_HYSTERESIS0 and ACMPn_HYSTERESIS1 as the ACMP supports asymmetric hystere sis ACMPn_HYSTERESIS0 are the hysteresis values used when the comparator output is 0 ACMPn_HYSTERESIS1 are the values used when the comparator output is 1 The user must set both registers to the same values if symmetric hysteresis is desired Along with the...

Page 817: ...r only X bus selections can be made for POSSEL The resistor only physically exists on the positive input of the com parator The user may also select from a number of internal voltages VADIV and VBDIV are two dividable voltages VADIV can be VACMPVDD divided or the user can choose to select inputs from a number of APORT buses VBDIV consists of two dividable band gap references of either 1 25V or 2 5...

Page 818: ...touched By measuring the output frequency with a timer via the PRS the change in capacitance can be detected The analog comparator contains a feedback loop including an optional internal resistor This resistor is enabled by setting the CSRE SEN bit in ACMPn_INPUTSEL The resistance can be set to any of 8 values by configuring the CSRESSEL bits in ACMPn_INPUTSEL The source for VADIV is set to VACMPV...

Page 819: ... VDD Voltage Divider ACMPn_HSYTERESIS1 VADIV ACMPn_HYSTERESIS0 VADIV time I O voltage ACMPOUT Figure 25 5 Capacitive Sensing Setup Reference Manual ACMP Analog Comparator silabs com Building a more connected world Rev 1 1 819 ...

Page 820: ...o help debugging over utilization of APORT resources the ACMP provides a number of status registers The ACMPn_APOR TREQ gives the user visibility into what APORT buses the ACMP is requesting given the setting of registers ACMPn_INPUTSEL and ACMPn_CTRL ACMPn_APORTCONFLICT indicates if any of the selections are in conflict internally or externally For example if the user selects APORT1XCH0 for POSSE...

Page 821: ...e configuration in ACMP_HYSTERESIS0 HYSTERESIS1 will be used To enable the external override interface these steps must be performed Configure the parts of the ACMP that will not be overridden i e everything except ACMP_INPUTSEL_POSSEL and possibly ACMP_HYSTERESIS0 HYSTERESIS1 Make sure ACMP_CTRL_EN is set Configure and enable the external override interface in ACMP_EXTIFCTRL Check for APORT confl...

Page 822: ...served To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 IFALL 0 RW Falling Edge Interrupt Sense Set this bit to 1 to set the EDGE interrupt flag on falling edges of comparator output Value Mode Description 0 DISABLED Interrupt flag is not set on falling edges 1 ENABLED Interrupt flag is set on falling edges 20 IRISE 0 RW Rising Edge Interru...

Page 823: ...Master Disable for Bus Selected By VASEL Determines if the ACMP will request the X or Y APORT bus selected by VASEL This bit allows multiple APORT connected devices to monitor the same APORT bus simultaneously by allowing the ACMP to not master the selected bus When 1 the determination is expected to be from another peripheral and the ACMP only passively looks at the bus When 1 the selection of ch...

Page 824: ...ng disabled 7 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 GPIOINV 0 RW Comparator GPIO Output Invert Set this bit to 1 to invert the comparator alternate function output to GPIO Value Mode Description 0 NOTINV The comparator output to GPIO is not inverted 1 INV The comparator output to GPIO is inverted 2 INACTVAL 0 RW Inactiv...

Page 825: ...acitive sense resistor value 2 3 RES3 Internal capacitive sense resistor value 3 4 RES4 Internal capacitive sense resistor value 4 5 RES5 Internal capacitive sense resistor value 5 6 RES6 Internal capacitive sense resistor value 6 7 RES7 Internal capacitive sense resistor value 7 27 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 26 ...

Page 826: ...2 APORT1YCH3 0x23 APORT1Y Channel 3 APORT1XCH4 0x24 APORT1X Channel 4 APORT1YCH5 0x25 APORT1Y Channel 5 APORT1XCH30 0x3e APORT1X Channel 30 APORT1YCH31 0x3f APORT1Y Channel 31 15 8 NEGSEL 0x00 RW Negative Input Select Select negative input APORT0XCH0 0x00 Dedicated APORT0X Channel 0 APORT0XCH1 0x01 Dedicated APORT0X Channel 1 APORT0XCH2 0x02 Dedicated APORT0X Channel 2 APORT0XCH15 0x0f Dedicated A...

Page 827: ...PORT2Y Channel 30 APORT2XCH31 0x5f APORT2X Channel 31 APORT3XCH0 0x60 APORT3X Channel 0 APORT3YCH1 0x61 APORT3Y Channel 1 APORT3XCH2 0x62 APORT3X Channel 2 APORT3YCH3 0x63 APORT3Y Channel 3 APORT3XCH4 0x64 APORT3X Channel 4 APORT3YCH5 0x65 APORT3Y Channel 5 APORT3XCH30 0x7e APORT3X Channel 30 APORT3YCH31 0x7f APORT3Y Channel 31 APORT4YCH0 0x80 APORT4Y Channel 0 APORT4XCH1 0x81 APORT4X Channel 1 AP...

Page 828: ...el 1 APORT0YCH2 0x12 Dedicated APORT0Y Channel 2 APORT0YCH15 0x1f Dedicated APORT0Y Channel 15 APORT1XCH0 0x20 APORT1X Channel 0 APORT1YCH1 0x21 APORT1Y Channel 1 APORT1XCH2 0x22 APORT1X Channel 2 APORT1YCH3 0x23 APORT1Y Channel 3 APORT1XCH4 0x24 APORT1X Channel 4 APORT1YCH5 0x25 APORT1Y Channel 5 APORT1XCH30 0x3e APORT1X Channel 30 APORT1YCH31 0x3f APORT1Y Channel 31 APORT2YCH0 0x40 APORT2Y Chann...

Page 829: ...RT4XCH1 0x81 APORT4X Channel 1 APORT4YCH2 0x82 APORT4Y Channel 2 APORT4XCH3 0x83 APORT4X Channel 3 APORT4YCH4 0x84 APORT4Y Channel 4 APORT4XCH5 0x85 APORT4X Channel 5 APORT4YCH30 0x9e APORT4Y Channel 30 APORT4XCH31 0x9f APORT4X Channel 31 DACOUT0 0xf2 DAC Channel 0 Output DACOUT1 0xf3 DAC Channel 1 Output VLP 0xfb Low Power Sampled Voltage VBDIV 0xfc Divided VB Voltage VADIV 0xfd Divided VA Voltag...

Page 830: ...More information in 1 2 Conven tions 3 EXTIFACT 0 R External Override Interface Active This bit is set when the external override interface is ready to use 2 APORTCONFLICT 0 R APORT Conflict Output 1 if any of the APORT BUSes being requested by the ACMPn are also being requested by another peripheral 1 ACMPOUT 0 R Analog Comparator Output Analog comparator output value 0 ACMPACT 0 R Analog Compara...

Page 831: ...Triggered Interrupt Flag Indicates that there has been a rising or falling edge on the analog comparator output 25 5 5 ACMPn_IFS Interrupt Flag Set Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access W1 W1 W1 Name APORTCONFLICT WARMUP EDGE Bit Name Reset Access Description 31 3 Reserved To ensure compatibility ...

Page 832: ...NFLICT interrupt flag Reading returns the value of the IF and clears the corresponding inter rupt flags This feature must be enabled globally in MSC 1 WARMUP 0 R W1 Clear WARMUP Interrupt Flag Write 1 to clear the WARMUP interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 0 EDGE 0 R W1 Clear EDGE Interrupt Fla...

Page 833: ...31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 APORTCONFLICT 0 RW APORTCONFLICT Interrupt Enable Enable disable the APORTCONFLICT interrupt 1 WARMUP 0 RW WARMUP Interrupt Enable Enable disable the WARMUP interrupt 0 EDGE 0 RW EDGE Interrupt Enable Enable disable the EDGE interrupt Reference Manual ACMP Analog Comparator silab...

Page 834: ...sted from the APORT 6 APORT3XREQ 0 R 1 If the Bus Connected to APORT3X is Requested Reports if the bus connected to APORT3X is being requested from the APORT 5 APORT2YREQ 0 R 1 If the Bus Connected to APORT2Y is Requested Reports if the bus connected to APORT2Y is being requested from the APORT 4 APORT2XREQ 0 R 1 If the Bus Connected to APORT2X is Requested Reports if the bus connected to APORT2X ...

Page 835: ...s is also being requested by another peripheral 6 APORT3XCONFLICT 0 R 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral Reports if the bus connected to APORT3X is is also being requested by another peripheral 5 APORT2YCONFLICT 0 R 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral Reports if the bus connected to APORT2Y is is also being requested by ano...

Page 836: ... 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral Reports if the bus connected to APORT0X is is also being requested by another peripheral Reference Manual ACMP Analog Comparator silabs com Building a more connected world Rev 1 1 836 ...

Page 837: ...en ACMPOUT 0 VADIV VA DIVVA 1 64 15 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 0 HYST 0x0 RW Hysteresis Select When ACMPOUT 0 Select hysteresis level when comparator output is 0 The hysteresis levels can vary please see the electrical characteristics for the device for more information Value Mode Description 0 HYST0 No hyste...

Page 838: ...en ACMPOUT 1 VADIV VA DIVVA 1 64 15 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 0 HYST 0x0 RW Hysteresis Select When ACMPOUT 1 Select hysteresis level when comparator output is 1 The hysteresis levels can vary please see the electrical characteristics for the device for more information Value Mode Description 0 HYST0 No hyste...

Page 839: ... 1 0 Reset 0 Access RW Name OUTPEN Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 OUTPEN 0 RW ACMP Output Pin Enable Enable disable analog comparator output to pin Reference Manual ACMP Analog Comparator silabs com Building a more connected world Rev 1 1 839 ...

Page 840: ... location of the OUT pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 LOC7 Location 7 8 LOC8 Location 8 9 LOC9 Location 9 10 LOC10 Location 10 11 LOC11 Location 11 12 LOC12 Location 12 13 LOC13 Location 13 14 LOC14 Location 14 15 LOC15 Location 15 16 LOC16 Location 16 17 LOC17 Location 17 18 L...

Page 841: ...LOC24 Location 24 25 LOC25 Location 25 26 LOC26 Location 26 27 LOC27 Location 27 28 LOC28 Location 28 29 LOC29 Location 29 30 LOC30 Location 30 31 LOC31 Location 31 Reference Manual ACMP Analog Comparator silabs com Building a more connected world Rev 1 1 841 ...

Page 842: ...X used EXT_BASE ACMP_INPUTSEL_POS SEL_APORT1XCH0 3 APORT1Y APORT1Y used EXT_BASE ACMP_INPUTSEL_POS SEL_APORT1XCH0 4 APORT1XY APORT1X Y used EXT_BASE ACMP_INPUTSEL_POS SEL_APORT1XCH0 5 APORT2X APORT2X used EXT_BASE ACMP_INPUTSEL_POS SEL_APORT2YCH0 6 APORT2Y APORT2Y used EXT_BASE ACMP_INPUTSEL_POS SEL_APORT2YCH0 7 APORT2YX APORT2Y X used EXT_BASE ACMP_INPUTSEL_POS SEL_APORT2YCH0 8 APORT3X APORT3X us...

Page 843: ...th future devices always write bits to 0 More information in 1 2 Conven tions 0 EN 0 RW Enable External Interface Set to enable an external module like LESENSE to control the ACMP Reference Manual ACMP Analog Comparator silabs com Building a more connected world Rev 1 1 843 ...

Page 844: ...grammable sequence With the help of PRS and DMA the ADC can operate without CPU inter vention in EM2 Deep Sleep and EM3 Stop minimiz ing the number of powered up resources The ADC can further be duty cycled to reduce the energy con sumption 26 1 Introduction The ADC uses a Successive Approximation Register SAR architecture with a resolution of up to 12 bits at up to one million samples per second ...

Page 845: ... Programmable watermark DVL to generate SCAN interrupt Supports overflow and underflow interrupt generation Supports window compare function Conversion tailgating support for predictable periodic scans Programmable single channel conversion Triggered by software or PRS input Can be interleaved between two scan sequences One shot or repetitive mode Oversampling available Four deep FIFO to store con...

Page 846: ...ctional Description An overview of the ADC is shown in Figure 26 1 ADC Overview on page 846 APORT1X TEMP VSS VSS APORT2X Sequencer Control ADCn_SINGLEDATA ADCn_SCANDATA ADCn_SCANCTRLX ADCn_SINGLECTRL ADCn_SCANCTRL Prescaler ADC_CLK HFPERCLKADCn ADCn_SINGLECTRLX ADCn_STATUS ADCnCLK ADCCLKMODE Oversampling filter SINGLESAMPLE FIFO SCAN SAMPLE FIFO SCAN INPUTID ADCn_CMD ADCn_CTRL ADCn_CMPTHR ADCn_BIA...

Page 847: ...me is determined by ADC_CLK and not by adc_clk_sar ASYNCCLK is a clock source from the CMU which is considered asynchronous to HFPERCLK The CMU_ADCCTRL register can be programmed to request and use ASYNCCLK It has multiple choices for its source including AUXHFRCO HFXO and HFSRCCLK and can optionally be inverted If the chosen source for ASYNCCLK is not active at the time of request the CMU enables...

Page 848: ...modes may be set up to run only once per trigger or to automatically repeat after each operation The scan mode has priority over the single channel mode However by default if scan sequence is running a triggered single channel conversion will be interleaved between two scan samples 26 3 3 1 Single Channel Mode Single channel mode can be used to convert a single channel either once per trigger or r...

Page 849: ...as acquired 26 3 7 Input Selection explains how the input sequence is chosen When the scan sequence is triggered the ADC samples all inputs that are included in the mask ADCn_SCANMASK starting at the lowest pin number DIFF in ADCn_SCANCTRL selects whether sin gle ended or differential inputs are used The FIFO data is tagged with SCANINPUTID and can be read along with the scan data using ADCn_SCAND...

Page 850: ...g rates between about 35 and 125 ksps It may also be useful for lower sampling rates where latency is important The reference selected for scan mode is kept warm but the ADC is powered down The ADC will initiate a 1 µs warmup period before a conversion begins Because the reference is kept warm the ADC will consume a small amount of standby current when it is not converting Figure b in Figure 26 4 ...

Page 851: ...be selected from the AVDD or DVDD supply pins using the EMU_PWRCTRL_ANASW bit field 26 3 6 Input Pin Considerations For external ADC inputs routed through the APORT the maximum supported analog input voltage will be limited to the MIN VADC IOVDD where VADC is VDDX_ANA as described in 26 3 5 Power Supply Note that pins configured as ADC inputs should disable OVT by setting the corresponding GPIO_Px...

Page 852: ...fer to the APORT Client Map in the device data sheet for exact mappings Unlike APORT1 through APORT4 APORT0 is not a shared resource It consists of a 16 channel X bus and a 16 channel Y bus each with dedicated I O pin connections Note that APORT0 is not available on all device families ch0 ch2 ch4 ch6 ch24 ch26 ch28 ch30 ch1 ch3 ch5 ch7 ch25 ch27 ch29 ch31 ch0 ch2 ch4 ch6 ch24 ch26 ch28 ch30 ch1 c...

Page 853: ...signals POSSEL and NEGSEL are fully configurable However when performing conversions on internal signals NEGSEL must be set to VSS This NEGSEL reconfigurability feature in single ended mode may not be available in all devices If compatibility with devices that do not support this feature is desired NEGSEL should be set to VSS for all single channel single ended conversions Note that in both the PO...

Page 854: ... a single ended scan configuration In this example ADCn_SCANINPUTSEL has been configured to place APORT1CH16TO23 in the first third and fourth channel groups APORT4CH8TO15 has been placed in the second channel group ADCn_SCANMASK selects six of these channels for inclusion in the scan When an ADC scan is initiated with this configuration the ADC begins at SCANINPUTID0 and converts each enabled cha...

Page 855: ...UTSEL group the negative input for SCANINPUT 9 11 13 and 15 may be re mapped to any of the even numbered channels in that group SCANIN PUT 8 10 12 or 14 Figure 26 8 ADC Differential Scan Mode Re mapping Negative Input Selections on page 855 shows the effects of the ADCn_SCAN NEGSEL register on the re mappable inputs The left side of the figure shows the default channel mapping and the right side o...

Page 856: ...ed shared analog bus preventing other peripherals from using it The bus will be released only when the input select registers are changed It is possible for the ADC to passively monitor shared bus signals without controlling the switches and creating bus conflicts This can be done by setting the ADCn_APORTMASTERDIS register When ADCn_APORTMASTERDIS is used channel selection defers to the periphera...

Page 857: ...ts operation For highest accuracy when using a VBGR derived inter nal bandgap reference source GPBIASACC in ADCn_BIASPROG should be cleared to 0 HIGHACC This will allow the ADC to ena ble high accuracy mode from the bias circuitry during conversions When AVDD or an external pin reference option is used software may set GPBIASACC in ADCn_BIASPROG to 1 LOWACC to conserve energy Note that VDAC and DC...

Page 858: ...he appropriate choice where a differential reference of greater than 1 05 V is required VREFPN A differential version of VREFP with the reference source applied to the ADCn_EXTP and ADCn_EXTN pins and no at tenuation This is the appropriate choice where a differential reference of between 0 7 V and 1 05 V is required VBGRLOW An internal 0 78 V bandgap reference voltage The ADC reference voltage sh...

Page 859: ... then the chip level bias circuit will be automatically switched to high accuracy mode potentially corrupting results of the on going ADC conversion Similarly DC DC startup automatically switches the chip level bias circuit to high accuracy mode for a short time i e if DC DC startup happens when ADC is doing a conversion with GPBIASACC set to LOWACC ADC results may get corrupted DC DC startup auto...

Page 860: ...ing warmed up for performing a single conversion the scan conversion will have priority and will be done before the single conversion However a scan trigger will not interrupt in the middle of a single conversion i e if the single conversion is in the acquisition or approximation phase then the scan will have to wait for the single conversion to com plete If a scan sequence is triggered by a timer...

Page 861: ...gered The 26 3 10 1 Conversion Tailgating explains how the single channel and scan mode conversions can push each other out of phase Conversion tailgating can be chosen in repetitive mode as well in order to ensure that the scan sequence will always start immediately when triggered provided the scan REPDELAY chosen is big enough for the single conversion to finish The status flags SINGLEACT and SC...

Page 862: ... synchronous the frequency of the input sam pling FS will experience a 11 2 to 21 2 ADC_CLK cycle jitter due to synchronization requirements To precisely control the sample frequency the PRSMODE can be set to TIMED mode In this mode a long PRS pulse is expected to trigger the ADC and its negative edge directly finishes input sampling and starts the approximation phase giving precise sampling fre q...

Page 863: ... should be converted through LESENSE inside the LESENSE settings LESENSE_CHX The results of LESENSE triggered conversions are not loaded in the FIFO DATA registers but are instead available in the LESENSE register Similarly the SCAN interrupt flag is not set on completion of a LESENSE triggered conversion because that flag is set only when the data is written to the Scan FIFO When there is a LESEN...

Page 864: ... 800 1 4096 VFS 000000000001 001 0 000000000000 000 Table 26 3 ADC Differential Conversion Input Output Results Binary Hex value 2047 4096 VFS 011111111111 7FF 0 25 VFS 010000000000 400 1 4096 VFS 000000000001 001 0 000000000000 000 1 4096 VFS 111111111111 FFF 0 25 VFS 110000000000 C00 0 5 VFS 100000000000 800 26 3 10 5 Resolution The ADC performs 12 bit conversions by default However if full 12 b...

Page 865: ...ts Result Resolution bits 2x 0 13 4x 0 14 8x 0 15 16x 0 16 32x 1 16 64x 2 16 128x 3 16 256x 4 16 512x 5 16 1024x 6 16 2048x 7 16 4096x 8 16 26 3 10 7 Adjustment By default all results are right adjusted with the LSB of the result in bit position 0 zero In differential mode the signed bit is extended up to bit 31 but in single ended mode the bits above the result are read as 0 By setting ADJ in ADC...

Page 866: ...DC at production temperature ADC0CAL3_TEMPREAD1V25 is given in the Device Information DI page The production tem perature CAL_TEMP is also given in this page The temperature sensor slope V_TS_SLOPE mV degree Celsius for the sensor is found in the data sheet for the device Using the 1 25V VFS option and 12 bit resolution the temperature can be calculated according to the following formula VFS in th...

Page 867: ...h single and scan mode Gain and offset for various references and modes are calibrated during production and the calibration values for these can be found in the Device Information page During reset the gain and offset calibration registers are loaded with the production calibration values for the 1V25 reference Others can be loaded as needed or the user can perform calibration on the fly using th...

Page 868: ...GLEOF or SCANOF Underflow interrupt SINGLEUF or SCANUF triggered if DMA pops more data than present in the FIFO while the system is asleep Compare interrupt SINGLECMP or SCANCMP Over voltage interrupt VREFOV The ADC can also work with the DMA so that the system does not have to wake up to consume data This can happen if the SCAN or SINGLE interrupt is disabled and the SINGLEDMAWU or SCANDMAWU in t...

Page 869: ... system view point ASYNC mode can also help with digital noise mitigation as this clock is asynchronous not balanced with the system clock More over the user can use the invert option to invert the source of ASYNCCLK helping in noise mitigation further Whenever ADC is being used in asynchronous mode then HFPERCLK must be at least 1 5 times higher than the ADC_CLK With ASNEEDED setting for ASYNCCLK...

Page 870: ...re checking the status flags If the SINGLE ACT SCANACT status flags are high the corresponding STOP command should be issued and the user should wait until the SINGLE ACT SCANACT flags go low If the ADC was warmed up then the WARMUPMODE should be changed to NORMAL and then the user should wait on WARM SINGLEREFWARM and SCANREFWARM flags until those go low Now the ADC is idle If both LESENSE scan a...

Page 871: ...errupt Flag Register 0x03C ADCn_IFS W1 Interrupt Flag Set Register 0x040 ADCn_IFC R W1 Interrupt Flag Clear Register 0x044 ADCn_IEN RW Interrupt Enable Register 0x048 ADCn_SINGLEDATA R a Single Conversion Result Data 0x04C ADCn_SCANDATA R a Scan Conversion Result Data 0x050 ADCn_SINGLEDATAP R Single Conversion Result Data Peek Register 0x054 ADCn_SCANDATAP R Scan Sequence Result Data Peek Register...

Page 872: ...arm and keep APORT switches for single channel closed if WARMUPMODE is not NORMAL 2 KEEPPREV Keep last used reference warm and keep APORT switches for corre sponding channel closed if WARMUPMODE is not NORMAL 29 CHCONMODE 0 RW Channel Connect Selects Channel Connect Mode Value Mode Description 0 MAXSETTLE Connect APORT switches for the next input as soon as possible This optimizes settling time 1 ...

Page 873: ... or greater Value Description TIMEBASE ADC STANDBY SLOWACC mode warm up is set to 1 x TIMEBASE 1 ADC_CLK cycles and NORMAL mode warm up is set to 5 x TIMEBASE 1 ADC_CLK cycles 15 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 14 8 PRESC 0x00 RW Prescalar Setting for ADC Sample and Conversion Clock Sets the prescale factor to generat...

Page 874: ...cription 0 While in EM2 the DMA controller will not get requests about DVL reached in SCANFIFO 1 DMA is available in EM2 for processing SCANFIFO DVL request 2 SINGLEDMAWU 0 RW SINGLEFIFO DMA Wakeup Selects whether to wakeup the DMA controller when in EM2 and DVL is reached in SINGLEFIFO Value Description 0 While in EM2 the DMA controller will not get requests about Data Valid Level DVL reached in ...

Page 875: ...e devices always write bits to 0 More information in 1 2 Conven tions 3 SCANSTOP 0 W1 Scan Sequence Stop Write a 1 to stop scan sequence 2 SCANSTART 0 W1 Scan Sequence Start Write a 1 to start scan sequence 1 SINGLESTOP 0 W1 Single Channel Conversion Stop Write a 1 to stop single channel conversions 0 SINGLESTART 0 W1 Single Channel Conversion Start Write to 1 to start converting in single channel...

Page 876: ...DC is warmed up 11 10 PROGERR 0x0 R Programming Error Status Programming Error Status Mode Value Description BUSCONF x1 APORT reported a BUS Conflict NEGSELCONF 1x SINGLECTRL s NEGSEL choice is invalid with respect to POSSEL choice Occurs when two X channels or two Y channels are selected 9 SCANREFWARM 0 R Scan Reference Warmed Up Reference selected for scan mode is warmed up 8 SINGLEREFWARM 0 R S...

Page 877: ...scription 0 SINGLEACT 0 R Single Channel Conversion Active Single channel conversion is active or has pending conversions Reference Manual ADC Analog to Digital Converter silabs com Building a more connected world Rev 1 1 877 ...

Page 878: ...atibility with future devices always write bits to 0 More information in 1 2 Conven tions 27 24 AT 0x0 RW Single Channel Acquisition Time Select the acquisition time for single channel Value Mode Description 0 1CYCLE 1 conversion clock cycle acquisition time for single channel 1 2CYCLES 2 conversion clock cycles acquisition time for single channel 2 3CYCLES 3 conversion clock cycles acquisition ti...

Page 879: ...t APORT2YCH0 APORT2XCH1 65 Select APORT2XCH1 APORT2XCH31 95 Select APORT2XCH31 APORT3XCH0 96 Select APORT3XCH0 APORT3YCH1 97 Select APORT3YCH1 APORT3YCH31 127 Select APORT3YCH31 APORT4YCH0 128 Select APORT4YCH0 APORT4XCH1 129 Select APORT4XCH1 APORT4XCH31 159 Select APORT4XCH31 TESTN 245 Reserved for future expansion VSS 255 VSS 15 8 POSSEL 0xFF RW Single Channel Positive Input Selection Selects t...

Page 880: ...APORT4XCH31 AVDD 224 Select AVDD BUVDD 225 Select BUVDD DVDD 226 Select DVDD PAVDD 227 Reserved for future use DECOUPLE 228 Select DECOUPLE IOVDD 229 Select IOVDD IOVDD1 230 Select IOVDD1 Not Applicable if no IOVDD1 is available VSP 231 Reserved for future expansion OPA2 242 OPA2 output Not Applicable if no OPA is available TEMP 243 Temperature sensor DAC0OUT0 244 DAC0 output 0 Not Applicable if n...

Page 881: ...onfigure reference 4 3 RES 0x0 RW Single Channel Resolution Select Select single channel conversion resolution Value Mode Description 0 12BIT 12 bit resolution 1 8BIT 8 bit resolution 2 6BIT 6 bit resolution 3 OVS Oversampling enabled Oversampling rate is set in OVSRSEL 2 ADJ 0 RW Single Channel Result Adjustment Select single channel result adjustment Value Mode Description 0 RIGHT Results are ri...

Page 882: ...orm one conversion per trigger in single channel mode 1 ADC will repeat conversions in single channel mode continuously until SINGLESTOP is written Reference Manual ADC Analog to Digital Converter silabs com Building a more connected world Rev 1 1 882 ...

Page 883: ...6 conversion clock cycles 4 32CYCLES 32 conversion clock cycles 5 64CYCLES 64 conversion clock cycles 6 128CYCLES 128 conversion clock cycles 7 256CYCLES 256 conversion clock cycles 28 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 27 CONVSTARTDELAY EN 0 RW Enable Delaying Next Conversion Start Delay value for next conversion start ...

Page 884: ...ngle channel trigger is considered a regular asynchronous pulse that starts ADC warm up then acquisition conversion sequence The ADC_CLK controls the warmup time 1 TIMED Single channel trigger should be a pulse long enough to provide the re quired warm up time for the selected ADC warmup mode The negative edge requests sample acquisition DELAY can be used to delay the warm up request if the pulse ...

Page 885: ...aling factor is 1 3 2 0 VREFSEL 0x0 RW Single Channel Reference Selection Select reference VREF to ADC single channel mode Value Mode Description 0 VBGR Internal 0 83V Bandgap reference 1 VDDXWATT Scaled AVDD AVDD the VREF attenuation factor 2 VREFPWATT Scaled singled ended external Vref ADCn_EXTP the VREF attenua tion factor 3 VREFP Raw single ended external Vref ADCn_EXTP 4 VENTROPY Special mode...

Page 886: ...RSSEL 28 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 27 24 AT 0x0 RW Scan Acquisition Time Select the acquisition time for scan Value Mode Description 0 1CYCLE 1 conversion clock cycle acquisition time for scan 1 2CYCLES 2 conversion clock cycles acquisition time for scan 2 3CYCLES 3 conversion clock cycles acquisition time for s...

Page 887: ...4 3 RES 0x0 RW Scan Sequence Resolution Select Select scan sequence conversion resolution Value Mode Description 0 12BIT 12 bit resolution 1 8BIT 8 bit resolution 2 6BIT 6 bit resolution 3 OVS Oversampling enabled Oversampling rate is set in OVSRSEL 2 ADJ 0 RW Scan Sequence Result Adjustment Select scan sequence result adjustment Value Mode Description 0 RIGHT Results are right adjusted 1 LEFT Res...

Page 888: ... Name Reset Access Description 1 Scan conversion mode repeats continuously until SCANSTOP is writ ten Reference Manual ADC Analog to Digital Converter silabs com Building a more connected world Rev 1 1 888 ...

Page 889: ...S 16 conversion clock cycles 4 32CYCLES 32 conversion clock cycles 5 64CYCLES 64 conversion clock cycles 6 128CYCLES 128 conversion clock cycles 7 256CYCLES 256 conversion clock cycles 28 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 27 CONVSTARTDELAY EN 0 RW Enable Delaying Next Conversion Start Delay value for next conversion sta...

Page 890: ...ption 0 PULSED Scan trigger is considered a regular async pulse that starts ADC warm up then acquisition conversion sequence The ADC_CLK controls the warmup time 1 TIMED Scan trigger should be a pulse long enough to provide the required warm up time for the selected ADC warmup mode The negative edge requests sample acquisition DELAY can be used to delay the warm up request if the pulse is too long...

Page 891: ...o val ues of VREFATT the scaling factor is 1 3 2 0 VREFSEL 0x0 RW Scan Channel Reference Selection Select reference VREF to ADC scan channel mode Value Mode Description 0 VBGR Internal 0 83V Bandgap reference 1 VDDXWATT Scaled AVDD AVDD the VREF attenuation factor 2 VREFPWATT Scaled singled ended external Vref ADCn_EXTP the VREF attenua tion factor 3 VREFP Raw single ended external Vref ADCn_EXTP ...

Page 892: ...ASK is set to 0 and scan conversion is triggered ADC will do a conversion with garbage results since no inputs were enabled for conversion Mode Value Description DIFF 0 INPUT0 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx1 ADCn_INPUT0 included in mask INPUT1 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxx1x ADCn_INPUT1 included in mask INPUT2 xxxxxxxxxxxxxxxxxxxxx xxxxxxxx1xx ADCn_INPUT2 included in mask INPUT3 xxxxxxxxxxxxxx...

Page 893: ...Cn_INPUT10 Negative input ADCn_INPUT11 in cluded in mask INPUT11IN PUT11NEGSEL xxxxxxxxxxxxxxxxxxxx1 xxxxxxxxxxx Positive input ADCn_INPUT11 Negative input chosen by IN PUT11NEGSEL included in mask INPUT12INPUT13 xxxxxxxxxxxxxxxxxxx1x xxxxxxxxxxx Positive input ADCn_INPUT12 Negative input ADCn_INPUT13 in cluded in mask INPUT13IN PUT13NEGSEL xxxxxxxxxxxxxxxxxx1xx xxxxxxxxxxx Positive input ADCn_INP...

Page 894: ...ORT1CH8TO15 5 Select APORT1 s CH8 CH15 as ADCn_INPUT24 ADCn_INPUT31 APORT1CH16TO23 6 Select APORT1 s CH16 CH23 as ADCn_INPUT24 ADCn_INPUT31 APORT1CH24TO31 7 Select APORT1 s CH24 CH31 as ADCn_INPUT24 ADCn_INPUT31 APORT2CH0TO7 8 Select APORT2 s CH0 CH7 as ADCn_INPUT24 ADCn_INPUT31 APORT3CH0TO7 12 Select APORT3 s CH0 CH7 as ADCn_INPUT24 ADCn_INPUT31 APORT4CH0TO7 16 Select APORT4 s CH0 CH7 as ADCn_INP...

Page 895: ...T15 APORT1CH8TO15 5 Select APORT1 s CH8 CH15 as ADCn_INPUT8 ADCn_INPUT15 APORT1CH16TO23 6 Select APORT1 s CH16 CH23 as ADCn_INPUT8 ADCn_INPUT15 APORT1CH24TO31 7 Select APORT1 s CH24 CH31 as ADCn_INPUT8 ADCn_INPUT15 APORT2CH0TO7 8 Select APORT2 s CH0 CH7 as ADCn_INPUT8 ADCn_INPUT15 APORT3CH0TO7 12 Select APORT3 s CH0 CH7 as ADCn_INPUT8 ADCn_INPUT15 APORT4CH0TO7 16 Select APORT4 s CH0 CH7 as ADCn_IN...

Page 896: ... APORT2CH0TO7 8 Select APORT2 s CH0 CH7 as ADCn_INPUT0 ADCn_INPUT7 APORT3CH0TO7 12 Select APORT3 s CH0 CH7 as ADCn_INPUT0 ADCn_INPUT7 APORT4CH0TO7 16 Select APORT4 s CH0 CH7 as ADCn_INPUT0 ADCn_INPUT7 Reference Manual ADC Analog to Digital Converter silabs com Building a more connected world Rev 1 1 896 ...

Page 897: ...ut 2 INPUT12 Selects ADCn_INPUT12 as negative channel input 3 INPUT14 Selects ADCn_INPUT14 as negative channel input 13 12 INPUT13NEGSEL 0x3 RW Negative Input Select Register for ADCn_INPUT13 in Differential Scan Mode Selects negative channel Value Mode Description 0 INPUT8 Selects ADCn_INPUT8 as negative channel input 1 INPUT10 Selects ADCn_INPUT10 as negative channel input 2 INPUT12 Selects ADCn...

Page 898: ... INPUT4NEGSEL 0x2 RW Negative Input Select Register for ADCn_INPUT4 in Differential Scan Mode Selects negative channel Value Mode Description 0 INPUT1 Selects ADCn_INPUT1 as negative channel input 1 INPUT3 Selects ADCn_INPUT3 as negative channel input 2 INPUT5 Selects ADCn_INPUT5 as negative channel input 3 INPUT7 Selects ADCn_INPUT7 as negative channel input 3 2 INPUT2NEGSEL 0x1 RW Negative Input...

Page 899: ...3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 0x0000 Access RW RW Name ADGT ADLT Bit Name Reset Access Description 31 16 ADGT 0x0000 RW Greater Than Compare Threshold Compare threshold value for greater than comparison Must match the conversion data representation chosen 15 0 ADLT 0x0000 RW Less Than Compare Threshold Compare threshold value for less than comparison Mus...

Page 900: ...for all references other than VBGR to conserve energy 15 13 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 VFAULTCLR 0 RW Clear VREFOF Flag Use this bit to request clearing of the VREFOF flag If VREFOF irq is enabled and is triggered the user must set this bit in the ISR to clear VREFOF The user needs to reset this bit to enable ...

Page 901: ...e Sin gle ended Mode This register contains the offset calibration value used with scan conversions for differential or positive single ended mode This field is set to the production offset calibration value for the 1V25 internal reference during reset hence the reset value might differ from device to device The field is encoded as a signed 2 s complement number Higher values lead to lower ADC res...

Page 902: ...ersions for differential or positive single ended mode This field is set to the production offset calibration value for the 1V25 internal reference during reset hence the reset value might differ from device to device The field is encoded as a signed 2 s complement number Higher values lead to lower ADC results Reference Manual ADC Analog to Digital Converter silabs com Building a more connected w...

Page 903: ...Programming Error Interrupt Flag Indicates that a programming error has occurred Read the STATUS register for cause 24 VREFOV 0 R VREF Over Voltage Interrupt Flag Indicates that attenuated vref is greater than 1 3V when this bit is set The ADC stops converting and disconnects the refer ence when this happens to protect the internal low voltage circuits 23 18 Reserved To ensure compatibility with f...

Page 904: ... if there is not room in the FIFO to store a new result 7 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 SCAN 0 R Scan Conversion Complete Interrupt Flag Indicates DVL 1 number of scan channel results are available in the Scan FIFO 0 SINGLE 0 R Single Conversion Complete Interrupt Flag Indicates DVL 1 number of single channel re...

Page 905: ...ND Interrupt Flag Write 1 to set the SCANEXTPEND interrupt flag 25 PROGERR 0 W1 Set PROGERR Interrupt Flag Write 1 to set the PROGERR interrupt flag 24 VREFOV 0 W1 Set VREFOV Interrupt Flag Write 1 to set the VREFOV interrupt flag 23 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 17 SCANCMP 0 W1 Set SCANCMP Interrupt Flag Write 1...

Page 906: ...pt Flag Write 1 to set the SINGLEOF interrupt flag 7 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions Reference Manual ADC Analog to Digital Converter silabs com Building a more connected world Rev 1 1 906 ...

Page 907: ... SCANEXTPEND Interrupt Flag Write 1 to clear the SCANEXTPEND interrupt flag Reading returns the value of the IF and clears the corresponding inter rupt flags This feature must be enabled globally in MSC 25 PROGERR 0 R W1 Clear PROGERR Interrupt Flag Write 1 to clear the PROGERR interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enab...

Page 908: ...y in MSC 9 SCANOF 0 R W1 Clear SCANOF Interrupt Flag Write 1 to clear the SCANOF interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 8 SINGLEOF 0 R W1 Clear SINGLEOF Interrupt Flag Write 1 to clear the SINGLEOF interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This...

Page 909: ...NEXTPEND 0 RW SCANEXTPEND Interrupt Enable Enable disable the SCANEXTPEND interrupt 25 PROGERR 0 RW PROGERR Interrupt Enable Enable disable the PROGERR interrupt 24 VREFOV 0 RW VREFOV Interrupt Enable Enable disable the VREFOV interrupt 23 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 17 SCANCMP 0 RW SCANCMP Interrupt Enable Ena...

Page 910: ...000000 Access R Name DATA Bit Name Reset Access Description 31 0 DATA 0x00000000 R Single Conversion Result Data This register holds the results from the last single channel mode conversion Reading this field pops one entry from the SINGLE FIFO 26 5 19 ADCn_SCANDATA Scan Conversion Result Data Actionable Reads Offset Bit Position 0x04C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11...

Page 911: ...ding this field will not pop an entry from the SINGLE FIFO 26 5 21 ADCn_SCANDATAP Scan Sequence Result Data Peek Register Offset Bit Position 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name DATAP Bit Name Reset Access Description 31 0 DATAP 0x00000000 R Scan Conversion Result Data Peek The register holds the results from th...

Page 912: ...entry from the SCAN FIFO 26 5 23 ADCn_SCANDATAXP Scan Sequence Result Data Data Source Peek Register Offset Bit Position 0x06C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x0000 Access R R Name SCANINPUTIDPEEK DATAP Bit Name Reset Access Description 31 21 Reserved To ensure compatibility with future devices always write bits to 0 More informatio...

Page 913: ... from the APORT 6 APORT3XREQ 0 R 1 If the Bus Connected to APORT3X is Requested Reports if the bus connected to APORT3X is being requested from the APORT 5 APORT2YREQ 0 R 1 If the Bus Connected to APORT2Y is Requested Reports if the bus connected to APORT2Y is being requested from the APORT 4 APORT2XREQ 0 R 1 If the Bus Connected to APORT2X is Requested Reports if the bus connected to APORT2X is b...

Page 914: ... also being requested by another peripheral 6 APORT3XCONFLICT 0 R 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral Reports if the bus connected to APORT3X is is also being requested by another peripheral 5 APORT2YCONFLICT 0 R 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral Reports if the bus connected to APORT2Y is is also being requested by another...

Page 915: ...with future devices always write bits to 0 More information in 1 2 Conven tions 2 0 SINGLEDC 0x0 R Single Data Count Number of unread data available in Single FIFO 26 5 27 ADCn_SCANFIFOCOUNT Scan FIFO Count Register Offset Bit Position 0x088 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 Access R Name SCANDC Bit Name Reset Access Description 31 3 Re...

Page 916: ...le FIFO Content Write a 1 to clear Single FIFO content 26 5 29 ADCn_SCANFIFOCLEAR Scan FIFO Clear Register Offset Bit Position 0x090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access W1 Name SCANFIFOCLEAR Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conve...

Page 917: ...cription 0 APORT mastering enabled 1 APORT mastering disabled 8 APORT4XMASTER DIS 0 RW APORT4X Master Disable Determines if the ADC will request this APORT bus if selected by POSSEL or NEGSEL or SCANINPUTSEL When 1 ADC only passively monitors the APORT bus and the selection of the channel for the selected bus is ignored The channel selection is done by the device that masters the APORT bus This bi...

Page 918: ...C only passively monitors the APORT bus and the selection of the channel for the selected bus is ignored The channel selection is done by the device that masters the APORT bus This bit allows multiple APORT connected devices to monitor the same APORT bus simultaneously Value Description 0 APORT mastering enabled 1 APORT mastering disabled 3 APORT1YMASTER DIS 0 RW APORT1Y Master Disable Determines ...

Page 919: ...nabled 1 APORT mastering disabled 1 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions Reference Manual ADC Analog to Digital Converter silabs com Building a more connected world Rev 1 1 919 ...

Page 920: ...to EM3 27 1 Introduction The current digital to analog converter IDAC can source or sink a configurable constant current from APORT and or main pad OUT PAD The current is configurable with several ranges of various step sizes 27 2 Features Can source and sink current Programmable constant output current Selectable current range between 0 05 µA and 64 µA Each range is linearly programmable in 32 st...

Page 921: ...ected by configuring the RANGESEL bitfield in IDAC_CURRPROG The current output in each range is linearly programmable in 32 steps and is controlled by the STEPSEL bitfield in IDAC_CURRPROG These current rang es and their step sizes are shown in Table 27 1 Range Selection on page 921 Table 27 1 Range Selection Range Select Range Value µA Step Size nA Step Counts 0 0 05 1 6 50 32 1 1 6 4 7 100 32 2 ...

Page 922: ...put Transition If the internal output of the IDAC differs from the voltage at the output pin enabling the output can cause an unwanted transition To minimize this transition it is possible to charge or discharge the internal output node before enabling the output to the pin Setting MIN OUTTRANS in IDAC_CTRL when the IDAC is sourcing current connects the internal node to GND Alternatively setting M...

Page 923: ...dule can be used by configuring for example a CC channel to compare match with a configurable level I T OFF ON T PRS input Figure 27 2 IDAC Charge Injection Example 27 4 Register Map The offset register address is relative to the registers base address Offset Name Type Description 0x000 IDAC_CTRL RW Control Register 0x004 IDAC_CURPROG RW Current Programming Register 0x00C IDAC_DUTYCONFIG RW Duty C...

Page 924: ...iption 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRSCH10 PRS Channel 10 selected 11 PRSCH11 PRS Channel 11 selected 19 ...

Page 925: ... determination is expected to be from another peripheral and the IDAC only passively looks at the bus When 1 the selection of channel for a selected bus is ignored the bus is not and will be whatever selection the external device mas tering the bus has configured for the APORT bus Value Description 0 Bus mastering enabled 1 Bus mastering disabled 13 EM2DELAY 0 RW EM2 Delay Delays EM2 entry until t...

Page 926: ...une the Current to Given Accuracy In production test the middle step 16 of each range is calibrated and can be read from the Device Information DI page 15 13 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 8 STEPSEL 0x00 RW Current Step Size Select Select the step within each range The size of each step depends on the RANGESEL set...

Page 927: ...on in 1 2 Conven tions 27 5 4 IDAC_STATUS Status Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name APORTCONFLICT Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 APORTCONFLICT 0 R APORT Conflict Output ...

Page 928: ...evices always write bits to 0 More information in 1 2 Conven tions 27 5 6 IDAC_IFS Interrupt Flag Set Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access W1 Name APORTCONFLICT Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 C...

Page 929: ...SC 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 27 5 8 IDAC_IEN Interrupt Enable Register Offset Bit Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access RW Name APORTCONFLICT Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices...

Page 930: ...IDAC_APORTCONFLICT APORT Request Status Register Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access R R Name APORT1YCONFLICT APORT1XCONFLICT Bit Name Reset Access Description 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 APORT1YCONFLICT 0 R 1 If th...

Page 931: ...pes Once the data is collected the programmable state machine LESENSE decoder is capable of process ing sensor data without CPU intervention A large re sult buffer allows the chip to remain in EM2 for long periods of time while autonomously collecting data 28 1 Introduction LESENSE is a low energy sensor interface utilizing on chip peripherals to perform measurement of a configurable set of sensor...

Page 932: ...the data collected by the sequencer To autonomously analyze sensor results the LESENSE decoder provides the ability to define a finite state machine with up to 32 states as well as define programmable actions upon state transitions This allows the decoder to implement a wide range of decod ing schemes such as quadrature decoding A RAM block is used for storage of configuration and measurement resu...

Page 933: ...vides an easy way to implement hysteresis on channel events as threshold values can be changed depending on the sensor status Setting SCANCONF to DECDEF will make the state of the decoder define which scan configuration to be used If the decoder state is at index 16 or higher channel x will use CHX 8_CONF otherwise it will use CHX_CONF Similarly channels 8 through 15 will use CHX_CONF when the dec...

Page 934: ...8 2 Scan Frequency on page 934 If SCANMODE is set to ONE SHOT a single scan will be made when START in CMD is set To start a new scan on a PRS event set SCANMODE to PRS and configure PRS channel in PRSSEL The PRS start signal needs to be active for at least one LFACLKLESENSE cycle to make sure LE SENSE is able to register it Fscan LFACLKLESENSE 1 PCTOP 2PCPRESC Figure 28 2 Scan Frequency It is pos...

Page 935: ...elays enables LESENSE to easily define exact time windows for sensor measurements A start delay can be inserted before sensor measurement begin by configuring STARTDLY in TIMCTRL This delay can be used to ensure that the VDAC conversion is done and voltages have stabilized before the sensor measurement begins The AUXHFRCO startup can be delayed until the system enters the excite phase by configuri...

Page 936: ...te phase Idle phase SAMPLEDLY Measure phase START AUXHFRCO INIT STARTDLY MEASUREDLY EXTIME Figure 28 5 Timing Diagram LFACLK Based Timing Reference Manual LESENSE Low Energy Sensor Interface silabs com Building a more connected world Rev 1 1 936 ...

Page 937: ...r on the alternative excite pin associated with the given channel By default the alternative excite pins are map ped to the LES_ALTEX pins but they can also be mapped to LESENSE CHX 8 mod 16 Mapping of the alternative excite pins is config ured in ALTEXMAP in the CTRL register Table 28 2 LESENSE Excitation Pin Mapping on page 937 summarizes the mapping of exci tation pins for different configurati...

Page 938: ...able for a given pin is set in ROUTEPEN 28 3 5 Sensor Sampling During the measurement phase LESENSE can sample data from sensors using either ADC0 or an ACMP This is configured in CHx_INTERACT_SAMPLE If the ACMP is used LESENSE can evaluate the ACMP output at a single point in time CHx_INTER ACT_SAMPLE ACMP or count pulses on the ACMP output CHx_INTERACT_SAMPLE ACMPCOUNT for a programmable peri od...

Page 939: ...ESENSE is running i e the RUNNING bit in LESENSE_STATUS is high ACMP sample LESENSE counter ACMP COUNTER ADC ADCDIFF CHx_EVAL_SCANRESINV COMPTHRES COMPTHRES GE LESS CHx_EVAL_COMP CHx_INTERACT_SAMPLE NONE LEVEL POSEDGE NEGEDGE CHx_INTERACT_SETIF 0 Set interrupt flag SCANRES x SENSORSTATE THRES SLIDINGWIN CHx_EVAL_MODE STEPDET ADC data COUNTER ADC ADCDIFF CHx_INTERACT_SAMPLE Window state STEP_UP STE...

Page 940: ...e 28 8 Sliding Window on page 940 shows how the sliding window evaluation mode can be used to implement a system with two self calibrating thresholds SCANRES Sensor data Figure 28 8 Sliding Window 28 3 6 3 Step Detection Step detection is used to detect steps in the sensor data compared to sensor data from the previous measurement The size of the step is configured in EVALCTRL_WINSIZE In this mode...

Page 941: ...on LESENSE can generate a pulse on one or more of the decoder PRS channels Which PRS channel to generate a pulse on is configured in the PRSACT bit field If PRSCNT in DECCTRL is set count signals will be generated on decoder PRS chan nels 0 and 1 according to the PRSACT configuration In this mode channel 0 will pulse each time a count event occurs while channel 1 indicates the count direction 1 be...

Page 942: ... MASKAi 1 Y N SENSORSTATE MASKBi 1 COMPBi 1 MASKBi 1 Y N SENSORSTATE changed ERRCHK 1 Y N CHAINi 1 1 Y N Figure 28 11 Decoder State Transition Evaluation The DECODER has a PRS output named DECCMP This output can be used to indicate which state or subset of states the decoder is currently in This PRS output is enabled by setting DECCMPEN in PRSCTRL and configured through DECCMPMASK and DECCMPV AL i...

Page 943: ...Figure 28 13 Decoder Hysteresis on page 943 illustrates how the hysteresis triggers upon state transitions State 0 State 1 1 B transition no hysteresis State 2 2 A transition hysteresis State 3 5 A transition no hysteresis 3 B transition hysteresis 4 A transition hysteresis A transition Transition defined in TCONFA B transition Transition defined in TCONFB Figure 28 13 Decoder Hysteresis When HYST...

Page 944: ... overflows During a scan the state of each sensor is stored in SCANRES If a sensor triggers a 1 is stored in SCANRES else a 0 is stored in SCANRES Whether or not a sensor is said to be triggered depends of the configuration for the given channel See 28 3 6 Sensor Evaluation for details If STRSAMPLE in CHx_EVAL is set the sensor data for each channel will be stored in the LESENSE result buf fer If ...

Page 945: ...MODE bit fields in PERCTRL LESENSE will take control of the positive input mux and the voltage dividers DIVVA DIVVB for ACMP0 and ACMP1 The remaining configuration of the analog comparators is done in the ACMP register interface If ACMPxMODE in PERCTRL is set to MUX LESENSE will take control of the positive input mux of the ACMP through the external override interface described in the ACMP chapter...

Page 946: ...buffer DMAWU in CTRL configures at which buffer level LESENSE should wake up the DMA when in EM2 Note The DMA controller should always fetch data from the BUFDATA register 28 3 14 PRS Output LESENSE is an asynchronous PRS producer and has twenty PRS outputs The decoder has four outputs and in addition all bits in the SCANRES register are available as PRS outputs For further information on the deco...

Page 947: ...sor as active if the frequency on a channel drops below the threshold i e the button is pressed c Set SAMPLEDLY to an appropriate value each sensor will be measured for SAMPLEDLY FLFACLK_LESENSE seconds MEAS UREDLY should be set to 0 5 Set CTRTHRESHOLD to an appropriate value An interrupt will be issued if the counter value for a sensor is below this threshold after the measurement phase 6 Enable ...

Page 948: ...LC Sensor Oscillations on page 948 illustrates how the output pulses from the ACMP correspond to damping of the oscillations The results from sensor evaluation can automatically be fed into the decoder in order to keep track of rotations 0 05 0 45 0 95 1 45 1 95 2 45 2 95 0 10 20 30 40 50 60 70 80 90 100 LC sensor ACMP output ACMP threshold 0 05 0 45 0 95 1 45 1 95 2 45 2 95 0 10 20 30 40 50 60 70...

Page 949: ...pin high d Set SAMPLE to ACMPCOUNT and COMP to LESS Status of each sensor is evaluated based on the number of pulses gener ated by the ACMP If they are less than the threshold value the sensor is said to be active e Set SAMPLEDLY to an appropriate value each sensor will be measured for SAMPLEDLY FLFACLK_LESENSE seconds 8 Set CTRTHRESHOLD to an appropriate value If the sensor is active the counter ...

Page 950: ...e sensors to be evaluated by the decoder b Configure the remaining bit fields in STx_TCONFA and STx_TCONFB as described in Table 28 3 LESENSE Decoder Configu ration for FSM Example 1 on page 950 4 To initialize the decoder run one scan and read the present sensor status from SENSORSTATE Then write the index of this state to DECSTATE 5 Write to START in CMD to start scanning of sensors and decoding...

Page 951: ...this state to DECSTATE 3 Write to START in CMD to start scanning of sensors and decoding Table 28 4 LESENSE Decoder Configuration for FSM Example 2 Register NEXTSTATE COMP MASK CHAIN ST0_TCONFA 8 0b1000 0b0111 1 ST0_TCONFB 2 0b0001 0b1000 ST1_TCONFA 6 0b0010 0b1000 0 ST1_TCONFB 6 0b0010 0b1000 ST2_TCONFA 8 0b1000 0b0111 1 ST2_TCONFB 4 0b0011 0b1000 ST3_TCONFA 0 0b0000 0b1000 0 ST3_TCONFB 0 0b0000 ...

Page 952: ...SE_IDLECONF RW GPIO Idle Phase Configuration 0x044 LESENSE_ALTEXCONF RW Alternative Excite Pin Configuration 0x050 LESENSE_IF R Interrupt Flag Register 0x054 LESENSE_IFS W1 Interrupt Flag Set Register 0x058 LESENSE_IFC R W1 Interrupt Flag Clear Register 0x05C LESENSE_IEN RW Interrupt Enable Register 0x060 LESENSE_SYNCBUSY R Synchronization Busy Register 0x064 LESENSE_ROUTEPEN RW I O Routing Regist...

Page 953: ...Hx_INTERACT RW Scan Configuration LESENSE_CHx_EVAL RWH Scan Configuration 0x330 LESENSE_CH15_TIMING RW Scan Configuration 0x334 LESENSE_CH15_INTERACT RW Scan Configuration 0x338 LESENSE_CH15_EVAL RWH Scan Configuration Reference Manual LESENSE Low Energy Sensor Interface silabs com Building a more connected world Rev 1 1 953 ...

Page 954: ... in debug mode 21 20 DMAWU 0x0 RW DMA Wake up From EM2 Set buffer threshold for waking up the DMA controller when the system is in EM2 Value Mode Description 0 DISABLE No DMA wake up from EM2 1 BUFDATAV DMA wake up from EM2 when data is valid in the result buffer 2 BUFLEVEL DMA wake up from EM2 when the result buffer is full half full depend ing on BUFIDL configuration 19 BUFIDL 0 RW Result Buffer...

Page 955: ...bits control which CHx_CONF registers to be used Value Mode Description 0 DIRMAP The channel configuration register registers used are directly mapped to the channel number 1 INVMAP The channel configuration register registers used are CHX 8_CONF for channels 0 7 and CHX 8_CONF for channels 8 15 2 TOGGLE The channel configuration register registers used toggles between CHX_CONF and CHX 8_CONF when...

Page 956: ...d as input 1 0 SCANMODE 0x0 RW Configure Scan Mode These bits control how the scan frequency is decided Value Mode Description 0 PERIODIC A new scan is started each time the period counter overflows 1 ONESHOT A single scan is performed when START in CMD is set 2 PRS Pulse on PRS channel Reference Manual LESENSE Low Energy Sensor Interface silabs com Building a more connected world Rev 1 1 956 ...

Page 957: ... bits to 0 More information in 1 2 Conven tions 23 22 STARTDLY 0x0 RW Start Delay Configuration Delay sensor interaction STARTDELAY LFACLKLESENSE cycles for each channel 21 20 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 19 12 PCTOP 0x00 RW Period Counter Top Value These bits contain the top value for the period counter 11 Reserve...

Page 958: ...KLESENSE 8 4 DIV16 Low frequency timer is clocked with LFACLKLESENSE 16 5 DIV32 Low frequency timer is clocked with LFACLKLESENSE 32 6 DIV64 Low frequency timer is clocked with LFACLKLESENSE 64 7 DIV128 Low frequency timer is clocked with LFACLKLESENSE 128 3 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 0 AUXPRESC 0x0 RW Presca...

Page 959: ...wn when LESENSE is idle 1 KEEPACMPWARM The analog comparators are kept powered up when LESENSE is idle 2 KEEPDACWARM The VDAC is kept powered up when LESENSE is idle 3 KEEPACMPDACWARM The analog comparators and VDAC are kept powered up when LE SENSE is idle 27 ACMP1HYSTEN 0 RW ACMP1 Hysteresis Enable Set to control ACMP1_HYSTERESIS0_DIVVX and ACMP1_HYSTERESIS1_DIVVX separately 26 ACMP0HYSTEN 0 RW ...

Page 960: ...to configure the duration between the VDAC conversion trigger and the sensor interaction Value Mode Description 0 FULLCYCLE VDAC is started a full LFACLKLESENSE cycle before sensor interaction starts 1 HALFCYCLE VDAC is started half a LFACLKLESENSE cycle before sensor interaction starts 5 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven t...

Page 961: ...CCH1EN 0 RW VDAC CH1 Enable Enable LESENSE control of VDAC0 CH1 0 DACCH0EN 0 RW VDAC CH0 Enable Enable LESENSE control of VDAC0 CH0 Reference Manual LESENSE Low Energy Sensor Interface silabs com Building a more connected world Rev 1 1 961 ...

Page 962: ...H1 PRS Channel 1 selected as input 2 PRSCH2 PRS Channel 2 selected as input 3 PRSCH3 PRS Channel 3 selected as input 4 PRSCH4 PRS Channel 4 selected as input 5 PRSCH5 PRS Channel 5 selected as input 6 PRSCH6 PRS Channel 6 selected as input 7 PRSCH7 PRS Channel 7 selected as input 8 PRSCH8 PRS Channel 8 selected as input 9 PRSCH9 PRS Channel 9 selected as input 10 PRSCH10 PRS Channel 10 selected as...

Page 963: ...ut 5 PRSCH5 PRS Channel 5 selected as input 6 PRSCH6 PRS Channel 6 selected as input 7 PRSCH7 PRS Channel 7 selected as input 8 PRSCH8 PRS Channel 8 selected as input 9 PRSCH9 PRS Channel 9 selected as input 10 PRSCH10 PRS Channel 10 selected as input 11 PRSCH11 PRS Channel 11 selected as input 14 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 C...

Page 964: ...t hysteresis is enabled in the decoder suppressing interrupt requests 5 HYSTPRS2 0 RW Enable Decoder Hysteresis on PRS2 Output When set hysteresis is enabled in the decoder suppressing changes on PRS channel 2 4 HYSTPRS1 0 RW Enable Decoder Hysteresis on PRS1 Output When set hysteresis is enabled in the decoder suppressing changes on PRS channel 1 3 HYSTPRS0 0 RW Enable Decoder Hysteresis on PRS0 ...

Page 965: ...ule duty cycled between low power and high accuracy mode 2 HIGHACC Bias module always in high accuracy mode 28 5 6 LESENSE_EVALCTRL LESENSE Evaluation Control Async Reg For more information about asynchronous registers see 4 3 Access to Low Energy Peripherals Asynchronous Registers Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset...

Page 966: ...0 More information in 1 2 Conven tions 16 DECCMPEN 0 RW Enable PRS Output DECCMP Enables decoder state compare match PRS output 15 13 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 12 8 DECCMPMASK 0x00 RW Decoder State Compare Value Mask Masks DECCMPVAL and DECSTATE for comparison 7 5 Reserved To ensure compatibility with future dev...

Page 967: ...op LESENSE If issued during a scan the command will take effect after scan completion 0 START 0 W1 Start Scanning of Sensors Set this bit to start LESENSE 28 5 9 LESENSE_CHEN Channel Enable Register Async Reg For more information about asynchronous registers see 4 3 Access to Low Energy Peripherals Asynchronous Registers Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ...

Page 968: ... 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 0x0000 Access RWH RWH Name STEPDIR SCANRES Bit Name Reset Access Description 31 16 STEPDIR 0x0000 RWH Direction of Previous Step Detection In step detection mode bit X will be set if a step up was detected on channel X 15 0 SCANRES 0x0000 RWH Scan Results Bit X will be set depending on channel X evaluation Reference Manual LESENSE Low Energy Sensor Interface...

Page 969: ... write bits to 0 More information in 1 2 Conven tions 5 DACACTIVE 0 R LESENSE VDAC Interface is Active LESENSE is currently using the VDAC 4 SCANACTIVE 0 R LESENSE Scan Active LESENSE is currently interfacing to sensors 3 RUNNING 0 R LESENSE Periodic Counter Running LESENSE is running in periodic mode 2 BUFFULL 0 R Result Buffer Full Set when the result buffer is full 1 BUFHALFFULL 0 R Result Buff...

Page 970: ...ead data in the result buffer Incremented on read from BUFDATA 28 5 13 LESENSE_BUFDATA Result Buffer Data Register Async Reg Actionable Reads For more information about asynchronous registers see 4 3 Access to Low Energy Peripherals Asynchronous Registers Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xX 0xXXXX Access R R Name...

Page 971: ...dex Shows the index of the current channel 28 5 15 LESENSE_DECSTATE Current Decoder State Async Reg For more information about asynchronous registers see 4 3 Access to Low Energy Peripherals Asynchronous Registers Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RWH Name DECSTATE Bit Name Reset Access Description 31 5...

Page 972: ...7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 Access RWH Name SENSORSTATE Bit Name Reset Access Description 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 3 0 SENSORSTATE 0x0 RWH Decoder Input Register Shows the status of sensors chosen as input to the decoder Reference Manual LESENSE Low Energy Sensor Interface silabs c...

Page 973: ...e on channels 4 5 7 10 12 13 29 28 CH14 0x0 RW Channel 14 Idle Phase Configuration This bitfield determines how the channel is configured during the idle phase Value Mode Description 0 DISABLE CH14 output is disabled in idle phase 1 HIGH CH14 output is high in idle phase 2 LOW CH14 output is low in idle phase 3 DAC CH14 output is connected to VDAC output in idle phase Note that this mode is only a...

Page 974: ...H10 output is high in idle phase 2 LOW CH10 output is low in idle phase 3 DAC CH10 output is connected to VDAC output in idle phase Note that this mode is only available on channels 4 5 7 10 12 13 19 18 CH9 0x0 RW Channel 9 Idle Phase Configuration This bitfield determines how the channel is configured during the idle phase Value Mode Description 0 DISABLE CH9 output is disabled in idle phase 1 HI...

Page 975: ...hase Configuration This bitfield determines how the channel is configured during the idle phase Value Mode Description 0 DISABLE CH5 output is disabled in idle phase 1 HIGH CH5 output is high in idle phase 2 LOW CH5 output is low in idle phase 3 DAC CH5 output is connected to VDAC output in idle phase Note that this mode is only available on channels 4 5 7 10 12 13 9 8 CH4 0x0 RW Channel 4 Idle Ph...

Page 976: ...e Configuration This bitfield determines how the channel is configured during the idle phase Value Mode Description 0 DISABLE CH1 output is disabled in idle phase 1 HIGH CH1 output is high in idle phase 2 LOW CH1 output is low in idle phase 3 DAC CH1 output is connected to VDAC output in idle phase Note that this mode is only available on channels 4 5 7 10 12 13 1 0 CH0 0x0 RW Channel 0 Idle Phase...

Page 977: ... bit to excite ALTEX5 regardless of what channel is active 20 AEX4 0 RW ALTEX4 Always Excite Enable Set this bit to excite ALTEX4 regardless of what channel is active 19 AEX3 0 RW ALTEX3 Always Excite Enable Set this bit to excite ALTEX3 regardless of what channel is active 18 AEX2 0 RW ALTEX2 Always Excite Enable Set this bit to excite ALTEX2 regardless of what channel is active 17 AEX1 0 RW ALTE...

Page 978: ...LECONF3 0x0 RW ALTEX3 Idle Phase Configuration This bitfield determines how the alternate excite pin is configured during the idle phase Value Mode Description 0 DISABLE ALTEX3 output is disabled in idle phase 1 HIGH ALTEX3 output is high in idle phase 2 LOW ALTEX3 output is low in idle phase 5 4 IDLECONF2 0x0 RW ALTEX2 Idle Phase Configuration This bitfield determines how the alternate excite pin...

Page 979: ...alternate excite pin is configured during the idle phase Value Mode Description 0 DISABLE ALTEX0 output is disabled in idle phase 1 HIGH ALTEX0 output is high in idle phase 2 LOW ALTEX0 output is low in idle phase Reference Manual LESENSE Low Energy Sensor Interface silabs com Building a more connected world Rev 1 1 979 ...

Page 980: ...lows 20 BUFLEVEL 0 R BUFLEVEL Interrupt Flag Set when the data buffer is full 19 BUFDATAV 0 R BUFDATAV Interrupt Flag Set when data is available in the result buffer 18 DECERR 0 R DECERR Interrupt Flag Set when the decoder detects an error 17 DEC 0 R DEC Interrupt Flag Set when the decoder has issued an interrupt request 16 SCANCOMPLETE 0 R SCANCOMPLETE Interrupt Flag Set when a scan sequence is c...

Page 981: ...iggers 5 CH5 0 R CH5 Interrupt Flag Set when channel 5 triggers 4 CH4 0 R CH4 Interrupt Flag Set when channel 4 triggers 3 CH3 0 R CH3 Interrupt Flag Set when channel 3 triggers 2 CH2 0 R CH2 Interrupt Flag Set when channel 2 triggers 1 CH1 0 R CH1 Interrupt Flag Set when channel 1 triggers 0 CH0 0 R CH0 Interrupt Flag Set when channel 0 triggers Reference Manual LESENSE Low Energy Sensor Interfac...

Page 982: ... flag 20 BUFLEVEL 0 W1 Set BUFLEVEL Interrupt Flag Write 1 to set the BUFLEVEL interrupt flag 19 BUFDATAV 0 W1 Set BUFDATAV Interrupt Flag Write 1 to set the BUFDATAV interrupt flag 18 DECERR 0 W1 Set DECERR Interrupt Flag Write 1 to set the DECERR interrupt flag 17 DEC 0 W1 Set DEC Interrupt Flag Write 1 to set the DEC interrupt flag 16 SCANCOMPLETE 0 W1 Set SCANCOMPLETE Interrupt Flag Write 1 to...

Page 983: ...to set the CH6 interrupt flag 5 CH5 0 W1 Set CH5 Interrupt Flag Write 1 to set the CH5 interrupt flag 4 CH4 0 W1 Set CH4 Interrupt Flag Write 1 to set the CH4 interrupt flag 3 CH3 0 W1 Set CH3 Interrupt Flag Write 1 to set the CH3 interrupt flag 2 CH2 0 W1 Set CH2 Interrupt Flag Write 1 to set the CH2 interrupt flag 1 CH1 0 W1 Set CH1 Interrupt Flag Write 1 to set the CH1 interrupt flag 0 CH0 0 W1...

Page 984: ... must be enabled globally in MSC 19 BUFDATAV 0 R W1 Clear BUFDATAV Interrupt Flag Write 1 to clear the BUFDATAV interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 18 DECERR 0 R W1 Clear DECERR Interrupt Flag Write 1 to clear the DECERR interrupt flag Reading returns the value of the IF and clears the correspo...

Page 985: ...responding interrupt flags This feature must be enabled globally in MSC 6 CH6 0 R W1 Clear CH6 Interrupt Flag Write 1 to clear the CH6 interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 5 CH5 0 R W1 Clear CH5 Interrupt Flag Write 1 to clear the CH5 interrupt flag Reading returns the value of the IF and clears...

Page 986: ...able disable the BUFOF interrupt 20 BUFLEVEL 0 RW BUFLEVEL Interrupt Enable Enable disable the BUFLEVEL interrupt 19 BUFDATAV 0 RW BUFDATAV Interrupt Enable Enable disable the BUFDATAV interrupt 18 DECERR 0 RW DECERR Interrupt Enable Enable disable the DECERR interrupt 17 DEC 0 RW DEC Interrupt Enable Enable disable the DEC interrupt 16 SCANCOMPLETE 0 RW SCANCOMPLETE Interrupt Enable Enable disabl...

Page 987: ...le the CH2 interrupt 1 CH1 0 RW CH1 Interrupt Enable Enable disable the CH1 interrupt 0 CH0 0 RW CH0 Interrupt Enable Enable disable the CH0 interrupt 28 5 23 LESENSE_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x060 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name CMD Bit Name Reset Access Description 31 8 Reserved To ensur...

Page 988: ...LESENSE ALTEX7 pin 22 ALTEX6PEN 0 RW ALTEX6 Pin Enable Set this bit to enable LESENSE ALTEX6 pin 21 ALTEX5PEN 0 RW ALTEX5 Pin Enable Set this bit to enable LESENSE ALTEX5 pin 20 ALTEX4PEN 0 RW ALTEX4 Pin Enable Set this bit to enable LESENSE ALTEX4 pin 19 ALTEX3PEN 0 RW ALTEX3 Pin Enable Set this bit to enable LESENSE ALTEX3 pin 18 ALTEX2PEN 0 RW ALTEX2 Pin Enable Set this bit to enable LESENSE AL...

Page 989: ...s bit to enable LESENSE CH6 pin 5 CH5PEN 0 RW CH5 Pin Enable Set this bit to enable LESENSE CH5 pin 4 CH4PEN 0 RW CH4 Pin Enable Set this bit to enable LESENSE CH4 pin 3 CH3PEN 0 RW CH3 Pin Enable Set this bit to enable LESENSE CH3 pin 2 CH2PEN 0 RW CH2 Pin Enable Set this bit to enable LESENSE CH2 pin 1 CH1PEN 0 RW CH1 Pin Enable Set this bit to enable LESENSE CH1 pin 0 CH0PEN 0 RW CH0 Pin Enable...

Page 990: ...SCNT 0 Mode Value Description NONE 0 No PRS pulses generated PRS0 1 Generate pulse on LESPRS0 PRS1 2 Generate pulse on LESPRS1 PRS01 3 Generate pulse on LESPRS0 and LESPRS1 PRS2 4 Generate pulse on LESPRS2 PRS02 5 Generate pulse on LESPRS0 and LESPRS2 PRS12 6 Generate pulse on LESPRS1 and LESPRS2 PRS012 7 Generate pulse on LESPRS0 LESPRS1 and LESPRS2 DECCTRL_PRSCNT 1 NONE 0 Do not count UP 1 Count...

Page 991: ...xXX RW Next State Index Index of next state to be entered if the sensor state equals COMP 7 4 MASK 0xX RW Sensor Mask Set bit X to exclude sensor X from evaluation 3 0 COMP 0xX RW Sensor Compare Value State transition is triggered when sensor state equals COMP Reference Manual LESENSE Low Energy Sensor Interface silabs com Building a more connected world Rev 1 1 991 ...

Page 992: ...s COMP DECCTRL_PRSCNT 0 Mode Value Description NONE 0 No PRS pulses generated PRS0 1 Generate pulse on PRS0 PRS1 2 Generate pulse on PRS1 PRS01 3 Generate pulse on PRS0 and PRS1 PRS2 4 Generate pulse on PRS2 PRS02 5 Generate pulse on PRS0 and PRS2 PRS12 6 Generate pulse on PRS1 and PRS2 PRS012 7 Generate pulse on PRS0 PRS1 and PRS2 DECCTRL_PRSCNT 1 NONE 0 Do not count UP 1 Count up DOWN 2 Count do...

Page 993: ...ipherals Asynchronous Registers Offset Bit Position 0x200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xX 0xXXXX Access R RWH Name DATASRC DATA Bit Name Reset Access Description 31 20 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 19 16 DATASRC 0xX R Result Data Source This bitfield co...

Page 994: ...ription 31 24 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 23 14 MEASUREDLY 0xXXX RW Set Measure Delay Configure measure delay Sensor measuring is delayed for MEASUREDLY EXCLK cycles 13 6 SAMPLEDLY 0xXX RW Set Sample Delay Configure sample delay Sampling will occur after SAMPLEDLY SAMPLECLK cycles 5 0 EXTIME 0xXX RW Set Excitation...

Page 995: ...o configure which clock is used for timing of SAMPLEDLY Value Mode Description 0 LFACLK LFACLK will be used for timing 1 AUXHFRCO AUXHFRCO will be used for timing 19 EXCLK X RW Select Clock Used for Excitation Timing This bit is used to configure which clock is used for timing of EXTIME and MEASUREDLY Value Mode Description 0 LFACLK LFACLK will be used for timing 1 AUXHFRCO AUXHFRCO will be used f...

Page 996: ...SAMPLE 0xX RW Select Sample Mode Select measurement to be used for evaluation Value Mode Description 0 ACMPCOUNT Counter output will be used in evaluation 1 ACMP ACMP output will be used in evaluation 2 ADC ADC output will be used in evaluation 3 ADCDIFF Differential ADC output will be used in evaluation 11 0 THRES 0xXXX RW ACMP Threshold or VDAC Data Set threshold used for ACMP or data used in VD...

Page 997: ...e sensor result 20 SCANRESINV X RW Enable Inversion of Result If set the bit stored in SCANRES will be inverted 19 18 STRSAMPLE 0xX RW Enable Storing of Sensor Sample in Result Buffer If set the sensor sample value will be stored and available in the result buffer Value Mode Description 0 DISABLE Nothing will be stored in the result buffer 1 DATA The sensor sample data will be stored in the result...

Page 998: ...hreshold used for comparison In step detection mode this bitfield is written by LESENSE and contains the value from previous sensor measurement In sliding window mode this bitfield is written by LESENSE and contains the window base for the given channel Reference Manual LESENSE Low Energy Sensor Interface silabs com Building a more connected world Rev 1 1 998 ...

Page 999: ...peripheral that implements a Cyclic Redundancy Check CRC function It supports both 32 bit and 16 bit polynomials The supported 32 bit polynomial is 0x04C11DB7 IEEE 802 3 while the 16 bit polynomial can be programmed to any value depending on the needs of the application Common 16 bit polynomials are 0x1021 CCITT 16 0x3D65 IEC16 MBus and 0x8005 zigbee 802 15 4 and USB 29 2 Features Programmable 16 ...

Page 1000: ...UTDATA byte reorder byte level bit reversal Hardware CRC Calculation Unit Seed bit reversal POLY 0x04C11DB7 16 bit Programmable 32 bit Fixed Polynomial Selection DATA byte reversal DATABYTEREV Figure 29 1 GPCRC Overview Reference Manual GPCRC General Purpose Cyclic Redundancy Check silabs com Building a more connected world Rev 1 1 1000 ...

Page 1001: ...DATAHWORD or GPCRC_INPUTDATABYTE register via the APB bus based on different data size If BYTEMODE in GPCRC_CTRL is set only the least significant byte of the data word will be used for the CRC calculation no matter which input register is written There are also three output registers for different ordering Reading from GPCRC_DATA will get the result based on the polynomial in reversed order while...

Page 1002: ...it 2 bit 0 bit 3 bit 1 bit 7 bit 5 bit 4 bit 6 bit 2 bit 0 bit 3 bit 1 Byte 1 bit 7 bit 5 bit 4 bit 6 bit 2 bit 0 bit 3 bit 1 Byte 2 bit 7 bit 5 bit 4 bit 6 bit 2 bit 0 bit 3 bit 1 Byte 3 bit 7 bit 5 bit 4 bit 6 bit 2 bit 0 bit 3 bit 1 Byte 3 bit 0 bit 2 bit 3 bit 1 bit 5 bit 7 bit 4 bit 6 Byte 2 bit 0 bit 2 bit 3 bit 1 bit 5 bit 7 bit 4 bit 6 Byte 0 bit 0 bit 2 bit 3 bit 1 bit 5 bit 7 bit 4 bit 6...

Page 1003: ... 0 0 0 8 h00 8 h00 Figure 29 4 Data Ordering Example 16 bit MSB first to LSB first Assuming a word input byte order of B3 B2 B1 B0 the values used in the CRC calculation for the various settings of the byte level bit reversal and byte reordering are shown in Table 29 1 Byte Level Bit Reversal and Byte Reordering Results B3 B2 B1 B0 Input Order on page 1003 Table 29 1 Byte Level Bit Reversal and By...

Page 1004: ...rol Register 0x004 GPCRC_CMD W1 Command Register 0x008 GPCRC_INIT RWH CRC Init Value 0x00C GPCRC_POLY RW CRC Polynomial Value 0x010 GPCRC_INPUTDATA W Input 32 bit Data Register 0x014 GPCRC_INPUTDATAHWORD W Input 16 bit Data Register 0x018 GPCRC_INPUTDATABYTE W Input 8 bit Data Register 0x01C GPCRC_DATA R CRC Data Register 0x020 GPCRC_DATAREV R CRC Data Reverse Register 0x024 GPCRC_DATABYTEREV R CR...

Page 1005: ...B3 B2 B1 B0 within the 32 bit data word Value Mode Description 0 NORMAL No reverse B3 B2 B1 B0 1 REVERSED Reverse byte order For 32 bit B0 B1 B2 B3 For 16 bit 0 0 B0 B1 9 BITREVERSE 0 RW Byte level Bit Reverse Enable Reverses bits within each byte of the 32 bit data word Value Mode Description 0 NORMAL No reverse 1 REVERSED Reverse bit order in each byte 8 BYTEMODE 0 RW Byte Mode Enable Treats all...

Page 1006: ...2 1 0 Reset 0 Access W1 Name INIT Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 0 INIT 0 W1 Initialization Enable Writing 1 to this bit initialize the CRC by writing the INIT value in CRC_INIT to CRC_DATA 29 5 3 GPCRC_INIT CRC Init Value Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 ...

Page 1007: ...ing that the lowest degree term is in the highest bit position of POLY Additionally the highest degree term in the polynomial is implicit Further examples of the CRC configuration can be found in the documen tation 29 5 5 GPCRC_INPUTDATA Input 32 bit Data Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access...

Page 1008: ...is register is written the CRC value is updated 29 5 7 GPCRC_INPUTDATABYTE Input 8 bit Data Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access W Name INPUTDATABYTE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven ti...

Page 1009: ...TIALIZE command 29 5 9 GPCRC_DATAREV CRC Data Reverse Register Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name DATAREV Bit Name Reset Access Description 31 0 DATAREV 0x00000000 R Data Reverse Value Bit reversed version of CRC Data register When a 32 bit CRC polynomial is selected the reversal occurs on t...

Page 1010: ...REV Bit Name Reset Access Description 31 0 DATABYTEREV 0x00000000 R Data Byte Reverse Value Byte reversed version of CRC Data register When a 32 bit CRC polynomial is selected the bytes are swizzled to B0 B1 B2 B3 When a 16 bit CRC polynomial is selected the bytes are swizzled to 0 0 B0 B1 Reference Manual GPCRC General Purpose Cyclic Redundancy Check silabs com Building a more connected world Rev...

Page 1011: ...ng software burden How Ring oscillators and sampling logic combine to pro duce non deterministic random numbers 30 1 Introduction The TRNG module is a non deterministic random number generator based on a full hardware solution The TRNG output passes the NIST 800 22 and AIS31 test suites 30 2 Features Simple bus interface to access random numbers control and status registers 64 x 32 bit FIFO for ra...

Page 1012: ..._generators_e pdf is also implemented in hardware and runs continuously on the data Both the preliminary noise alarm and the noise alarm are optionally available as interrupt sources from the TRNG module If a noise alarm occurs the TRNG will be shut down and must be reset with a software reset Additionally the NIST 800 90B and AIS31 startup tests may be optionally enabled or disabled by software T...

Page 1013: ...m the FIFO in the following order Word 1 0x33221100 Word 2 0x77665544 Word 3 0xBBAA9988 Word 4 0xFFDDEECC This is important to note when checking the conditioning function for validity The KEY registers also follow this standard with KEY0 holding the MSB of a 128 bit value and KEY3 holding the LSB 30 3 4 TRNG Usage It is highly recommended to use the software libraries provided by Silicon Labs to ...

Page 1014: ...ABUSY 0 after each write 5 Read the 128 bit result from the FIFO 32 bits at a time Table 30 1 Known Answer Test for Conditioning Function on page 1014 shows an example with a given key known data input and expected output taken from section F 2 1 in http csrc nist gov publications nistpubs 800 38a sp800 38a pdf Table 30 1 Known Answer Test for Conditioning Function 128 bit Format 32 bit Bus Format...

Page 1015: ...r the STATUS_FULLIF flag to set indicating the FIFO is full Note that STATUS_FULLIF may be configured to generate an interrupt if desired 2 When FIFOLEVEL has reached the expected value or when STATUS_FULLIF is set read the random numbers using the FIFO register 3 Use four 32 bit random values to program a random key to the KEY0 KEY1 KEY2 and KEY3 registers 4 Apply a software reset by setting CONT...

Page 1016: ...31 startup test is bypassed 12 BYPNIST 0 RW NIST Start up Test Bypass Bypass for NIST 800 90B startup test Value Mode Description 0 NORMAL NIST 800 90B startup test is applied No data will be written to the FIFO until the test passes 1 BYPASS NIST 800 90B startup test is bypassed 11 FORCERUN 0 RW Oscillator Force Run Set this bit to force oscillators to run even when FIFO is full Value Mode Descri...

Page 1017: ...ailure interrupt 3 CONDBYPASS 0 RW Conditioning Bypass Enables bypassing of the conditioning function to observe entropy source directly Value Mode Description 0 NORMAL The conditionig function is used 1 BYPASS The conditioning function is bypassed 2 TESTEN 0 RW Test Enable Selects the input for the conditioning function and continuous tests Value Mode Description 0 NOISE Non determinsitc random n...

Page 1018: ...data available in the FIFO The STATUS_FULLIF flag is cleared when FIFOLEVEL is read 30 5 3 TRNGn_FIFODEPTH FIFO Depth Register Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000040 Access R Name VALUE Bit Name Reset Access Description 31 0 VALUE 0x00000040 R FIFO Depth Maximum number of 32 bit words that can be stored in th...

Page 1019: ...0x00000000 RW Key 0 AES Key 32 bit sub word 0 MSB 30 5 5 TRNGn_KEY1 Key Register 1 Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name VALUE Bit Name Reset Access Description 31 0 VALUE 0x00000000 RW Key 1 AES Key 32 bit sub word 1 Reference Manual TRNG True Random Number Generator silabs com Building a mor...

Page 1020: ...0x00000000 RW Key 2 AES Key 32 bit sub word 2 30 5 7 TRNGn_KEY3 Key Register 3 Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name VALUE Bit Name Reset Access Description 31 0 VALUE 0x00000000 RW Key 3 AES Key 32 bit sub word 3 LSB Reference Manual TRNG True Random Number Generator silabs com Building a mor...

Page 1021: ...function or to the continuous tests Each word written to this register represents 32 bits of input data for the selected test in test mode CONTROL_TESTEN 1 TESTDATABUSY in the STATUS register will be set to 1 each time data is written and will clear to 0 when the next data word can be written Writes to this register are ignored if the TESTEN bit in the CONTROL register is 0 Reference Manual TRNG T...

Page 1022: ...he STATUS_FULLIF flag is cleared by reading FIFOLEVEL 6 APT4096IF 0 R Adaptive Proportion test failure 4096 sample window interrupt status Set when an Adaptive Proportion test 4096 sample window failure occurs 5 APT64IF 0 R Adaptive Proportion test failure 64 sample window interrupt sta tus Set when an Adaptive Proportion test 64 sample window failure occurs 4 REPCOUNTIF 0 R Repetition Count Test ...

Page 1023: ...ALUE 0xFF RW Wait counter value Number of clock cycles to wait before sampling data from the noise source 30 5 11 TRNGn_FIFO FIFO Data Actionable Reads Offset Bit Position 0x100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name VALUE Bit Name Reset Access Description 31 0 VALUE 0x00000000 R FIFO Read Data Data may be read from the ...

Page 1024: ...f 128 bit 256 bit or 512 bit registers to implement or accelerate Elliptic Curve Cryptography ECC SHA 1 SHA 224 SHA 256 and various block cipher modes based on the Advanced Encryption Standard also known as AES FIPS 197 CRYPTO is capable of autonomously fetching data performing cipher operations and storing data across multiple blocks When the source data is not a multiple of 16 bytes 128 bits Zer...

Page 1025: ...h BUFC the buffer controller DMA request signals for data read and write Optional XOR Data write Interrupt on finished operations Extensive software support Extensive software library in Simplicity Studio Implements all major cryptographic algorithms AES SHA 1 SHA 2 and ECC Implements legacy algorithms DES 3DES MD4 MD5 and RC4 Hardware accelerated when possible 31 3 Usage and Programming Interface...

Page 1026: ...TRANSFER Sequencer DATA1 127 0 DATA0 127 0 DATA3 127 0 DATA2 127 0 KEYBUF 255 0 KEY 255 0 DDATA0 255 0 AHB bus Control DDATA4 255 0 DDATA1 255 0 DDATA0 255 0 DDATA2 255 0 DDATA3 255 0 QDATA0 511 0 QDATA1 511 0 Figure 31 1 CRYPTO Overview Reference Manual CRYPTO Crypto Accelerator silabs com Building a more connected world Rev 1 1 1026 ...

Page 1027: ...lue in DATA0 This is used in a large variety of block cipher modes All of these registers operate on DATA0 DATA1 can be accessed through CRYPTO_DATA1 32 bit and CRYPTO_DATA1BYTE 8 bit The remaining data registers have regular 32 bit access through their respective registers Note that all data registers require a full read or write to be fully accessed This means that the 128 bit registers need fou...

Page 1028: ...t LSB Write data CRYPTO_DDATA2 DATA1 Read data DDATA2 256 bit DATA0 CRYPTO_DDATA3 DATA3 Read data DDATA3 256 bit DATA2 Write data Write data CRYPTO_DDATA1 KEY Read data DDATA1 256 bit Write data CRYPTO_DDATA4 KEYBUF Read data DDATA4 256 bit Write data CRYPTO_QDATA0 DDATA1 Read data QDATA0 512 bit DDATA0 CRYPTO_QDATA1 DDATA3 Read data QDATA1 512 bit DDATA2 Write data Figure 31 2 CRYPTO Data and Key...

Page 1029: ...t clear DDATA2 DDATA3 MSBs Since the DATA0 DATA3 registers are always 128 bit all bit positions greater than 128 are interpreted as 0 when RESULTWIDTH is greater than 128 bits However the assignment instructions DATAxTODDATAy will not zero out the upper 128 bits of the DDATAy tar get Instead those upper words become undefined after such operations 31 4 2 Instructions and Execution The CRYPTO modul...

Page 1030: ...ion or set SEQSTART in CRYPTO_CMD CRYPTO will then execute the instructions starting in CRYPTO_SEQ0 and ending at the first END instruction SEQRUNNING in CRYPTO_STATUS is set while the sequence is running and the interrupt flag SEQDONE in CRYPTO_IF will be set when the sequence has completed A sequence can be stopped by issuing the SEQSTOP command in the CRYPTO_CMD register This command also clear...

Page 1031: ...ry is only set not cleared If V0 DDATA0 then V1 DDATA0 ADDC DDATA0 V0 V1 carry If V0 DDATA0 then V1 DDATA0 ADDIC DDATA0 V0 V1 carry 128 If V0 DDATA0 then V1 DDATA0 If resultwidth is 128b then carry is undefined MADD DDATA0 V0 V1 mod P If V0 DDATA0 then V1 DDATA0 MADD32 DDATA0 i V0 i V1 i Word wise addition carry is not modified If V0 DDATA0 then V1 DDATA0 SUB DDATA0 V0 V1 V1 DDATA0 If V1 is 128b a...

Page 1032: ...uest DATA0WR DATAX DATA0 DDATA0 DDATA0BIG QDATA0 DMA0TODATAXOR DATA0 DATA0 DMA DMA request DATA0XORWR DATATODMA1 DMA DATAX DMA request DMA1RD DATAX DATA1 DDATA1 QDATA1 QDATA1BIG as defined by DMA1RSEL DMA1TODATA DATAX DMA DMA request DATA0WR DATAX DATA1 DDATA1 QDATA1 QDATA1BIG DATAxTODATAy DATAy DATAx DATAxTODATA0XOR DATA0 DATA0 DATAx If resultwidth is 128b then carry is undefined DATAxTODATA0XOR ...

Page 1033: ... DATA1 clearinc DATA1 See 31 4 2 4 DATA1INC and DATA1INCCLR Instructions 31 4 2 3 MULx Details For the MULx instructions not MMUL MULWIDTH in CRYPTO_WAC specifies the width of operands DDATA1 and sometimes V1 This is useful in order to optimize performance because multiplications take the same number of cycles as the bits in the operands plus a couple of cycles for setup As with the other ALU inst...

Page 1034: ...GTHA in CRYPTO_SEQCTRL to the number of bytes in the set and BLOCKSIZE to the size of the blocks in the set The sequence will then be repeated N times where N is LENGTHA BLOCKSIZE if LENGTHA is a multiple of BLOCKSIZE or ceiling LENGTHA BLOCKSIZE if not In the latter case data written by DMA or received from BUFC will be zero padded up to BLOCKSIZE if it is written to a register which has a size e...

Page 1035: ...s the CipherKey This key must be loaded into the KEY regis ters prior to the decryption After one decryption the resulting key will be the PlainKey The resulting PlainKey CipherKey is only de pendent on the value in the KEY registers before encryption decryption The resulting keys and data are shown in Figure 31 4 CRYPTO Key and Data Definitions on page 1035 PlainText CipherText PlainKey CipherKey...

Page 1036: ... S0 0 S0 1 S1 0 S1 1 S2 0 S2 1 S0 2 S0 3 S1 2 S1 3 S2 2 S2 3 S3 2 S3 3 S3 0 S3 1 KEY0 KEY1 KEY2 KEY3 a16 a20 a17 a21 a18 a22 a24 a28 a25 a29 a26 a30 a27 a31 a19 a23 Figure 31 5 CRYPTO Data and Key Orientation as Defined in the Advanced Encryption Standard Reference Manual CRYPTO Crypto Accelerator silabs com Building a more connected world Rev 1 1 1036 ...

Page 1037: ...FF53A 0xC3D2E1F0 0xFFC00B31 0x510E527F 0x00000000 0x68581511 0x9B05688C 0x00000000 0x64F98FA7 0x1F83D9AB 0x00000000 0xBEFA4FA4 0x5BE0CD19 Table 31 6 SHA Preparations STEP ACTION Description STEP0 DDATA1TODDATA0 Copy init data to DDATA0 STEP1 SELDDATA0DDATA1 Select DDATA0 and DDATA1 as operands for SHA instruction Then for each 512 bit block write the block to CRYPTO_QDATA1BIG execute the instructi...

Page 1038: ...structions DATATODMA1 Full CRYPTO_DATA1 CRYPTO_DDATA1 CRYP TO_QDATA1 or CRYPTO_QDATA1BIG read depending on DMA1MODE in CRYPTO_CTRL Note DMAxRSEL in CRYPTO_CTRL has to be set to the data registers that are to be read using the respective DMA channels on a DATATODMAx instruction As an important note DMAxRSEL in CRYPTO_CTRL selects what is read from any of the selectable read registers during an ongo...

Page 1039: ...n the 32 bit aligned word and not the 4 N words at the end To achieve this set DxDMAREADMODE in CRYPTO_CTRL to either UN ALIGNEDFULL or UNALIGNEDLENLIMIT and set DATAxDMASKIP in CRYPTO_SEQCTRL equal to N When reading in data using a DMA oriented instruction to DATAx DDATAx or QDATAx the read will now only contain the 16 bytes and not the N bytes before or 4 N words after Note that in this case the...

Page 1040: ...lso written e g a full number of 16 byte buffers are written to the BUFC Note The buffer selected by READBUFSEL and WRITEBUFSEL in the CRYPTO_CTRL registers must be appropriately configured in the BUFC module prior to using instructions involving BUFC All BUFC reads start at the current BUFC read pointer and move the pointer according to the number of bytes read BUFC writes nor mally also work in ...

Page 1041: ... can be read from SEQIP in CRYPTO_CSTATUS SEQSKIP also in CRYPTO_CSTATUS tells whether the next instruction will be executed or not based on previous conditionals in the program SEQ PART in CRYPTO_CSTATUS shows whether CRYPTO is currently in part A or B of a sequence Even with NOBUSYSTALL in CRYP TO_CTRL cleared read and write accesses to CRYPTO will be allowed when CRYPTO is waiting to be stepped...

Page 1042: ...THA in CRYPTO_SEQCTRL Finally the buffers selec ted by READBUFSEL and WRITEBUFSEL must be configured correctly in the BUFC The sequence is started by issuing the SEQ START command in CRYPTO_CMD In Figure 31 7 CBC Encryption Operation on page 1042 the CBC encryption is illustrated and in Table 31 9 CBC Encryption Steps on page 1042 each step in the loop is explained Loop 0 DATA0 DATA1 BUF a8 a12 a1...

Page 1043: ... illustrated and in Table 31 10 CBC Decryption Steps on page 1043 each step in the loop is explained Loop 0 DATA0 DATA1 BUF a0 a4 a1 a5 a2 a6 a8 a12 a13 a10 a14 S0 1 C0 S0 2 S0 3 S1 3 S2 3 a16 a20 a17 a18 a24 a28 a25 a29 a26 a30 CBC Decryption C0 IV C0 E C0 E C0 XOR IV a0 a4 a1 a5 a2 a6 X C1 S0 2 S0 3 S2 3 E C1 E C1 XOR C0 E C0 C1 C0 C1 C0 Loop 1 IV Init 1 2 3 4 5 1 2 3 4 5 Steps Steps Figure 31 8...

Page 1044: ...C CRYPTO_SEQ3 RW Sequence Register 3 0x060 CRYPTO_SEQ4 RW Sequence Register 4 0x080 CRYPTO_DATA0 RWH nB a DATA0 Register Access 0x084 CRYPTO_DATA1 RWH nB a DATA1 Register Access 0x088 CRYPTO_DATA2 RWH nB a DATA2 Register Access 0x08C CRYPTO_DATA3 RWH nB a DATA3 Register Access 0x0A0 CRYPTO_DATA0XOR RWH nB a DATA0XOR Register Access 0x0B0 CRYPTO_DATA0BYTE RWH nB a DATA0 Register Byte Access 0x0B4 C...

Page 1045: ... Access 0x148 CRYPTO_DDATA0BYTE32 RWH nB DDATA0 Register Byte 32 Access 0x180 CRYPTO_QDATA0 RWH nB a QDATA0 Register Access 0x184 CRYPTO_QDATA1 RWH nB a QDATA1 Register Access 0x1A4 CRYPTO_QDATA1BIG RWH nB a QDATA1 Register Big Endian Access 0x1C0 CRYPTO_QDATA0BYTE RWH nB a QDATA0 Register Byte Access 0x1C4 CRYPTO_QDATA1BYTE RWH nB a QDATA1 Register Byte Access Reference Manual CRYPTO Crypto Accel...

Page 1046: ...lect Specifies which read register is used for DMA1RD DMA requests see related notes in 31 4 8 DMA and 31 4 3 Repeated Sequence Value Mode Description 0 DATA1 1 DDATA1 2 QDATA1 3 QDATA1BIG 27 26 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 25 24 DMA1MODE 0x0 RW DMA1 Read Mode This field determines how data is read when using DMA V...

Page 1047: ...are less bytes available than the register size only length necessary zero padding is read Zero padding is automatically added when writing 2 FULLBYTE Target register is fully read written during every DMA transaction Byte wise DMA 3 LENLIMITBYTE Length Limited When the current length i e LENGTHA or LENGTHB indicates that there are less bytes available than the register size only length necessary ...

Page 1048: ... Select SHA 1 or SHA 2 mode Value Mode Description 0 SHA1 SHA 1 mode 1 SHA2 SHA 2 mode SHA 224 or SHA 256 1 KEYBUFDIS 0 RW Key Buffer Disable Set to Disable key buffering 0 AES 0 RW AES Mode Select AES mode Value Mode Description 0 AES128 AES 128 mode 1 AES256 AES 256 mode Reference Manual CRYPTO Crypto Accelerator silabs com Building a more connected world Rev 1 1 1048 ...

Page 1049: ...S in CRYPTO_STATUS 9 8 MULWIDTH 0x0 RW Multiply Width Number of bits to multiply on non modulus multiply instruction Value Mode Description 0 MUL256 Multiply 256 bits 1 MUL128 Multiply 128 bits 2 MULMOD Same number of bits as specified by MODULUS 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 4 MODOP 0 RW Modular Operation Field...

Page 1050: ... 1 6 ECCPRIME224P Modulus for P 224 ECC curve p 2 224 2 96 1 7 ECCPRIME192P Modulus for P 192 ECC curve p 2 192 2 64 1 8 ECCBIN233N P modulus for B 233 ECC curve 9 ECCBIN233KN P modulus for K 233 ECC curve 10 ECCBIN163N P modulus for B 163 ECC curve 11 ECCBIN163KN P modulus for K 163 ECC curve 12 ECCPRIME256N P modulus for P 256 ECC curve 13 ECCPRIME224N P modulus for P 224 ECC curve 14 ECCPRIME19...

Page 1051: ... SEQUENCE 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 7 0 INSTR 0x00 W Execute Instruction Write to this field to perform any of the instructions described below Illegal values are ignored See 31 4 2 2 Available In structions for details and requirements of each instruction Value Mode Description 0 END End of program 1 EXEC Sta...

Page 1052: ... XOR XOR 50 INV Invert operand 52 CSET Carry set 53 CCLR Carry clear 54 BBSWAP128 See detailed instruction listing 56 INC Increment DDATA0 57 DEC Decrement DDATA0 62 SHRA Arithmetic shift right 64 DATA0TODATA0 DATA0 DATA0 65 DATA0TODATA0XOR DATA0 DATA0 DATA0 66 DATA0TODATA0XOR LEN DATA0 len 1 0 DATA0 len 1 0 DATA0 len 1 0 68 DATA0TODATA1 DATA1 DATA0 69 DATA0TODATA2 DATA2 DATA0 70 DATA0TODATA3 DATA...

Page 1053: ...ATAXOR See detailed instruction listing 114 DMA1TODATA See detailed instruction listing 120 BUFTODATA0 See detailed instruction listing 121 BUFTODATA0XOR See detailed instruction listing 122 BUFTODATA1 See detailed instruction listing 129 DDATA0TODDATA1 DDATA1 DDATA0 130 DDATA0TODDATA2 DDATA2 DDATA0 131 DDATA0TODDATA3 DDATA3 DDATA0 132 DDATA0TODDATA4 DDATA4 DDATA0 133 DDATA0LTODATA0 DATA0 DDATA0 1...

Page 1054: ...DATA1 DDATA1 DATA1 184 DATA2TODDATA0 DDATA0 DATA2 185 DATA2TODDATA1 DDATA1 DATA2 186 DATA2TODDATA2 DDATA2 DATA2 192 SELDDATA0DDATA0 Use DDATA0 as V0 DDATA0 as V1 193 SELDDATA1DDATA0 Use DDATA1 as V0 DDATA0 as V1 194 SELDDATA2DDATA0 Use DDATA2 as V0 DDATA0 as V1 195 SELDDATA3DDATA0 Use DDATA3 as V0 DDATA0 as V1 196 SELDDATA4DDATA0 Use DDATA4 as V0 DDATA0 as V1 197 SELDATA0DDATA0 Use DATA0 as V0 DDA...

Page 1055: ...s V1 223 SELDATA2DDATA3 Use DATA2 as V0 DDATA2 as V1 224 SELDDATA0DDATA4 Use DDATA0 as V0 DDATA4 as V1 225 SELDDATA1DDATA4 Use DDATA1 as V0 DDATA4 as V1 226 SELDDATA2DDATA4 Use DDATA2 as V0 DDATA4 as V1 227 SELDDATA3DDATA4 Use DDATA3 as V0 DDATA4 as V1 228 SELDDATA4DDATA4 Use DDATA4 as V0 DDATA4 as V1 229 SELDATA0DDATA4 Use DATA0 as V0 DDATA4 as V1 230 SELDATA1DDATA4 Use DATA1 as V0 DDATA4 as V1 2...

Page 1056: ...atus Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access R R R Name DMAACTIVE INSTRRUNNING SEQRUNNING Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 2 DMAACTIVE 0 R DMA Action is Active This bit indicates th...

Page 1057: ...depend on RESULTWIDTH in CRYPTO_WAC 19 16 DDATA0MSBS 0xX R MSB in DDATA0 Allows read of 4 MSBs in DDATA0 The bits depend on RESULTWIDTH in CRYPTO_WAC 15 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 11 8 DDATA0LSBS 0xX R LSBs in DDATA0 Allows read of 4 LSBs in DDATA0 7 4 Reserved To ensure compatibility with future devices alway...

Page 1058: ...information in 1 2 Conven tions 17 SEQSKIP 0 R Sequence Skip Next Instruction When in halted sequence tells whether next instruction will be skipped 16 SEQPART 0 R Sequence Part Shows whether currently in part A or B of a sequence Value Mode Description 0 SEQA 1 SEQB 15 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 10 8 V1 0x2 R...

Page 1059: ...s Actionable Reads Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name KEY Bit Name Reset Access Description 31 0 KEY 0xXXXXXXX X RWH Key Access Access the KEY 4x32bits 8x32bits if AES256 in CRYPTO_CTRL is set read write accesses are required to fully read write KEY Reference Manual CRYPTO Crypto Accelerat...

Page 1060: ... 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name KEYBUF Bit Name Reset Access Description 31 0 KEYBUF 0xXXXXXXX X RWH Key Buffer Access Access to KEYBUF 4x32bits 8x32bits if AES256 in CRYPTO_CTRL is set read write accesses are required to fully read write KEYBUF Reference Manual CRYPTO Crypto Accelerator silabs com Building a more connected world Rev 1 1 1060 ...

Page 1061: ...ip Set to number of bytes to exclude from data received by next DMA1RD insruction 25 24 DMA0SKIP 0x0 RWH DMA0 Skip Set to number of bytes to exclude from data received by next DMA0RD insruction 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 21 20 BLOCKSIZE 0x0 RW Size of Data Blocks Defines the width of blocks processed in eac...

Page 1062: ...n If only the second part of a data set is written enable only this to preserve the data read in during part A 28 DMA0PRESB 0 RW DMA0 Preserve B For unaligned sequences set this bit along with DMA0PRESA for in place conversions where all data is written out from CRYPTO again If only the second part of a data set is written enable only this to preserve the data read in during part A 27 14 Reserved ...

Page 1063: ...ys write bits to 0 More information in 1 2 Conven tions 3 BUFUF 0 R Buffer Underflow Set if the buffer READBUFFER experiences an underflow when attempting a read 2 BUFOF 0 R Buffer Overflow Set if the buffer WRITEBUFFER experiences an overflow when attempting a write 1 SEQDONE 0 R Sequence Done Set when an instruction sequence has completed 0 INSTRDONE 0 R Instruction Done Set when an instruction ...

Page 1064: ... future devices always write bits to 0 More information in 1 2 Conven tions 3 BUFUF 0 W1 Set BUFUF Interrupt Flag Write 1 to set the BUFUF interrupt flag 2 BUFOF 0 W1 Set BUFOF Interrupt Flag Write 1 to set the BUFOF interrupt flag 1 SEQDONE 0 W1 Set SEQDONE Interrupt Flag Write 1 to set the SEQDONE interrupt flag 0 INSTRDONE 0 W1 Set INSTRDONE Interrupt Flag Write 1 to set the INSTRDONE interrupt...

Page 1065: ...be enabled globally in MSC 2 BUFOF 0 R W1 Clear BUFOF Interrupt Flag Write 1 to clear the BUFOF interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 1 SEQDONE 0 R W1 Clear SEQDONE Interrupt Flag Write 1 to clear the SEQDONE interrupt flag Reading returns the value of the IF and clears the corresponding interrup...

Page 1066: ...Enable disable the INSTRDONE interrupt 31 6 15 CRYPTO_SEQ0 Sequence Register 0 Offset Bit Position 0x050 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 0x00 Access RW RW RW RW Name INSTR3 INSTR2 INSTR1 INSTR0 Bit Name Reset Access Description 31 24 INSTR3 0x00 RW Sequence Instruction 3 Sequence instruction See INSTR in CRYPTO_CMD for a po...

Page 1067: ...on See INSTR in CRYPTO_CMD for a possible values 31 6 17 CRYPTO_SEQ2 Sequence Register 2 Offset Bit Position 0x058 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 0x00 Access RW RW RW RW Name INSTR11 INSTR10 INSTR9 INSTR8 Bit Name Reset Access Description 31 24 INSTR11 0x00 RW Sequence Instruction 11 Sequence instruction See INSTR in CRYPT...

Page 1068: ...ction See INSTR in CRYPTO_CMD for a possible values 31 6 19 CRYPTO_SEQ4 Sequence Register 4 Offset Bit Position 0x060 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 0x00 Access RW RW RW RW Name INSTR19 INSTR18 INSTR17 INSTR16 Bit Name Reset Access Description 31 24 INSTR19 0x00 RW Sequence Instruction 19 Sequence instruction See INSTR in ...

Page 1069: ...ite accesses are required to fully read write DATA0 31 6 21 CRYPTO_DATA1 DATA1 Register Access No Bit Access Actionable Reads Offset Bit Position 0x084 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name DATA1 Bit Name Reset Access Description 31 0 DATA1 0xXXXXXXX X RWH Data 1 Access Access to DATA1 4x32bits read write accesses are...

Page 1070: ...ite accesses are required to fully read write DATA2 31 6 23 CRYPTO_DATA3 DATA3 Register Access No Bit Access Actionable Reads Offset Bit Position 0x08C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name DATA3 Bit Name Reset Access Description 31 0 DATA3 0xXXXXXXX X RWH Data 3 Access Access to DATA3 4x32bits read write accesses are...

Page 1071: ...ull XOR write to DATA0 31 6 25 CRYPTO_DATA0BYTE DATA0 Register Byte Access No Bit Access Actionable Reads Offset Bit Position 0x0B0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXX Access RWH Name DATA0BYTE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven...

Page 1072: ...y may occur 31 6 27 CRYPTO_DATA0XORBYTE DATA0 Register Byte XOR Access No Bit Access Actionable Reads Offset Bit Position 0x0BC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXX Access RWH Name DATA0XORBYTE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven ...

Page 1073: ...X RWH Data 0 Byte 12 Access Access to DATA0 byte 12 31 6 29 CRYPTO_DATA0BYTE13 DATA0 Register Byte 13 Access No Bit Access Offset Bit Position 0x0C4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXX Access RWH Name DATA0BYTE13 Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More inform...

Page 1074: ...X RWH Data 0 Byte 14 Access Access to DATA0 byte 14 31 6 31 CRYPTO_DATA0BYTE15 DATA0 Register Byte 15 Access No Bit Access Offset Bit Position 0x0CC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXX Access RWH Name DATA0BYTE15 Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More inform...

Page 1075: ... write DDATA0 31 6 33 CRYPTO_DDATA1 DDATA1 Register Access No Bit Access Actionable Reads Offset Bit Position 0x104 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name DDATA1 Bit Name Reset Access Description 31 0 DDATA1 0xXXXXXXX X RWH Double Data 0 Access Access to DDATA1 which is equal to the full width of KEY regardless of AES2...

Page 1076: ...e accesses are required to fully read write DDA TA2 31 6 35 CRYPTO_DDATA3 DDATA3 Register Access No Bit Access Actionable Reads Offset Bit Position 0x10C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name DDATA3 Bit Name Reset Access Description 31 0 DDATA3 0xXXXXXXX X RWH Double Data 0 Access Access to DDATA3 which consists of DA...

Page 1077: ... 8x32bits read write accesses are required to fully read write DDATA4 31 6 37 CRYPTO_DDATA0BIG DDATA0 Register Big Endian Access No Bit Access Actionable Reads Offset Bit Position 0x130 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name DDATA0BIG Bit Name Reset Access Description 31 0 DDATA0BIG 0xXXXXXXX X RWH Double Data 0 Big En...

Page 1078: ...med in multiples of 4 or data incoherency may occur 31 6 39 CRYPTO_DDATA1BYTE DDATA1 Register Byte Access No Bit Access Actionable Reads Offset Bit Position 0x144 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXX Access RWH Name DDATA1BYTE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to ...

Page 1079: ...Access Access to DDATA0 byte 32 This is used when RESULTWIDTH in CRYPTO_WAC is set to 260BIT 31 6 41 CRYPTO_QDATA0 QDATA0 Register Access No Bit Access Actionable Reads Offset Bit Position 0x180 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name QDATA0 Bit Name Reset Access Description 31 0 QDATA0 0xXXXXXXX X RWH Quad Data 0 Acces...

Page 1080: ...red to fully read write QDATA1 31 6 43 CRYPTO_QDATA1BIG QDATA1 Register Big Endian Access No Bit Access Actionable Reads Offset Bit Position 0x1A4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RWH Name QDATA1BIG Bit Name Reset Access Description 31 0 QDATA1BIG 0xXXXXXXX X RWH Quad Data 1 Big Endian Access Big endian access to QDATA1 w...

Page 1081: ...med in multiples of 4 or data incoherency may occur 31 6 45 CRYPTO_QDATA1BYTE QDATA1 Register Byte Access No Bit Access Actionable Reads Offset Bit Position 0x1C4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXX Access RWH Name QDATA1BYTE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to ...

Page 1082: ...ame pin Fully asynchronous interrupts can also be generated from any pin 32 1 Introduction In the EFR32 devices the General Purpose Input Output GPIO pins are organized into ports with up to 16 pins each These GPIO pins can individually be configured as either an output or input More advanced configurations like open drain open source and glitch filter ing can be configured for each individual GPI...

Page 1083: ...ata can be overridden by peripheral Output enable can be overridden by peripheral Toggle register for output data Dedicated data input register read only Interrupts 2 Interrupt lines using either levels or edges EM4 wake up pins are selectable for level interrupts All GPIO pins are selectable for edge interrupts Separate enable status set and clear registers Asynchronous sensing Rising falling or ...

Page 1084: ...in the register is connected to pin n on the port When configured as an output the value of the Data Out Register GPIO_Px_DOUT will be driven to the pin The DOUT value can be changed in 4 different ways Writing to the GPIO_Px_DOUT register Writing the BITSET address of the GPIO_Px_DOUT register sets the DOUT bits Writing the BITCLEAR address of the GPIO_Px_DOUT register clears the DOUT bits Writin...

Page 1085: ...L Push pull x Push pull PUSHPULLALT x On Push pull with alternate port control values WIREDOR Open Source Wired OR x Open source WIREDORPULLDOWN x On Open source with pull down WIREDAND Open Drain Wired AND x Open drain WIREDANDFILTER x On Open drain with filter WIREDANDPULLUP x On Open drain with pull up WIREDANDPULLUPFILTER x On On Open drain with pull up and filter WIREDANDALT x On Open drain w...

Page 1086: ... 3 Push Pull Configuration on page 1086 Input Enable DOUT DIN Output Enable Figure 32 3 Push Pull Configuration When MODEn is WIREDOR or WIREDORPULLDOWN the pin operates in open source mode with a pull down resistor for WIRE DORPULLDOWN When driving a high value in open source mode the pull down is disconnected to save power When the mode is prefixed with WIREDAND the pin operates in open drain mo...

Page 1087: ...2 3 1 3 Drive Strength The drive strength can be applied to pins on a port by port basis The drive strength applied to pins configured using normal MODEn settings can be controlled using the DRIVESTRENGTH field in GPIO_Px_CTRL The drive strength applied to pins configured using alternate MODEn settings can be controlled using the DRIVESTRENGTHALT field 32 3 1 4 Slewrate The slewrate can be applied...

Page 1088: ...PIO_IF register The mapping between EM4WU pins and the bit indexes in the GPIO_EM4WUEN GPIO_EXTILEVEL GPIO_IFC GPIO_IFS GPIO_IEN and GPIO_IF registers is as follows Table 32 2 EM4WU Register Bit Index to EM4WU Pin Mapping EM4WU Register Bit Indexes EM4WU Pin 16 GPIO_EM4WU0 17 GPIO_EM4WU1 18 GPIO_EM4WU2 19 GPIO_EM4WU3 31 GPIO_EM4WU15 Note See the device data sheet for actual pin location 32 3 3 EM4...

Page 1089: ...th internal pull up and pull down resistors respectively It is possible to disable these pin connections and disable the pull resistors by setting the SWDIOTMSPEN and SWCLKTCKPEN bits in GPIO_ROUTEPEN to 0 The Serial Wire Viewer pin SWV can be enabled by setting the SWVPEN bit in GPIO_ROUTEPEN This bit can also be routed to alternate locations by configuring the SWVLOC bitfield in GPIO_ROUTELOC0 3...

Page 1090: ...TIPSELn bits in GPIO_EXTIPSELL or GPIO_EXTIPSELH select which PORT in the group will trigger the interrupt The EXTI PINSELn bits in GPIO_EXTIPINSELL or GPIO_EXTIPINSELH will determine which pin inside the selected group will trigger the inter rupt For example if EXTIPSEL11 PORTB and EXTPINSEL11 0 then PB8 will be used for EXTI11 EXTI11 uses the third group 11 4 2 so the list of possible pins is Px...

Page 1091: ...O_IF will be triggered by a high level on pin EM4WU8 and a interrupt request will be sent on IRQ_GPIO_EVEN Figure 32 7 Level Interrupt Example 32 3 6 Output to PRS All pins within a group of four 0 3 4 7 8 11 12 15 from all ports are grouped together to form one PRS producer which outputs to the PRS The pin from which the output should be taken is selected in the same fashion as the edge interrupt...

Page 1092: ...214 GPIO_PL_MODEL RW Port Pin Mode Low Register 0x218 GPIO_PL_MODEH RW Port Pin Mode High Register 0x21C GPIO_PL_DOUT RW Port Data Out Register 0x228 GPIO_PL_DOUTTGL W1 Port Data Out Toggle Register 0x22C GPIO_PL_DIN R Port Data in Register 0x230 GPIO_PL_PINLOCKN RW Port Unlocked Pins Register 0x238 GPIO_PL_OVTDIS RW Over Voltage Disable for All Modes 0x400 GPIO_EXTIPSELL RW External Interrupt Por...

Page 1093: ...UTEPEN RW I O Routing Pin Enable Register 0x444 GPIO_ROUTELOC0 RW I O Routing Location Register 0x450 GPIO_INSENSE RW Input Sense Register 0x454 GPIO_LOCK RWH Configuration Lock Register Reference Manual GPIO General Purpose Input Output silabs com Building a more connected world Rev 1 1 1093 ...

Page 1094: ...ates 19 17 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 16 DRIVESTRENGTH ALT 0 RW Alternate Drive Strength for Port Drive strength setting for port pins using alternate drive strength Value Mode Description 0 STRONG 10 mA drive current 1 WEAK 1 mA drive current 15 13 Reserved To ensure compatibility with future devices always writ...

Page 1095: ...trength for Port Drive strength setting for port pins not using alternate modes Value Mode Description 0 STRONG 10 mA drive current 1 WEAK 1 mA drive current Reference Manual GPIO General Purpose Input Output silabs com Building a more connected world Rev 1 1 1095 ...

Page 1096: ...DOWN Wired or output with pull down 8 WIREDAND Open drain output 9 WIREDANDFILTER Open drain output with filter 10 WIREDANDPULLUP Open drain output with pullup 11 WIREDANDPULLUP FILTER Open drain output with filter and pullup 12 WIREDANDALT Open drain output using alternate control 13 WIREDANDALTFILTER Open drain output using alternate control with filter 14 WIREDANDALTPULL UP Open drain output us...

Page 1097: ...ED Input disabled Pullup if DOUT is set 1 INPUT Input enabled Filter if DOUT is set 2 INPUTPULL Input enabled DOUT determines pull direction 3 INPUTPULLFILTER Input enabled with filter DOUT determines pull direction 4 PUSHPULL Push pull output 5 PUSHPULLALT Push pull using alternate control 6 WIREDOR Wired or output 7 WIREDORPULLDOWN Wired or output with pull down 8 WIREDAND Open drain output 9 WI...

Page 1098: ...in output using alternate control with filter 14 WIREDANDALTPULL UP Open drain output using alternate control with pullup 15 WIREDANDALTPUL LUPFILTER Open drain output using alternate control with filter and pullup 15 12 MODE3 0x0 RW Pin 3 Mode Configure mode for pin 3 Value Mode Description 0 DISABLED Input disabled Pullup if DOUT is set 1 INPUT Input enabled Filter if DOUT is set 2 INPUTPULL Inp...

Page 1099: ...EDAND Open drain output 9 WIREDANDFILTER Open drain output with filter 10 WIREDANDPULLUP Open drain output with pullup 11 WIREDANDPULLUP FILTER Open drain output with filter and pullup 12 WIREDANDALT Open drain output using alternate control 13 WIREDANDALTFILTER Open drain output using alternate control with filter 14 WIREDANDALTPULL UP Open drain output using alternate control with pullup 15 WIRE...

Page 1100: ...t enabled Filter if DOUT is set 2 INPUTPULL Input enabled DOUT determines pull direction 3 INPUTPULLFILTER Input enabled with filter DOUT determines pull direction 4 PUSHPULL Push pull output 5 PUSHPULLALT Push pull using alternate control 6 WIREDOR Wired or output 7 WIREDORPULLDOWN Wired or output with pull down 8 WIREDAND Open drain output 9 WIREDANDFILTER Open drain output with filter 10 WIREDA...

Page 1101: ...ULLDOWN Wired or output with pull down 8 WIREDAND Open drain output 9 WIREDANDFILTER Open drain output with filter 10 WIREDANDPULLUP Open drain output with pullup 11 WIREDANDPULLUP FILTER Open drain output with filter and pullup 12 WIREDANDALT Open drain output using alternate control 13 WIREDANDALTFILTER Open drain output using alternate control with filter 14 WIREDANDALTPULL UP Open drain output...

Page 1102: ...LED Input disabled Pullup if DOUT is set 1 INPUT Input enabled Filter if DOUT is set 2 INPUTPULL Input enabled DOUT determines pull direction 3 INPUTPULLFILTER Input enabled with filter DOUT determines pull direction 4 PUSHPULL Push pull output 5 PUSHPULLALT Push pull using alternate control 6 WIREDOR Wired or output 7 WIREDORPULLDOWN Wired or output with pull down 8 WIREDAND Open drain output 9 W...

Page 1103: ...in output using alternate control with filter 14 WIREDANDALTPULL UP Open drain output using alternate control with pullup 15 WIREDANDALTPUL LUPFILTER Open drain output using alternate control with filter and pullup 15 12 MODE11 0x0 RW Pin 11 Mode Configure mode for pin 11 Value Mode Description 0 DISABLED Input disabled Pullup if DOUT is set 1 INPUT Input enabled Filter if DOUT is set 2 INPUTPULL ...

Page 1104: ...REDAND Open drain output 9 WIREDANDFILTER Open drain output with filter 10 WIREDANDPULLUP Open drain output with pullup 11 WIREDANDPULLUP FILTER Open drain output with filter and pullup 12 WIREDANDALT Open drain output using alternate control 13 WIREDANDALTFILTER Open drain output using alternate control with filter 14 WIREDANDALTPULL UP Open drain output using alternate control with pullup 15 WIR...

Page 1105: ...t enabled Filter if DOUT is set 2 INPUTPULL Input enabled DOUT determines pull direction 3 INPUTPULLFILTER Input enabled with filter DOUT determines pull direction 4 PUSHPULL Push pull output 5 PUSHPULLALT Push pull using alternate control 6 WIREDOR Wired or output 7 WIREDORPULLDOWN Wired or output with pull down 8 WIREDAND Open drain output 9 WIREDANDFILTER Open drain output with filter 10 WIREDA...

Page 1106: ... 5 GPIO_Px_DOUTTGL Port Data Out Toggle Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access W1 Name DOUTTGL Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 DOUTTGL 0x0000 W1 Data Out Toggle Write bits ...

Page 1107: ...7 GPIO_Px_PINLOCKN Port Unlocked Pins Register Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xFFFF Access RW Name PINLOCKN Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 PINLOCKN 0xFFFF RW Unlocked Pins Shows unlocke...

Page 1108: ...DIS Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 OVTDIS 0x0000 RW Disable Over Voltage Capability Disabling the Over Voltage capability will provide less distortion on analog inputs Reference Manual GPIO General Purpose Input Output silabs com Building a more connected world Rev 1 1 110...

Page 1109: ...x0 RW External Interrupt 6 Port Select Select input port for external interrupt 6 Value Mode Description 0 PORTA Port A group selected for external interrupt 6 1 PORTB Port B group selected for external interrupt 6 2 PORTC Port C group selected for external interrupt 6 3 PORTD Port D group selected for external interrupt 6 5 PORTF Port F group selected for external interrupt 6 23 20 EXTIPSEL5 0x0 ...

Page 1110: ...Value Mode Description 0 PORTA Port A group selected for external interrupt 2 1 PORTB Port B group selected for external interrupt 2 2 PORTC Port C group selected for external interrupt 2 3 PORTD Port D group selected for external interrupt 2 5 PORTF Port F group selected for external interrupt 2 7 4 EXTIPSEL1 0x0 RW External Interrupt 1 Port Select Select input port for external interrupt 1 Value...

Page 1111: ...up selected for external interrupt 0 3 PORTD Port D group selected for external interrupt 0 5 PORTF Port F group selected for external interrupt 0 Reference Manual GPIO General Purpose Input Output silabs com Building a more connected world Rev 1 1 1111 ...

Page 1112: ...0 RW External Interrupt 14 Port Select Select input port for external interrupt 14 Value Mode Description 0 PORTA Port A group selected for external interrupt 14 1 PORTB Port B group selected for external interrupt 14 2 PORTC Port C group selected for external interrupt 14 3 PORTD Port D group selected for external interrupt 14 5 PORTF Port F group selected for external interrupt 14 23 20 EXTIPSEL...

Page 1113: ...t 10 Value Mode Description 0 PORTA Port A group selected for external interrupt 10 1 PORTB Port B group selected for external interrupt 10 2 PORTC Port C group selected for external interrupt 10 3 PORTD Port D group selected for external interrupt 10 5 PORTF Port F group selected for external interrupt 10 7 4 EXTIPSEL9 0x0 RW External Interrupt 9 Port Select Select input port for external interru...

Page 1114: ...up selected for external interrupt 8 3 PORTD Port D group selected for external interrupt 8 5 PORTF Port F group selected for external interrupt 8 Reference Manual GPIO General Purpose Input Output silabs com Building a more connected world Rev 1 1 1114 ...

Page 1115: ...ternal interrupt 7 Value Mode Description 0 PIN4 Pin 4 1 PIN5 Pin 5 2 PIN6 Pin 6 3 PIN7 Pin 7 27 26 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 25 24 EXTIPINSEL6 0x2 RW External Interrupt 6 Pin Select Select the pin for external interrupt 6 Value Mode Description 0 PIN4 Pin 4 1 PIN5 Pin 5 2 PIN6 Pin 6 3 PIN7 Pin 7 23 22 Reserved ...

Page 1116: ...ode Description 0 PIN0 Pin 0 1 PIN1 Pin 1 2 PIN2 Pin 2 3 PIN3 Pin 3 11 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 9 8 EXTIPINSEL2 0x2 RW External Interrupt 2 Pin Select Select the pin for external interrupt 2 Value Mode Description 0 PIN0 Pin 0 1 PIN1 Pin 1 2 PIN2 Pin 2 3 PIN3 Pin 3 7 6 Reserved To ensure compatibility with f...

Page 1117: ... More information in 1 2 Conven tions 1 0 EXTIPINSEL0 0x0 RW External Interrupt 0 Pin Select Select the pin for external interrupt 0 Value Mode Description 0 PIN0 Pin 0 1 PIN1 Pin 1 2 PIN2 Pin 2 3 PIN3 Pin 3 Reference Manual GPIO General Purpose Input Output silabs com Building a more connected world Rev 1 1 1117 ...

Page 1118: ...rrupt 15 Value Mode Description 0 PIN12 Pin 12 1 PIN13 Pin 13 2 PIN14 Pin 14 3 PIN15 Pin 15 27 26 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 25 24 EXTIPINSEL14 0x2 RW External Interrupt 14 Pin Select Select the pin for external interrupt 14 Value Mode Description 0 PIN12 Pin 12 1 PIN13 Pin 13 2 PIN14 Pin 14 3 PIN15 Pin 15 23 22 ...

Page 1119: ...de Description 0 PIN8 Pin 8 1 PIN9 Pin 9 2 PIN10 Pin 10 3 PIN11 Pin 11 11 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 9 8 EXTIPINSEL10 0x2 RW External Interrupt 10 Pin Select Select the pin for external interrupt 10 Value Mode Description 0 PIN8 Pin 8 1 PIN9 Pin 9 2 PIN10 Pin 10 3 PIN11 Pin 11 7 6 Reserved To ensure compatibil...

Page 1120: ... 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name EXTIRISE Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 EXTIRISE 0x0000 RW External Interrupt N Rising Edge Trigger Enable Set bit n to enable triggering of external interrupt n...

Page 1121: ...erved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 15 0 EXTIFALL 0x0000 RW External Interrupt N Falling Edge Trigger Enable Set bit n to enable triggering of external interrupt n on falling edge Value Description EXTIFALL n 0 Falling edge trigger dis abled EXTIFALL n 1 Falling edge trigger ena bled Reference Manual GPIO General Purpose Inp...

Page 1122: ...o 0 More information in 1 2 Conven tions 25 EM4WU9 0 RW EM4 Wake Up Level for EM4WU9 Pin 24 EM4WU8 0 RW EM4 Wake Up Level for EM4WU8 Pin 23 21 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 20 EM4WU4 0 RW EM4 Wake Up Level for EM4WU4 Pin 19 18 Reserved To ensure compatibility with future devices always write bits to 0 More informati...

Page 1123: ... Pin n external interrupt flag Value Description 0 External interrupt flag cleared 1 External interrupt flag set 32 5 17 GPIO_IFS Interrupt Flag Set Register Offset Bit Position 0x420 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 0x0000 Access W1 W1 Name EM4WU EXT Bit Name Reset Access Description 31 16 EM4WU 0x0000 W1 Set EM4WU Interrupt Flag W...

Page 1124: ...Clear EXT Interrupt Flag Write 1 to clear the EXT interrupt flag Reading returns the value of the IF and clears the corresponding interrupt flags This feature must be enabled globally in MSC 32 5 19 GPIO_IEN Interrupt Enable Register Offset Bit Position 0x428 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 0x0000 Access RW RW Name EM4WU EXT Bit Na...

Page 1125: ...iption 31 16 EM4WUEN 0x0000 RW EM4 Wake Up Enable Write 1 to enable EM4 wake up request write 0 to disable EM4 wake up request Value Description 0 Disable EM4 wake up on pin 1 Enable EM4 wake up on pin 15 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions Reference Manual GPIO General Purpose Input Output silabs com Building a more co...

Page 1126: ...onnection to pin WARNING When this pin is disabled the device can no longer be accessed by a debugger A reset will set the pin back to a default state as enabled If you disable this pin make sure you have at least a 3 second timeout at the start of you program code before you disable the pin This way the debugger will have time to halt the device after a reset before the pin is disabled 0 SWCLKTCK...

Page 1127: ...n 1 2 LOC2 Location 2 3 LOC3 Location 3 32 5 23 GPIO_INSENSE Input Sense Register Offset Bit Position 0x450 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 1 1 Access RW RW Name EM4WU INT Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in 1 2 Conven tions 1 EM4WU 1 RW EM4...

Page 1128: ...uration Lock Key Write any other value than the unlock code to lock MODEL MODEH CTRL PINLOCKN OVTDIS EXTIPSELL EXTIP SELH EXTIGSELL EXTIGSELH INSENSE ROUTEPEN and ROUTELOC0 from editing Write the unlock code to unlock When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOCKED 0 GPIO registers are unlocked LOCKED 1 GPIO registers are locked Write ...

Page 1129: ...RT control switches the pad and the analog signal onto a common bus 33 1 Introduction APORT consists of wires switches and control logic needed to route signals between analog peripherals and I O pins On chip clients can be either producers or consumers Analog producers are active devices that drive current voltage into an APORT such as current or voltage DACs Consumers are passive devices that mo...

Page 1130: ...operating differentially most APORT clients require that one input be chosen from an X bus and the other from a Y bus For example the ACMP block will not allow both positive and negative inputs to be chosen from X buses 33 3 1 I O Pin Considerations For external analog signals routed through the APORT the maximum supported analog I O voltage will typically be limited to the MIN VANALOGSUPPLY IOVDD...

Page 1131: ...dentify the ABUS in the pair For example BUSDX decodes as BUS ABUS D pair X bus Figure 33 2 Conceptual APORT Structure on page 1131 illustrates this organization APORT clients are generally described once in this reference manual regardless of its number of instances For example the ACMP client is described once but the device could contain multiple instances of the ACMP Because of this for APORT ...

Page 1132: ...4Y 1X POS NEG ADC0 1X 2X 3X 4X 1Y 2Y 3Y 4Y EXTP EXTN POS NEG OPA0 1X 2X 3X 4X 1Y 2Y 3Y 4Y 1X OPA0_P OPA0_N OUT0 OUT0ALT OUT1 OUT2 OUT3 OUT4 OUT POS NEG OPA1 OUT 1X 2X 3X 4X 1Y 2Y 3Y 4Y 1X OPA1_P OPA1_N OUT1 OUT1ALT OUT1 OUT2 OUT3 OUT4 ADC_EXTP ADC_EXTN OUT0 OUT1 OPA0_N OPA0_P OPA1_N OPA1_P VDAC0_OUT0ALT OUT0ALT VDAC0_OUT0ALT OUT0ALT VDAC0_OUT0ALT OUT0ALT VDAC0_OUT1ALT OUT1ALT VDAC0_OUT1ALT OUT1ALT...

Page 1133: ...ive ADC APORT input 2X and the negative ADC APORT input 2Y can be routed to pin PC9 and PC10 via BUSBX and BUSBY respectively with the following configuration Set ADCn_SINGLECTRL_POSSEL APORT2XCH9 This selects the pin PC9 for the positive input to the ADC Set ADCn_SINGLECTRL_NEGSEL APORT2YCH10 This selects the pin PC10 for the negative input to the ADC For smaller packages not all GPIO pins are av...

Page 1134: ...n on a particular ABUS the user might set the bus master disable bit to 1 for the IDAC and ACMP The ADC is the sole master of the switch configuration on that ABUS so switches are configured using the configuration set in the ADC When IDAC or ACMP channels are chosen on that same bus the actual pin connection is dictated by the ADC settings for that bus ACMP0 ABUS 0 ABUS 2 ABUS 4 ABUS 6 ABUS 1 ABU...

Page 1135: ...r client ABUS 4 The user must resolve the conflict before ABUS 4 is useable ACMP0 ABUS 0 ABUS 2 ABUS 4 ABUS 6 ABUS 1 ABUS 3 ABUS 5 ABUS 7 ACMP1 ADC0 APORT_CONTROL APORT_REQ 0000_1111 APORT_REQ 0011_0000 APORT_REQ 0000_0000 Figure 33 6 APORT Example 3 Sharing an ABUS Figure 33 6 APORT Example 3 Sharing an ABUS on page 1135 illustrates ABUS sharing Both ACMPs are configured identically ex cept ACMP0...

Page 1136: ...stereis and riding falling thresholds 11 3 2 4 HFXO Configuration Clarified steady state timeout and state transition to ready 11 3 2 5 LFXO Configuration Added recommendations for GAIN setting 15 3 1 3 Configurable PRS Logic Clarified ANDNEXT and ORPREV behavior for first and last PRS channels 15 3 2 Producers Added more detail about GPIO producer source 15 3 5 DMA Request on PRS Fixed incorrect ...

Page 1137: ... Keying BLE Bluetooth Low Energy BLE LR Bluetooth Low Energy Long Range BR Baud Rate BT Bandwidth Time product BUFC Buffer Controller BW Bandwidth CBC Cipher Block Chaining AES mode of operation CBC MAC Cipher Block Chaining Message Authentication Code AES mode of operation CC Compare Capture CCA Clear Channel Assessment CFB Cipher Feedback AES mode of operation CHF Channel Filter CLK Clock CM3 AR...

Page 1138: ... Crystal Oscillator HW Hardware Hz Hertz IF Intermediate Frequency ISR Interrupt Service Routine LFRCO Low Frequency RC Oscillator LFXO Low Frequency Crystal Oscillator LNA Low Noise Amplifier LO Local Oscillator MOD Modulator MODEM Modulator and Demodulator MSK Minimum Shift Keying NRZ Non Return to Zero NVIC Nested Vector Interrupt Controller OFB Output Feedback Mode AES mode of operation OOK On...

Page 1139: ...dio State Machine RSSI Received Signal Strength Indicator RTC Real Time Counter RX Receive SEQ Radio Sequencer SPI Serial Peripheral Interface SRC Sample Rate Converter STIMER Sequencer Timer SW Software SYNTH Synthesizer TX Transmit WOR Wake On Radio XTAL Crystal Reference Manual Abbreviations silabs com Building a more connected world Rev 1 1 1139 ...

Page 1140: ...mply or express copyright licenses granted hereunder to design or fabricate any integrated circuits The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in signif...

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