The figure below shows the reference plane positions used in the simulations for the EFR32 IC 2G4RF_IOP pin and for the discrete
SMD pins. Since the IC pin covers the whole pad area, the reference plane falls to the geometric center of the PCB pad. With the dis-
crete SMD elements, the reference plane is put at the ends of the SMD soldering pin.
Figure 3.5. Reference Planes with Real SMD Elements
Figure 3.6 Estimation of PCB Layout Parasitics on page 10
shows the Rf part of the top layer of the 5x5 mm packaged EFR single
band design with estimated pcb series parasitic inductor and parallel capacitor values. The series pcb parasitic inductors are calculated
here using the reference plane definitions of
Figure 3.5 Reference Planes with Real SMD Elements on page 10
. The parallel parasitic
cap values are calculated to the whole printed area including the soldering pads. Here, estimation both for the area cap (calculated from
the dielectric thickness down to the grounding layer beneath and from the pad dimensions) and the fringing field caps (to the side
ground metal on the same layer) are required. The gap to the side ground metal are given by the G parameters in the figure. The easi-
est way to make that estimation is to use a grounded coplanar calculator, which computes the unit parallel capacitance and series in-
ductance parasitics as well. Numerous calculators can be found on the internet. An example of this type of calculator is given in Item 3
of
6. References
at the end of this document.
The ladder 2-element matching circuit with PCB parasitics is shown in
Figure 3.7 2-Element Lumped Element Match with Discrete Mod-
els of PCB Layout Parasitics on page 11
. The applied PCB layout is proper for incorporating a ladder four-element match; so, if only
the ladder two-element match is applied, the additional LC section (a series inductor denoted by L1 and a parallel capacitor denoted by
C1 ) is not populated. In this case, a 0 Ω resistor has to be used in the place of the series L1. The parasitic series inductance of this 0 Ω
resistor is ~0.1 nH, which is also included in the figure. The losses of the PCB traces are not taken into account because they are much
smaller compared to the losses of the applied SMD discretes.
Figure 3.6. Estimation of PCB Layout Parasitics
AN930: EFR32 2.4 GHz Matching Guide
2.4 GHz RF Matching Design Steps
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