000-0046140-111
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SLG46140
•
At CPOL=0 the base value of the clock is zero
• For CPHA=0, data are captured on the clock's rising edge (LOW→HIGH transition) and data is propagated on a falling edge.
(HIGH→LOW clock transition).
• For CPHA=1, data are captured on the clock's falling edge and data is propagated on a rising edge.
•
At CPOL=1 the base value of the clock is one (inversion of CPOL=0)
• For CPHA=0, data are captured on clock's falling edge and data is propagated on a rising edge.
• For CPHA=1, data are captured on clock's rising edge and data is propagated on a falling edge.
That is, CPHA=0 means sample on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock
edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle
before the first clock cycle.
The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI
master and slave devices may well sample data at different points in that half cycle.
This adds more flexibility to the communication channel between the master and slave.
17.3 SPI Clock synchronization
When the parallel data is going to be loaded into the buffer in SPI, the SPI will generate the "sync" signal, it will be gating the
ADC/PWM CLOCK or FSM CLOCK/256 to stop the running ADC, PWM, FSM or CNTs to avoid mis-catch data due to the
asynchronization of SCLK and the internal clocks, see
.
Note: The internal clock and SPI clock must satisfy the: 2T
CLK_IN
T < 1/2T
SCK
Figure 75. Timing Diagram showing SPI Clock synchronization
CK_INT
SYNC
sync_pipe
CK_synced
LOAD (in the SPI)
When load to trigger the ADC data,
the data must be frozen
Half of the SCK period
The delay is within 2 CK_INT period
