S I G N U M S Y S T E M S
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Coprocessor Registers
Coprocessor registers are defined for a core rather than a processor. The register description
comes from the cores\<core>.def file which has the same format as the peripheral registers file.
In our iMX31 processor (ARM1136J-S core) example, the register description is taken from the
core\ARM1136J-S.def file. You should avoid modifying this file.
The CP<nr> structure contains the definition of the coprocessor register. For instance, all CP15
registers are members of the $CP15 structure:
(gdb) ptype $CP15
type = struct CP15 {
int32_t ID;
int32_t CACHE_TYPE;
int32_t TCM_STATUS;
int32_t TLB_TYPE;
int32_t CONTROL;
...
}
To display a register value, use the print command.
(gdb) p /x $CP15.CONTROL
$1 = 0xe5287a
A register can be modified using the set var command:
(gdb) set var $CP15.CONTROL=0x51078
Alternatively, coprocessor registers may be accessed using one of the monitor commands. (See
Table 2
on page
5
for a list of available commands.) For instance,
(gdb) monitor mem space 0x1F
(gdb) monitor s32 0x0400 = 0x78
(gdb) monitor d32 0x0400
(gdb) monitor s32 0x0C00 = 0xFFFFFFFF
(gdb) monitor d32 0x0C00
(gdb) monitor mem space default memory
Use the
show convenience
command to display a complete list of processor registers. For
example:
(gdb) show convenience
$CP15 = {ID = 1090949733, CACHE_TYPE = 487661906, TCM_STATUS = 0,
CONTROL = 327800, TTBR = 0, DAC = 4294967295, DFSR = 46, IFSR = 68,
...
DTLB_LOCKDOWN_VICTIM = 0, WB_DRAIN = 1090949733, FCSE_PID = 0,
CONTEXT_ID = 0}
$io = {TC0 = {TC0_CCR = 0, TC0_CMR = 0, TC0_CV = 0, TC0_RA = 0, TC0_RB = 0,
TC0_RC = 0, TC0_SR = 0, TC0_IER = 0, TC0_IDR = 0, TC0_IMR = 0,
TC1_CCR = 0, TC1_CMR = 0, TC1_CV = 0, TC1_RA = 0, TC1_RB = 0, TC1_RC = 0,
TC1_SR = 0, TC1_IER = 0, TC1_IDR = 0, TC1_IMR = 0, TC2_CCR = 0,
TC2_CMR = 0, TC2_CV = 0, TC2_RA = 0, TC2_RB = 0, TC2_RC = 0, TC2_SR = 0,
TC2_IER = 0, TC2_IDR = 0, TC2_IMR = 0, TC3_CCR = 0, TC3_CMR = 0,
...
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