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Rev 1.1
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Communication Interfaces
transmission will cause the device to behave erratically or hang. Information for writing to the
configuration registers is provided in
Configuration Registers. Upon the execution of the register
that was sent, the device will return one (1) byte of data with bit 1 high to indicate success. This byte
must be read by the host to clear its receive buffer so that reading subsequent registers will not contain
corrupted data. Furthermore, reading back this byte will ensure that the device is ready for the next
register command.
Reading from the Device Via RS232
To query information from the device, the query registers are addressed, and data is returned. These are
request for data registers, in that a request for certain data is made by writing to the specific register first,
followed by reading back the requested data. Some registers may require instruction data to specify the
type of data to return, while others do not need any. For example, the GET_RF_PARAMETERS (0x20)
returns sweep dwell time, rf1 frequency, list start frequency, etc.; this depends on the request instruction
byte.
Returned data length is always 8 bytes (64 bits), with the first byte being the most significant (MSB). Not
all 8 bytes are valid, some have 7, some 4, and others 2. It is important that all 8 bytes are read in order to
clear the interface buffers.
contains the query register information. As with the configuration registers, it is
important that all data byte(s) (write) associated with the query registers are sent even if they are null. All
queries will return 8 bytes of data (read) with the first received byte being the most significant (MSB).
Section
4.2 Query Registers
provides the format details of the received data.
PXI
The PXIe interface contains a high-speed PCIe-to-Serial bridge chip. This bridge chip communicates with
the onboard microcontroller serially. The interface on the bridge chip resides at offset addresses between
0x00 and 0xFF from BAR0; which is memory mapped. A kernel level driver for the operating system is
needed to access this memory address. A simple driver using IO controls should be sufficient to read and
write byte data to this block of addresses. Although SignalCore provides the driver and API for these
products, information is provided here for users who may need to write drivers for a different operating
system or a different driver. An example would be writing the API for the Linux operating system.
Setting Up the PCI to Serial Bridge
The serial function of the bridge chip must first be initialized before it can communicate with the onboard
microcontroller, and hence communication between the microcontroller and the PXIe bus. The
initialization can be done at the kernel level mode or at the user level mode, the decision is left to the
user. The following table lists the programming order of the bridge register addresses to initialize and
setup the serial port function.
Step
BAR0 Register
Address
Data (Byte)
1
0x88
0x01
2
0x04
0x00
3
0x03
0x80
