SC5313A Operating & Programming Manual
Rev 1.0.2
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N T E R F A C E
The SPI Architecture
The SPI interface is implemented using 8-bit length physical buffers for both the input and output, hence
they need to be read and cleared before consecutive bytes can be transferred to and from them. In
other words, a time delay is required between consecutive bytes written to or read from the device by
the host. The chip-select pin (
) must be asserted low before data is clocked in or out of the product.
must be asserted for the entire duration of the transfer.
Once a full transfer has been received, the device will proceed to process the command and de-assert
low the SERIAL_READY bit. The status of this bit can be read by the host by invoking the SERIAL_READY
register (0x04). The SERIAL_READY bit can also be monitored on pin 15
of the SPI interface (digital I/O)
connector. While SERIAL_READY is de-asserted low, the device will ignore any incoming commands. It is
only ready when the previous command is fully processed and SERIAL_READY is re-asserted high. It is
important that the host monitors the SERIAL_READY bit and performs transfers only when it is asserted
high to avoid miscommunication. Figure 3 shows the command transfer for obtaining the SERIAL_READY
bit, which is returned in bit 0 of the device MISO line.
Figure 3. Querying the SerialReady bit.
All data transferred to and from the device are clocked on the falling edge of the clock as shown in
Figure 4. Figure 5 shows a 3 byte SPI transfer initiated by the host; the device is always in slave mode.
The CS pin must be asserted low for a minimum period of
before data is clocked in. The clock rate
may be as high as 1.0 MHz, however if the external SPI signals do not have sufficient integrity due to
cabling problems the rate should be lowered. It is recommended that the clock rate not exceed 1.0 MHz
to ensure proper serial operation. As mentioned above, the SPI architecture limits the byte rate because
after every byte transfer, the input and output SPI buffers need to be cleared and loaded respectively by
the device SPI engine. The time required to perform this task is indicated in Figure 5 by
, which is the
time interval between the end of one byte transfer and the beginning of another. The recommended
time delay for
is
or greater. The number of bytes transferred depends on the command. It is
important that the correct number of bytes is transferred for the associated device register because
once the first byte (MSB) containing the device register is received, the device will wait for the desired
number of bytes associated with it. The device will hang if insufficient number of bytes is written and
0x04
CLK
DATA IN
CS
DATA OUT
0x00
Invalid
0x01
