SC5506A Operating & Programming Manual
Rev 2.1.1
30
P
R O G R A M M I N G T H E
S
E R I A L
P
E R I P H E R A L
I
N T E R F A C E
( S P I )
The SPI Architecture
The SPI interface is implemented using 8-bit length physical buffers for both the input and output, hence
they need to be read and cleared before consecutive bytes can be transferred to and from them. In other
words, a time delay is required between consecutive bytes written to or read from the device by the host.
The chip-select pin (
𝐶𝑆
̅̅̅̅
) must be asserted low before data is clocked in or out of the product.
𝐶𝑆
̅̅̅̅
must be
asserted for the entire duration of the transfer.
Once a full transfer has been received, the device will proceed to process the command and de-assert low
the SERIAL_READY bit. The status of this bit can be read by the host by invoking the SERIAL_READY register
(0x04). The SERIAL_READY bit can also be monitored on pin 15 of the SPI interface (digital I/O) connector.
While SERIAL_READY is de-asserted low, the device will ignore any incoming commands. It is only ready
when the previous command is fully processed and SERIAL_READY is re-asserted high. It is important that
the host monitors the SERIAL_READY bit and performs transfers only when it is asserted high to avoid
miscommunication.
All data transferred to and from the device are clocked on the falling edge of the clock by default as shown
in Figure 3. To clock data in and out on the rising edge of the clock, pin 18 of the digital I/0 connector
needs to be grounded. See Table 2 for the connector pin layout. Figure 4 shows a 3 byte SPI transfer
initiated by the host; the device is always in slave mode. The CS pin must be asserted low for a minimum
period of
5 𝜇𝑠
before data is clocked in. The clock rate may be as high as 1.0 MHz, however if the external
SPI signals do not have sufficient integrity due to cabling problems then the rate should be lowered.
SignalCore recommends that the clock rate not exceed 1.0 MHz to ensure proper serial operation. As
mentioned above, the SPI architecture limits the byte rate due to the fact that after every byte transfer
the input and output SPI buffers need to be cleared and loaded respectively by the device SPI engine. The
time required to perform this task is indicated in Figure 4 by
𝑇
𝐵
, which is the time interval between the
end of one byte transfer and the beginning of another. The recommended time delay for
𝑇
𝐵
is
10𝜇𝑠
or
greater. The number of bytes transferred depends on the command. It is important that the correct
number of bytes is transferred for the associated device register, because once the first byte (MSB)
containing the device register is received, the device will wait for the desired number of associated bytes.
The device will hang if an insufficient number of bytes are written to the register. In order to clear the
hung condition, the device will need to be reset externally. The time required to process a command is
also dependent on the command itself. Measured times for command completions are typically between
40 𝜇𝑠
to
150 𝜇𝑠
after reception. The user may choose to wait a minimum of
150 𝜇𝑠
or query the
SERIAL_READY bit before sending in another command. The latter is recommended for robustness.
