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SiFive Core IP FPGA Eval Kit User Guide

v3p0

© SiFive, Inc.

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Summary of Contents for E2* Core IP Series

Page 1: ...SiFive Core IP FPGA Eval Kit User Guide v3p0 SiFive Inc ...

Page 2: ...2 SiFive Core IP FPGA Eval Kit User Guide v3p0 ...

Page 3: ...ion or use of any product or circuit and specifically disclaims any and all liability including without limitation indirect incidental special exemplary or consequential damages SiFive reserves the right to make changes without further notice to any products herein Release Information Version Date Changes v3p0 Feb 28 2019 Updated for 19 02 Core IP Release Supports v19 02 Core IP Package Added desc...

Page 4: ...ii SiFive Core IP FPGA Eval Kit User Guide v3p0 ...

Page 5: ...Evaluation Kit 3 2 2 USB A to Micro B Cable 3 2 3 Olimex ARM USB TINY H Debugger 3 2 4 USB A to B Cable 3 2 5 Male To Female Jumper Cables 10 4 3 Board Setup 5 3 1 Connecting the USB Interface 5 3 2 Connecting the Debugger 5 4 FPGA Flash Programming File 9 4 1 Programming the Arty 35T SPI Flash 9 4 2 Programming the Arty 100T SPI Flash 10 5 Boot and Run 11 5 1 Serial Setup 11 5 1 1 Reset and boot ...

Page 6: ...ng to the Target Board 18 6 6 3 Debugging a Target Program 19 6 6 4 Cleaning a Target Program Build Directory 19 6 6 5 Create a Standalone Project 19 7 E2 Core IP FPGA Eval Kit MCS Image Contents 21 7 1 Core IP FPGA Eval Kit Memory Map 21 7 2 Core IP FPGA Eval Kit Clock and Reset 21 7 3 Core IP FPGA Eval Kit Pinout 21 8 E3 S5 Core IP FPGA Eval Kit MCS Image Contents 25 8 1 Core IP FPGA Eval Kit Me...

Page 7: ...bug Connections To the Olimex ARM USB TINY H 6 3 3 Debug Connections to the Arty Board JD PMOD Header 6 3 4 Photo of the Arty Board showing USB and Debug Connections 7 7 1 E2 Core IP FPGA Eval Kit Block Diagram 22 8 1 E3 S5 Core IP FPGA Eval Kit Block Diagram 26 9 1 E7 S7 Core IP FPGA Eval Kit Block Diagram 30 v ...

Page 8: ...vi SiFive Core IP FPGA Eval Kit User Guide v3p0 ...

Page 9: ...this Release This Eval Kit allows you to prototype and benchmark your target RISC V software without modifying integrating or synthesizing any Verilog code This release is intended for evaluation purposes only 1 3 Evaluation Version Limitations Version v19 02 of the Core IP FPGA Eval Kit has the following limitations compared with the fully functional Core IP DTIM is limited in size to 64kB Periph...

Page 10: ...2 SiFive Core IP FPGA Eval Kit User Guide v3p0 ...

Page 11: ...Note that the Arty kit does not include one http store digilentinc com usb a to micro b cable 2 3 Olimex ARM USB TINY H Debugger The Olimex ARM USB TINY H is a hardware JTAG debugger The Core IP Arty FPGA Dev Kit has a standard JTAG debugging interface and the tools included with the Core IP FPGA Eval Kit have been tested using the Olimex ARM USB TINY H It can be purchased from Olimex or Digi Key ...

Page 12: ...Cables 10 The connection between the Olimex ARM USB TINY H and Core IP FPGA Eval Kit requires 10 connections These can be made with Male to Female jumper cables These cables are available from Adafruit in convenient rip apart ribbon cables https www adafruit com products 826 ...

Page 13: ...PGA image and run the included demo program you cannot change the software which executes Connect the Olimex ARM USB TINY H with the USB Type A to B cable to the host machine Then connect the Olimex ARM USB TINY H debugger to PMOD header JD using the 10 jumper cables The pinout is as shown in Figure 3 1 Note that the Olimex ARM USB TINY H and the PMOD header on the Arty Board have different number...

Page 14: ...ugging Connections between Olimex ARM USB TINY H and Arty Board s PMOD header JD 1 VREF red 2 VREF brown 3 nTRST orange 4 5 TDI yellow 6 7 TMS green 8 NOTCH 9 TCK blue 10 NOTCH 11 12 13 TDO purple 14 GND black 15 nRST grey 16 GND white 17 18 19 20 LED Figure 3 2 Debug Connections To the Olimex ARM USB TINY H square pad 1 TDO purple 7 TDI yellow 2 nTRST orange 8 TMS green 3 TCK blue 9 nRST grey 4 1...

Page 15: ...Copyright 2016 2019 SiFive Inc All rights reserved 7 Figure 3 4 Photo of the Arty Board showing USB and Debug Connections ...

Page 16: ...8 SiFive Core IP FPGA Eval Kit User Guide v3p0 ...

Page 17: ...ab Edition and WebPACK Edition 2018 2 support Artix 7 devices free of charge 4 1 Programming the Arty 35T SPI Flash To program the Arty 35T SPI Flash with Vivado take the following steps 1 Launch Vivado 2 Open Hardware Manager 3 Open target board 4 Right click on the FPGA device and select Add Configuration Memory Device 5 Select the following SPI flash parameters Part m25ql128 Manufacturer Micron...

Page 18: ...vado 2 Open Hardware Manager 3 Open target board 4 Right click on the FPGA device and select Add Configuration Memory Device 5 Select the following SPI flash parameters Part s25fl128sxxxxxx0 Manufacturer Spansion Alias s25fl127s Family s25flxxxs Type spi Density 128 Width x1 x2 x4 6 Click OK to Do you want to program the configuration memory device now 7 Add the MCS file 8 Select OK 9 Once the pro...

Page 19: ... k to kill exit the running screen session Depending on your setup you may need additional drivers or permissions to communicate over the USB port If you are running on Ubuntu style Linux the below is an example of steps you may need to follow to access your dev kit without sudo permissions 1 With your board s debug interface connected make sure your device shows up with the lsusb command lsusb Bu...

Page 20: ...rial device belonging to the plugdev group ls dev ttyUSB dev ttyUSB0 dev ttyUSB1 dev tty USB2 dev tty USB3 If you have other serial devices or multiple boards attached you may have more devices listed For serial communication with the UART you will always want to select the higher number of the pair in this example dev ttyUSB2 ls l dev ttyUSB2 crw rw r 1 root plugdev 188 1 Nov 28 00 00 dev ttyUSB1...

Page 21: ...a program 5 2 Default Demo Program For Core IP the MCS file includes a simple demo program This program is loaded to the SPI Flash along with the FPGA image With Switch 0 set to the Off position towards the edge of the board on reset the Core will execute a simple demo program This program prints a message over the UART and uses the PWM peripheral to change RGB LED 1 This program will be overwritt...

Page 22: ...14 SiFive Core IP FPGA Eval Kit User Guide v3p0 55555 5 BUILD TIME Feb 28 2019 00 00 00 Welcome to the E21 Core IP FPGA Evaluation Kit ...

Page 23: ...rivers are automatically installed you do not need to download or install it seperately to get tools and example code You can obtain Freedom Studio from the SiFive website https www sifive com boards More information on how to use it can be found in the Freedom Studio Manual https www sifive com documentation tools freedom studio manual 6 3 Software Development Using Freedom E SDK Command Line Too...

Page 24: ... location Then use the RISCV PATH and RISCV OPENOCD PATH variables when using the tools For example cp openocd date platform tar gz my desired location cp riscv64 unknown elf gcc date platform tar gz my desired location cd my desired location tar xvf openocd date platform tar gz tar xvf riscv64 unknown elf gcc date platform tar gz export RISCV_OPENOCD_PATH my desired location openocd export RISCV_...

Page 25: ...llowing design dts The DeviceTree description of the target This file is used to parameterize the Freedom Metal library to the target device It is included as reference so that users of Freedom Metal are aware of what features and peripherals are available on the target metal h The Freedom Metal machine header which is used internally to Freedom Metal to instantiate structures to support the targe...

Page 26: ...ler for and trigger a software interrupt timer interrupt Demonstrates how to register a handler for and trigger a timer interrupt local interrupt Demonstrates how to register a handler for and trigger a local interrupt example pmp Demonstrates how to configure a Physical Memory Protection PMP region 6 6 Using the Freedom E SDK 6 6 1 Building an Example To compile a bare metal RISC V program make B...

Page 27: ...t You can export a program to a standalone project directory using the standalone target The resulting project will be locked to a specific TARGET STANDALONE DEST is a required argument to provide the desired project location make standalone BSP metal PROGRAM hello TARGET coreip s51 arty STANDALONE_DEST path to desired location Once the standalone project is created it can be compiled simply by ty...

Page 28: ...20 SiFive Core IP FPGA Eval Kit User Guide v3p0 ...

Page 29: ... 65 MHz and the clock peripheral clock at 32 5 MHz The io rtcToggle is driven at approximately 32 kHz The system reset driven by the Reset Button on the evaluation board is combined with the external debugger s SRST n pin as a full system reset for the Core IP FPGA Eval Kit This is combined with the io ndreset to drive the reset input to the Core IP The reset vector is set with Switch 0 Leave the ...

Page 30: ...22 SiFive Core IP FPGA Eval Kit User Guide v3p0 Figure 7 1 E2 Core IP FPGA Eval Kit Block Diagram ...

Page 31: ... GPIO GPIO 0 LED 0 RED 7 GPIO 1 LED 0 GREEN 8 GPIO 2 LED 0 BLUE 9 GPIO 3 SWITCH 3 10 GPIO 4 BUTTON 0 11 GPIO 5 BUTTON 1 12 GPIO 6 BUTTON 2 13 GPIO 7 BUTTON 3 14 GPIO 8 PMOD A 0 15 GPIO 9 PMOD A 1 16 GPIO 10 PMOD A 2 17 GPIO 11 PMOD A 3 18 GPIO 12 PMOD A 4 19 GPIO 13 PMOD A 5 20 GPIO 14 PMOD A 6 21 GPIO 15 PMOD A 7 22 PWM Counter PWM CMP 0 23 PWM CMP 1 LED 1 RED 24 PWM CMP 2 LED 1 GREEN 25 PWM CMP ...

Page 32: ...Local Interrupts Mapping Hardware Input Local Interrupt Number Index in mip mie registers Switch 0 16 Switch 1 17 Switch 2 18 Switch 3 19 Button 0 20 Button 1 21 Button 2 22 Button 3 23 PMOD A 0 24 PMOD A 1 25 PMOD A 2 26 PMOD A 3 27 PMOD A 4 28 PMOD A 5 29 PMOD A 6 30 PMOD A 7 31 ...

Page 33: ...k at 65 MHz and the clock peripheral clock at 32 5 MHz The io rtcToggle is driven at approximately 32 kHz The system reset driven by the Reset Button on the evaluation board is combined with the external debugger s SRST n pin as a full system reset for the Core IP FPGA Eval Kit This is combined with the io ndreset to drive the reset input to the Core IP The reset vector is set with Switch 0 Leave ...

Page 34: ...26 SiFive Core IP FPGA Eval Kit User Guide v3p0 Figure 8 1 E3 S5 Core IP FPGA Eval Kit Block Diagram ...

Page 35: ... GPIO GPIO 0 LED 0 RED 7 GPIO 1 LED 0 GREEN 8 GPIO 2 LED 0 BLUE 9 GPIO 3 SWITCH 3 10 GPIO 4 BUTTON 0 11 GPIO 5 BUTTON 1 12 GPIO 6 BUTTON 2 13 GPIO 7 BUTTON 3 14 GPIO 8 PMOD A 0 15 GPIO 9 PMOD A 1 16 GPIO 10 PMOD A 2 17 GPIO 11 PMOD A 3 18 GPIO 12 PMOD A 4 19 GPIO 13 PMOD A 5 20 GPIO 14 PMOD A 6 21 GPIO 15 PMOD A 7 22 PWM Counter PWM CMP 0 23 PWM CMP 1 LED 1 RED 24 PWM CMP 2 LED 1 GREEN 25 PWM CMP ...

Page 36: ...Local Interrupts Mapping Hardware Input Local Interrupt Number Index in mip mie registers Switch 0 16 Switch 1 17 Switch 2 18 Switch 3 19 Button 0 20 Button 1 21 Button 2 22 Button 3 23 PMOD A 0 24 PMOD A 1 25 PMOD A 2 26 PMOD A 3 27 PMOD A 4 28 PMOD A 5 29 PMOD A 6 30 PMOD A 7 31 ...

Page 37: ...sed to derive the Core IP s io coreClock at 32 5 MHz and the clock peripheral clock at 32 5 MHz The io rtcToggle is driven at approximately 32 kHz The system reset driven by the Reset Button on the evaluation board is combined with the external debugger s SRST n pin as a full system reset for the Core IP FPGA Eval KitT his is combined with the io ndreset to drive the reset input to the Core IP 9 3...

Page 38: ...30 SiFive Core IP FPGA Eval Kit User Guide v3p0 Figure 9 1 E7 S7 Core IP FPGA Eval Kit Block Diagram ...

Page 39: ... GPIO GPIO 0 LED 0 RED 7 GPIO 1 LED 0 GREEN 8 GPIO 2 LED 0 BLUE 9 GPIO 3 SWITCH 3 10 GPIO 4 BUTTON 0 11 GPIO 5 BUTTON 1 12 GPIO 6 BUTTON 2 13 GPIO 7 BUTTON 3 14 GPIO 8 PMOD A 0 15 GPIO 9 PMOD A 1 16 GPIO 10 PMOD A 2 17 GPIO 11 PMOD A 3 18 GPIO 12 PMOD A 4 19 GPIO 13 PMOD A 5 20 GPIO 14 PMOD A 6 21 GPIO 15 PMOD A 7 22 PWM Counter PWM CMP 0 23 PWM CMP 1 LED 1 RED 24 PWM CMP 2 LED 1 GREEN 25 PWM CMP ...

Page 40: ...Local Interrupts Mapping Hardware Input Local Interrupt Number Index in mip mie registers Switch 0 16 Switch 1 17 Switch 2 18 Switch 3 19 Button 0 20 Button 1 21 Button 2 22 Button 3 23 PMOD A 0 24 PMOD A 1 25 PMOD A 2 26 PMOD A 3 27 PMOD A 4 28 PMOD A 5 29 PMOD A 6 30 PMOD A 7 31 ...

Page 41: ...t version of this guide and supporting files can be found at https www sifive com More information about RISC V in general is available at http riscv org SiFive thoughts ideas and news at https www sifive com blog Webinars at https info sifive com risc v webinar 33 ...

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