Hardware interfaces
Version 8 dated 15.03.00
23
Siemens Information and Communication Products
Note
: data clock (VSCLK_C, VSCKL_V): 104 kHz, word length: 13 bits, synchronisation pulse rate (VSFS_C,
VSFS_V): 8 kHz.
For detailed information on timing characteristics, see
Timing characteristics of DAI to microcontroller
.The corresponding timing values can be found in
Fig. 4-4
Timing characteristics of DAI to microcontroller
Fig. 4-5
Timing characteristics of DAI to codec
VSFS_V
Synchronisation
O
2.8V
to codec
VSCLK_V
Clock
O
2.8V
to codec
VSDO_V
Data output
O
2.8V
to codec
VSDI_V
Data Input
I
2.8V
to codec
Parameter
Comment
Min.
Typ.
Max.
Units
t
43
VSDI setup time before VSCLK low
25
ns
t
44
VSDI hold time after VSCLK low
10
ns
t
47
VSFS delay from VSCLK high
25
ns
t
48
VSFS hold time after VSCLK high
-20
ns
t
49
VSDO hold time after VSCLK high
-20
ns
t
50
VSDO delay from VSCLK high
20
ns
t
90
VSCLK period
9615
ns
t
91
VSFS setup time before VSCLK low
4
ns
t
92
VSFS hold time after VSCLK low
7
ns
t
93
VSDI setup time before VSCLK low
4
ns
VSCLK (I)
VSDI (I)
VSDO (O)
t
90
D15 D14
VSFS (I)
t
91
t
92
t
93
t
94
t
95
D15 D14 D13
VSDI (I)
VSDO (O)
VSCLK (O)
VSFS (O)
t
43
t
44
t
47
t
48
t
50
D15 D14 D4 D3 D15
t
49
D15 D14 D4 D3 D15