Siemens KNX EIB TP-UART 2-IC Manual Download Page 7

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GAMMA

instabus

Release: February 2012

KNX EIB TP-UART 2-IC

Siemens AG

pages 42

Technical Manual

Infrastructure and Cities Sector,
Building Technologies
Control Products and Systems

page 7

P. O. Box 10 09 53,

Subject to change without further notice.

D-93009 Regensburg

6 VDDH

AIO

VSP

VB-

SMPS control

7 SVCC

AIO

VCC

VB-

VCC control

8 VCC

AIO

5.5V Clamp

to VB-

VB-

External power supply 3.3/5 V

9 IND

AIO

VSP

VB-

SMPS-output; no external freewheeling
diode

10 VB-

Ground

Negative bus pin, exposed pad (see Figure
5 and 7.2 Layout Guidelines)

11 VB+

70V Clamp to

VB-

Positive bus pin

12 BYP

AIO

VB+

VB-

Bypass current stabilisation pin

13 TXO

AIO

VB+

VB-

Transmit output current (bus signal)

14 STxO

AIO

VB+

VB-

Transmitting active indication

15 RxIN

AIO

VB+

VB-

Capacitive coupled to bus signal

16 VB-

Ground

Negative bus
pin

17 VIF

5.5V Clamp

to VB-

VB-

External supply for IO cells

18 SAVE

DO_PU

VIF

VB-

Signalization of bus voltage break-down

19 RESn

DIO_PU

VIF

VB-

Reset pin, open drain with internal pullup

20 RxD

DI_PD

VIF

VB-

Data receive from host with internal
pulldown

21 TxD

VIF

VB-

Data transmission to host

TSTOUT_TW

VIF

VB-

Digital test / temperature signal

23 X1

VIF

VB-

Crystal oscillator pin 1; external clock input

24 X2

VIF

VB-

Crystal oscillator pin 2

25 V20PD

VDP

VB-

Enable and disable V20

26 NC2

DIO

VDP

VB-

Used during chip test mode

27 NC3

AIO

VDP

28 VDP

AIO

5.5V Clamp

to VB-

VB-

Storage capacitor for internal power supply

29 TSTIN_BDS

DIO

VDP

VB-

Input for digital test / baud rate select;
digital output for analog test

30 DIV

VDP

VB-

Internal clock divider 2:1 active

31 CTM_AMS

VDP

VB-

Chip Test mode control

32 MODE 3

VDP

VB-

Chip Test Mode control pin 4

33 MODE 2

VDP

VB-

Chip Test Mode / Mode control pin 3

34 MODE 1

VDP

VB-

Mode control pin 2

35 MODE 0

VDP

VB-

Mode control pin 1

36 TESTMODE

VDP

VB-

Test mode control

Table 2: Pin Description

PIN Types:

...

supply pad

AIO

...

analog I/O

… digital input

DI_PU

...

digital input with pull up

Summary of Contents for KNX EIB TP-UART 2-IC

Page 1: ...ower supply 20V 25mA with limiting function IV20max adjustable in steps IVB max overshoot due to load changes actively limited Operating temperature range 25 C to 85 C Small QFN36X36 package GENERAL DESCRIPTION The TP UART IC Twisted Pair Universal Asynchronous Receive Transmit IC is a transceiver which supports the connection of microcontrollers of sensors actuators or other applications to the E...

Page 2: ...upply 30V TP UART IC A Bus B Bus Bus Device 1 Bus Device 2 Bus Device n Optional Power Supply 230V 50Hz Optional Electrical Isolation Optocoupler TxD RxD TxD RxD TxD RxD TP UART IC TP UART IC Application Application Application STRUCTURE OF TP UART 2 IC Block Diagram Filter 1 Byte Receviebuffer KNX Receiver UART Transmitter 64 Byte Sendbuffer KNX Transmitter RxD TxD RxD3 TxD3 RESn Physical Address...

Page 3: ...nd VB 10 2 2 4 CCS stabilisation Pin BYP 10 2 2 5 Buffer Voltage Pin VSP 10 2 2 6 Supply Pin VCC 11 2 2 7 Supply Pin VDP 12 2 2 8 Supply Pins VDDH and VSSH 12 2 2 9 Supply Pin V20 and Pin R20 13 2 2 10 Pin IND SMPS output 14 2 2 11 Pin SVCC 14 2 2 12 Receive Pin RxIN 14 2 2 13 Transmit Pin TxO 15 2 2 14 Supply Pin VIF 15 2 2 15 Oscillator Pins X1 and X2 15 2 2 16 Interface Pin RxD 15 2 2 17 Interf...

Page 4: ...ologies page 4 Siemens AG 2012 Control Products and Systems Subject to change without further notice P O Box 10 09 53 D 93009 Regensburg 4 1 PACKAGE 34 5 TAPE AND REEL PACKING 37 6 SOLDERING PROFILE 38 7 APPENDIX 39 7 1 TYPICAL APPLICATION CIRCUITS 39 7 1 1 Mode of Operation Normal 39 7 1 2 Mode of Operation Analog 40 7 2 LAYOUT GUIDELINES 40 ...

Page 5: ...r notice D 93009 Regensburg 1 Modes of Operation 1 1 Interface to host electronics TxD RxD Normal Mode Bus Coupler Mode IDLE HIGH IDLE HIGH IDLE LOW EIB TP UART IC Analog Part Digital Part TxD3 RxD3 IDLE LOW HOST Controller 1 2 Selection of Different Modes of Operation Mode of operation MODE TEST MODE CTM TSTIN_BDS TSTOUT_TW 0 1 2 3 Normal 1 1 0 0 0 0 BDS 0 19 2 kBd at UART BDS 1 9 6 KBd at UART T...

Page 6: ...24 TSTOUT_TW 23 TxD 22 21 20 RxIN 19 VSP 10 11 IND 12 13 BYP 14 VB 15 TxO 16 VDP 34 33 32 31 30 29 28 STxO 8 9 17 18 26 27 35 36 TSTIN_BDS TESTMODE MODE 0 MODE 1 MODE 2 MODE 3 CTM DIV X2 V20PD NC2 NC3 VB VIF SAVE RxD RESn VB Figure 1 Package Pin Assignment 2 1 2 PIN DESCRIPTION Pin Pin Name Pin Type Positive supply Negative supply Notes 1 NC0 AIO VB VB Used during chip test mode 2 R20 AIO VDP VB E...

Page 7: ... DO_PU VIF VB Signalization of bus voltage break down 19 RESn DIO_PU VIF VB Reset pin open drain with internal pullup 20 RxD DI_PD VIF VB Data receive from host with internal pulldown 21 TxD DO VIF VB Data transmission to host 22 TSTOUT_TW DO VIF VB Digital test temperature signal 23 X1 DI VIF VB Crystal oscillator pin 1 external clock input 24 X2 DO VIF VB Crystal oscillator pin 2 25 V20PD DI VDP...

Page 8: ...Tjnc1 Junction temperature 125 ºC fclk clock frequency external quartz 4 9152 MHz 3 1 DC voltage of bus is 20V to 30V with signal and compensation pulse 11 V 45 V 2 set by SVCC 3 4 915MHz external clock running Table 3 General operating conditions 2 2 2 ABSOLUTE MAXIMUM RATINGS NON OPERATING Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These ...

Page 9: ...l resistance of QFN package to ambient Rtha 28 K W 6 thermal resistance of QFN package to package surface measured on exposed paddle Rths 5 K W 6 Total power dissipation at Tamb 85 ο C all supplies and outputs Pt 1 4 W TW not active 7 Humidity non condensing HNC 5 93 8 Table 4 Absolute maximum ratings Notes 1 during surge impulse 20 V for 2 sec and 65 V for 150 sec 2 In particular allowed voltage ...

Page 10: ...V for 150 µs 2 no load at all VCC V20 I O pins 3 4 915MHz external clock running 4 SVCC connected to VCC nominal VCC 5V 5 SVCC connected to VB nominal VCC 3 3V Table 5 Bus Pins VB and VB 2 2 4 CCS stabilisation Pin BYP The BYP pin drives the control node of the controlled current source CCS via a capacitor connected to the VB bus line This drive is used to ensure that the capacitive loading on the...

Page 11: ...ust be larger than the capacitor at VCC 6 It is highly recommended but not mandatory that an additional capacitor CVDDH is included in any application configuration where capacitors CVSP is present When present it is recommended that CVDDH be placed as close as possible to pin VDDH Table 7 Buffer Voltage Pin VSP Figure 2 VCC supply external connections 2 2 6 Supply Pin VCC Pin VCC delivers the int...

Page 12: ... generated supply voltage to internal loads only The supply is generated by a series regulator Internal input voltage for VDP is VDDH Supply VDP is the positive supply for the mode control pins and DIV and TSTIN_BDS pins Symbol Parameter Min Max Unit Note VIN input voltage 4 75 VVSP V VVDP Internal supply voltage 3 0 3 6 V CVDP external storage capacitance 176 264 nF 1 IVDP external load at VDP 0 ...

Page 13: ...ulator The pin should not be used to dynamically control the state of the V20 regulator when the device is powered up The CV20 capacitor can be removed from the application when V20PD is active hard wired to VDP The IV characteristic of the regulated voltage should not cross the resistive load line defined by RLL VV20 min IV20 Symbol Parameter Min Max Unit Note VV20 supply voltage when current lim...

Page 14: ...e node is clamped to VB The voltages and currents depend on the switched mode power supply concept 2 2 11 Pin SVCC This input pin controls the value of VCC It is possible to switch between 3 3 V and 5 V If pin SVCC is connected to VB VCC voltage is 3 3 V If pin SVCC is connected to VCC VCC voltage is 5 V In any case it is necessary to connect SVCC to a defined level 2 2 12 Receive Pin RxIN The Rec...

Page 15: ...llator Pins X1 and X2 are used for directly connecting a crystal of 4 9152 MHz without additional external capacitors The tolerance of the oscillator is set by the parameters of the external crystal and is expected to be 0 05 It is possible to drive the ASIC by an external clock by forcing the X1 with the external clock pin X2 must be open In Analog Mode no external XTAL is needed and the XTAL osc...

Page 16: ...ternal pull up resistance It is driven to provide a high output level during transmission In all modes where the digital part is active an internal signal generated by the digital part and used to control the switching of STxO It switches from LOW to HIGH before typ 500 µs the first transmit signal In all modes where the digital part is not active Table 19 Switching Pin STxO applies The control fo...

Page 17: ...tput low voltage 0 2 V 2 tf fall time 90 10 for VIF 5 25V 100 ns CL 150 pF 3 1 switching level approx VIF 2 i e VIF 2 Vhyst 2 2 IOL of 1mA when VIF 1V IOL of 5mA when VIF 3V 3 Rise time determined by RPullUp CL and VIF Table 20 Reset Pin RESn 2 2 20 Mode Control Pins MODE0 MODE1 MODE2 MODE3 TESTMODE and CTM These input pins are used to control the mode of the ASIC by connecting them to VB 0 or VDP...

Page 18: ...n typ 1 5 ms save condition this pin delivers an active LOW signal to external host electronic Symbol Parameter Min Max Unit Note RPullUp Value of internal pull up resistor to VIF 10 25 kΩ Vmax maximum voltage at SAVE pin VIF 0 5 V VOL output low voltage 0 2 V 1 tFRG2 Delay from VB break down to SAVE LOW debounce time of internal signal FRG2 0 7 3 ms Typ 1 5 ms tf fall time 90 10 100 ns CL 150 pF ...

Page 19: ...and stacks can be used without modification In addition TP UART 2 supports some additional useful services These services reduce the necessary performance in the microcontroller 3 1 Relationship to ISO Reference Model Host Contoller UART Digital Part UART Analog Part Link Layer Physical Layer Media Access Control Logical Link Control Network Layer Transport Layer Applikation Layer ISO Layer EIB UA...

Page 20: ...ing voltage the TP UART IC generates an active reset level 0 V at pin RESn This is valid for all modes If Normal Mode is activated the following will happen at the UART interface TxD will be 0 as long as there was no bus signal on the EIB for 40 Tbit 1 Tbit 1 9600 s Attention The bittime of RxD TxD depends on the adjusted baud rate at the UART interface for example 1 Tbit or 0 5 Tbit This results ...

Page 21: ... Addressed 0 0 1 0 0 0 0 0 U_ProductID request 20 0 0 1 0 0 0 0 1 U_ActivateBusyMode 21 0 0 1 0 0 0 1 0 U_ResetBusyMode 22 0 0 1 0 0 1 0 0 U_MxRstCnt 24 0 0 1 0 0 1 0 1 U_ActivateCRC 25 0 0 1 0 1 0 0 0 U_SetAddress 28 1 0 0 0 0 0 0 0 U_L_DataStart 80 1 0 i i i i i i U_L_DataContinue 81 BE i Index 1 62 0 1 l l l l l l U_L_DataEnd 47 7F l length 7 63 1 1 1 0 s s s s U_PollingState E0 EE s Slotnumber...

Page 22: ...6 U_ActivateBusmon 3 2 3 1 4 U_ProductID request Requests the internal TP UART IC product identifier The TP UART IC answers with the U_ProductID response service UART Controlfield 20hex 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 0 Fig 7 U_ProductID request 3 2 3 1 5 U_ActivateBusyMode If the host controller is temporarily not able to receive telegrams from the bus e g due to no code execution during flash eras...

Page 23: ...eption of the complete U_SetAddress service and when no Layer 2 frame is currently received from the EIB If the address is set a complete address evaluation in the TP UART is activated group addressed telegrams are now generally confirmed Note The TP UART does not evaluate the received EIB telegrams which were sent itself After reset the address evaluation is deactivated again UART Controlfield 28...

Page 24: ...error occurs parity or checksum error then it generates an INACK Note Also during activated address evaluation the host is able to manipulate the IACK generation of the TP UART by sending the U_AckInformation service 3 2 3 1 8 U_AckInformation Service The U_AckInformation Service is only sent to the TP UART if a host controller wants to check the destination address itself This service is sent by ...

Page 25: ...s s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 5 6 7 p s Addresstype TPCI Checksum Send to Controller p s s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 5 6 7 p s Ack Information Rec from Controller s 0 1 2 3 4 5 6 7 p s Send to Bus s 0 1 2 3 4 5 6 7 p s Time for Addresssearch 17 Bit 1 Bit Buffertime 1 Bit Buffertime Fig 12 Timing for send U_AckInfo e g 96...

Page 26: ...Data Services The U_L_Data Services are used to transfer the complete EIB Linklayer Frame L_Data request and L_PollData request to the TP UART If the host sends a second frame the first frame buffer is yet active the TP UART rejects this and reports it with a Status indication PE bit set immediate Ack 1 Databyte U_LDATA_Start TP UART U_LDATA_End U_LDATA_Cont 2 U_LDATA_Cont 1 Chksum 2 Databyte 1 Da...

Page 27: ...nal data the EIB Control byte is transmitted which is the control field of the L_Data frame or L_Polldata frame If the repetition flag in the control byte is just cleared the TP UART transmits the frame only once time with repetition flag set UART Controlfield 80hex Additional Information 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 F F R 1 c c 0 0 L Data Data Index 00 Start EIB Controlfield Fi...

Page 28: ... 1 9 3 U_L_DataEnd Service The U_L_DataEnd Service marks the end of the transmission of the EIB Frame After receiving this service the TP UART checks the checksum and if correct the transmission starts on the EIB else the UART returns a state indication with Receive Errorflag is set UART Controlfield 80hex Additional Information 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 l l l l l l c c c c c c c c L Dat...

Page 29: ... 0 0 0 1 0 0 1 0 1 Fig 21 U_ActivateCRC 3 2 3 1 9 6 U_PollingState This service must be send to the TP UART if an Pollingframe Ctrlbyte is received If the TP UART detects a collision during sending the slave slot to the EIB the TP UART generates a State indication with the Slave Collisionflag set UART Controlfield Polling Address high 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 0 s s s s c c c c c c c c...

Page 30: ...oller s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 5 6 7 p s s PollAddr Slotcount Checksum Fillbyte for Slot0 Send to Bus s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 PollAddr Slotcount Checksum Slot 0 Slot 1 Receive from Bus s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 5 6 7 p s s 0 1 2 3 4 PollAddr P...

Page 31: ...ated Fig 25 Control Field 3 2 3 1 10 Layer 2 Services The Layer 2 Services includes all standard EIB Linklayer Services The Controlfields are followed by the data of the EIB Frame All bytes received on the EIB are immediately sent to the host The host either has to detect an end of packet timeout by supervising the EOP gap of 2 2 5 ms or check the end of frame by calculating the CCITT CRC must be ...

Page 32: ...bit and the low byte is sent immediately afterwards IACK Receive from bus s 0 1 2 3 4 5 6 7 P S s 0 1 2 3 4 5 6 7 P S s 0 1 2 3 4 5 6 7 P S _ _ _ _ _ _ _ _ _ _ _ Send to Controller Data Checks CRC HB CRC LB confirm TPUART TXD 19200 Data Checksum Fig 27 Timing for CRC 16 bit 3 2 3 1 11 Acknowledge Services Acknowledge services are only transmitted to the host in busmonitormode Note In busmonitormod...

Page 33: ...vice is sent if an U_State request Service was received from the host If the TP UART is too hot over temperature the TW bit has the value 1 In case of Slave Collision Receive Error Checksum Error or Protocol Error or Recognition Over Temperature or Recognition Leaving Over Temperature the TP UART sends a State indication Service TP UART Controlfield 7 6 5 4 3 2 1 0 SC RE TE PE TW 1 1 1 Fig 31 TP U...

Page 34: ...nd Cities Sector Building Technologies page 34 Siemens AG 2012 Control Products and Systems Subject to change without further notice P O Box 10 09 53 D 93009 Regensburg 4 Mechanical Specification 4 1 Package Package type Punched QFN36 6x6x0 9mm Figure 4 Package outline Punched QFN 6x6x0 9mm 36LD 0 5mm Lead Pitch ...

Page 35: ...chnical Manual Infrastructure and Cities Sector Building Technologies Control Products and Systems Siemens AG 2012 page 35 P O Box 10 09 53 Subject to change without further notice D 93009 Regensburg Figure 5 Package dimensions Punched QFN 6x6x0 9mm 36LD 0 5mm Lead Pitch Variant C ...

Page 36: ...al pages 42 Siemens AG Infrastructure and Cities Sector Building Technologies page 36 Siemens AG 2012 Control Products and Systems Subject to change without further notice P O Box 10 09 53 D 93009 Regensburg Figure 6 Package notes Punched QFN 6x6x0 9mm 36LD 0 5mm Lead Pitch ...

Page 37: ...cal Manual Infrastructure and Cities Sector Building Technologies Control Products and Systems Siemens AG 2012 page 37 P O Box 10 09 53 Subject to change without further notice D 93009 Regensburg 5 Tape and Reel Packing Figure 7 Tape and Reel Packing 1 Figure 8 Tape and Reel Packing 2 ...

Page 38: ...perature min 150 C Preheat Soak Tsmax Temperature max 200 C Preheat Soak tS Time 60 120 s Tsmin to Tsmax TL to TP Ramp up rate TL to TP 3 C s TL Liquidous Temperature 217 C tL Time tL maintained above TL 60 150 s TP Peak package body temperature 260 C tP Time tP within 5 C of the specified classification temperature TC see Figure 5 1 30 s TP to TL Ramp down rate TP to TL 6 C s t25 to tP Time 25 C ...

Page 39: ...ue of VCC 5V is used 7 1 1 Mode of Operation Normal V20 C7 22u 35V U2 SMAJ43CA D1 BYG21M A B C3 10u C4 330u 35V R1 68 1W RESn VCC GND TxD RxD C5 10n C6 10n SAVE L1 220uH 1 2 TW C8 220n C9 220n 1 NC0 1 R20 2 V20 3 VDDH 4 VSSH 5 SVCC 6 VCC 7 25 X2 24 X1 23 TSTOUT_TW 22 21 20 RxIN 19 VSP 10 11 IND 12 13 VB 14 VB 15 TxO 16 VDP 34 33 32 31 30 29 28 STxO 8 9 17 18 26 27 35 36 TSTIN_BDS TESTMODE MODE0 MO...

Page 40: ...11 IND 12 13 VB 14 VB 15 TxO 16 VDP 34 33 32 31 30 29 28 STxO 17 18 35 36 TSTIN _ BDS TESTMODE MODE 0 MODE 1 MODE 2 MODE 3 CTM DIV NC3 1 C1 47n 50V VIF VB CBYP 47n 50V BYP 2 recommended close to Pins VDDH and VCC 3 The maximum average power dissipation of the transmitting resistance R1 of 1 W is valid for an active telegram rate of 50 Figure 11 Mode of Operation Analog 7 2 Layout Guidelines The gu...

Page 41: ...D 93009 Regensburg 5 C3 As close as possible to VCC and GND 3 6 CBYP As close as possible to BYP and VB 2 7 C6 As close as possible to VSP and GND 2 8 Y1 As close as possible to X1 and X2 Embed Y1 crystal and its connections on the component side in GND Place on next layer below Y1 a GND area 1 9 TP UART 2 Ground plane on component side and below TP UART 2 has to be designed Four vias are necessar...

Page 42: ...l Manual pages 42 Siemens AG Infrastructure and Cities Sector Building Technologies page 42 Siemens AG 2012 Control Products and Systems Subject to change without further notice P O Box 10 09 53 D 93009 Regensburg Figure 13 Layout Topview Figure 14 Layout Bottom View ...

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