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Siemens C16 Series, Instruction Set Manual

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Siemens C16 Series Instruction Set Manual Download Page 64

30Mar98@15:00h

Semiconductor Group

64

Version 1.2, 12.97

C166 Family Instruction Set

Instruction Description

DIVL

32-by-16 Signed Division

DIVL

Syntax

DIVL op1

Operation

(MDL) 

←

 (MD) / (op1)

(MDH) 

←

 (MD) mod (op1)

Data Types

WORD, DOUBLEWORD

Description

Performs an extended signed 32-bit by 16-bit division of the two words 
stored in the MD register by the source word operand op1. The signed 
quotient is then stored in the low order word of the MD register (MDL) and 
the remainder is stored in the high order word of the MD register ( MDH).   

E Always cleared.

Z Set if result equals zero. Cleared otherwise.

V Set if an arithmetic overflow occurred, ie. the result cannot be repre-

sented in a word data type, or if the divisor (op1) was zero. Cleared 
otherwise.

C Always cleared.

N Set if the most significant bit of the result is set. Cleared otherwise.

Addressing Modes

Mnemonic

Format

Bytes

DIVL

Rw

n

6B nn

2

Condition Flags

E

Z

V

C

N

0

*

S

0

*

Summary of Contents for C16 Series

Page 1: ...Instruction Set Manual Version 1 2 12 97 Instruction Set Manual for the C16x Family of Siemens 16 Bit CMOS Single Chip Microcontrollers h t t p w w w s i e m e n s d e S e m i c o n d u c t o r ...

Page 2: ... Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the costs of transport For packing material that is returned to us un sorted or which we are not obliged to accept we shall have to invoice you for any costs in curred Components used in life support ...

Page 3: ...tax corrected 75 JBC Condition flags corrected 77 JMPI operation corrected 81 JNBS Condition flags corrected 86 87 MUL U Flag N corrected 95 PRIOR Operation corrected 104 SCXT Data Type added 108 SRVWDT Syntax corrected We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of t...

Page 4: ...s Table of Contents Page Semiconductor Group 4 Version 1 2 12 97 1 Introduction 5 2 Short Instruction Summary 6 3 Instruction Set Summary 9 4 Instruction Opcodes 21 5 Instruction Description 26 6 Addressing Modes 116 7 Instruction State Times 123 ...

Page 5: ... according to different criteria and also unloads the technical manuals for the different devices from redundant information This manual also describes the different addressing mechanisms and the relation between the logical addresses used in a program and the resulting physical addresses There is also information provided to calculate the execution time for specific instructions depending on the ...

Page 6: ...ngth depending on the selected addressing mode This reference helps to optimize instruction sequences in terms of code size and or execution time 0x 1x 2x 3x 4x 5x 6x 7x x0 ADD ADDC SUB SUBC CMP XOR AND OR x1 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x2 ADD ADDC SUB SUBC CMP XOR AND OR x3 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x4 ADD ADDC SUB SUBC XOR AND OR x5 ADDB ADDCB SUBB SUBCB XORB ANDB ORB...

Page 7: ...I1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS MOV MOV x1 NEG CPL NEGB CPLB AT EXTR MOVB MOVB x2 CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS PCALL MOV x3 MOVB x4 MOV MOV MOVB MOVB MOV MOV MOVB MOVB x5 DISWDT EINIT MOVBZ MOVBS x6 CMPI1 CMPI2 CMPD1 CMPD2 SCXT SCXT MOV MOV x7 IDLE PWRDN SRVWDT SRST EXTP S R MOVB MOVB x8 MOV MOV MOV MOV MOV MOV MOV x9 MOVB MOVB MOVB MOVB MOVB MOVB MOVB xA JB JNB JBC JNBS CALLA CALLS JMPA J...

Page 8: ...2 Rwn data4 Rwn data16 Rwn mem 2 4 4 BAND BCMP BMOV BMOVN BOR BXOR bitaddrZ z bitaddrQ q 4 CMP B Rwn Rwm 1 Rwn Rwi 1 Rwn Rwi 1 Rwn data3 1 reg data16 2 reg mem 2 2 2 2 4 4 BCLR BSET bitaddrQ q 2 CALLA JMPA cc caddr 4 BFLDH BFLDL bitoffQ mask8 data8 4 CALLI JMPI cc Rwn 2 MOV B Rwn Rwm 1 Rwn data4 1 Rwn Rwm 1 Rwn Rwm 1 Rwm Rwn 1 Rwm Rwn 1 Rwn Rwm Rwn Rwm Rwn Rwm reg data16 2 Rwn Rwm d16 1 Rwm d16 Rw...

Page 9: ...r the arithmetic logical and compare instructions where only R0 to R3 are allowed bitaddr Direct bit in the bit addressable memory area bitoff Direct word in the bit addressable memory area data Immediate constant The number of significant bits which can be specified by the user is represented by the respective appendix x mask8 Immediate 8 bit mask used for bit field modifications Multiply and Div...

Page 10: ...n the SAB 8XC166 W devices Branch Condition Codes cc Symbolically specifiable condition codes cc_UC Unconditional cc_Z Zero cc_NZ Not Zero cc_V Overflow cc_NV No Overflow cc_N Negative cc_NN Not Negative cc_C Carry cc_NC No Carry cc_EQ Equal cc_NE Not Equal cc_ULT Unsigned Less Than cc_ULE Unsigned Less Than or Equal cc_UGE Unsigned Greater Than or Equal cc_UGT Unsigned Greater Than cc_SLE Signed ...

Page 11: ...e data to direct register 4 ADDB reg mem Add direct byte memory to direct register 4 ADDB mem reg Add direct byte register to direct memory 4 ADDC Rw Rw Add direct word GPR to direct GPR with Carry 2 ADDC Rw Rw Add indirect word memory to direct GPR with Carry 2 ADDC Rw Rw Add indirect word memory to direct GPR with Carry and post increment source pointer by 2 2 ADDC Rw data3 Add immediate word da...

Page 12: ...diate byte data from direct register 4 SUBB reg mem Subtract direct byte memory from direct register 4 SUBB mem reg Subtract direct byte register from direct memory 4 SUBC Rw Rw Subtract direct word GPR from direct GPR with Carry 2 SUBC Rw Rw Subtract indirect word memory from direct GPR with Carry 2 SUBC Rw Rw Subtract indirect word memory from direct GPR with Carry and post increment source poin...

Page 13: ...ons AND Rw Rw Bitwise AND direct word GPR with direct GPR 2 AND Rw Rw Bitwise AND indirect word memory with direct GPR 2 AND Rw Rw Bitwise AND indirect word memory with direct GPR and post increment source pointer by 2 2 AND Rw data3 Bitwise AND immediate word data with direct GPR 2 AND reg data16 Bitwise AND immediate word data with direct register 4 AND reg mem Bitwise AND direct word memory wit...

Page 14: ...reg mem Bitwise OR direct byte memory with direct register 4 ORB mem reg Bitwise OR direct byte register with direct memory 4 XOR Rw Rw Bitwise XOR direct word GPR with direct GPR 2 XOR Rw Rw Bitwise XOR indirect word memory with direct GPR 2 XOR Rw Rw Bitwise XOR indirect word memory with direct GPR and post increment source pointer by 2 2 XOR Rw data3 Bitwise XOR immediate word data with direct ...

Page 15: ...rd GPR to direct GPR 2 CMP Rw Rw Compare indirect word memory to direct GPR 2 CMP Rw Rw Compare indirect word memory to direct GPR and post increment source pointer by 2 2 CMP Rw data3 Compare immediate word data to direct GPR 2 CMP reg data16 Compare immediate word data to direct register 4 CMP reg mem Compare direct word memory to direct register 4 CMPB Rb Rb Compare direct byte GPR to direct GP...

Page 16: ...ment GPR by 1 4 CMPI1 Rw mem Compare direct word memory to direct GPR and increment GPR by 1 4 CMPI2 Rw data4 Compare immediate word data to direct GPR and increment GPR by 2 2 CMPI2 Rw data16 Compare immediate word data to direct GPR and increment GPR by 2 4 CMPI2 Rw mem Compare direct word memory to direct GPR and increment GPR by 2 4 Prioritize Instruction PRIOR Rw Rw Determine number of shift ...

Page 17: ... shift cycles specified by immediate data 2 Data Movement MOV Rw Rw Move direct word GPR to direct GPR 2 MOV Rw data4 Move immediate word data to direct GPR 2 MOV reg data16 Move immediate word data to direct register 4 MOV Rw Rw Move indirect word memory to direct GPR 2 MOV Rw Rw Move indirect word memory to direct GPR and post increment source pointer by 2 2 MOV Rw Rw Move direct word GPR to ind...

Page 18: ...t byte GPR to indirect memory 2 MOVB Rw Rw Move indirect byte memory to indirect memory 2 MOVB Rw Rw Move indirect byte memory to indirect memory and post increment destination pointer by 1 2 MOVB Rw Rw Move indirect byte memory to indirect memory and post increment source pointer by 1 2 MOVB Rb Rw data16 Move indirect byte memory by base plus constant to direct GPR 4 MOVB Rw data16 Rb Move direct...

Page 19: ...set 4 JNB bitaddr rel Jump relative if direct bit is not set 4 JNBS bitaddr rel Jump relative and set bit if direct bit is not set 4 CALLA cc caddr Call absolute subroutine if condition is met 4 CALLI cc Rw Call indirect subroutine if condition is met 2 CALLR rel Call relative subroutine 2 CALLS seg caddr Call absolute subroutine in any code segment 4 PCALL reg caddr Push direct word register onto...

Page 20: ...w 4 SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End of Initialization on RSTOUT pin 4 ATOMIC irang2 Begin ATOMIC sequence 2 EXTR irang2 Begin EXTended Register sequence 2 EXTP Rw irang2 Begin EXTended Page sequence 2 EXTP pag10 irang2 Begin EXTended Page sequence 4 EXTPR Rw irang2 Begin EXTended Page and Register sequence 2 EXTPR pag10 irang2 Begin EXTended Page a...

Page 21: ...direct address pointers 2 These instructions are encoded by means of additional bits in the operand field of the instruction 00xx xxxxB EXTS or ATOMIC 01xx xxxxB EXTP 10xx xxxxB EXTSR or EXTR 11xx xxxxB EXTPR The ATOMIC and EXTended instructions are not available in the SAB 8XC166 W devices Notes on the JMPR Instructions The condition code to be tested for the JMPR instructions is specified by the...

Page 22: ...B 2 MUL Rw Rw 2B 2 PRIOR Rw Rw 0C 2 ROL Rw Rw 2C 2 ROR Rw Rw 0D 2 JMPR cc_UC rel 2D 2 JMPR cc_EQ rel or cc_Z rel 0E 2 BCLR bitoff 0 2E 2 BCLR bitoff 2 0F 2 BSET bitoff 0 2F 2 BSET bitoff 2 10 2 ADDC Rw Rw 30 2 SUBC Rw Rw 11 2 ADDCB Rb Rb 31 2 SUBCB Rb Rb 12 4 ADDC reg mem 32 4 SUBC reg mem 13 4 ADDCB reg mem 33 4 SUBCB reg mem 14 4 ADDC mem reg 34 4 SUBC mem reg 15 4 ADDCB mem reg 35 4 SUBCB mem r...

Page 23: ...taddr bitaddr 4B 2 DIV Rw 6B 2 DIVL Rw 4C 2 SHL Rw Rw 6C 2 SHR Rw Rw 4D 2 JMPR cc_V rel 6D 2 JMPR cc_N rel 4E 2 BCLR bitoff 4 6E 2 BCLR bitoff 6 4F 2 BSET bitoff 4 6F 2 BSET bitoff 6 50 2 XOR Rw Rw 70 2 OR Rw Rw 51 2 XORB Rb Rb 71 2 ORB Rb Rb 52 4 XOR reg mem 72 4 OR reg mem 53 4 XORB reg mem 73 4 ORB reg mem 54 4 XOR mem reg 74 4 OR mem reg 55 4 XORB mem reg 75 4 ORB mem reg 56 4 XOR reg data16 7...

Page 24: ...bitaddr rel 8B AB 2 CALLI cc Rw 8C AC 2 ASHR Rw Rw 8D 2 JMPR cc_C rel or cc_ULT rel AD 2 JMPR cc_SGT rel 8E 2 BCLR bitoff 8 AE 2 BCLR bitoff 10 8F 2 BSET bitoff 8 AF 2 BSET bitoff 10 90 2 CMPI2 Rw data4 B0 2 CMPD2 Rw data4 91 2 CPL Rw B1 2 CPLB Rb 92 4 CMPI2 Rw mem B2 4 CMPD2 Rw mem 93 B3 94 4 MOV mem Rw B4 4 MOVB mem Rw 95 B5 4 EINIT 96 4 CMPI2 Rw data16 B6 4 CMPD2 Rw data16 97 4 PWRDN B7 4 SRST ...

Page 25: ... 2 RET EB 2 RETP reg CC 2 NOP EC 2 PUSH reg CD 2 JMPR cc_SLT rel ED 2 JMPR cc_UGT rel CE 2 BCLR bitoff 12 EE 2 BCLR bitoff 14 CF 2 BSET bitoff 12 EF 2 BSET bitoff 14 D0 2 MOVBS Rw Rb F0 2 MOV Rw Rw D1 2 ATOMIC or EXTR irang2 2 F1 2 MOVB Rb Rb D2 4 MOVBS reg mem F2 4 MOV reg mem D3 F3 4 MOVB reg mem D4 4 MOV Rw Rw data16 F4 4 MOVB Rb Rw data16 D5 4 MOVBS mem reg F5 D6 4 SCXT reg mem F6 4 MOV mem re...

Page 26: ...ssing modes available are summarized at the end of each single instruction description In contrast to the syntax for the instructions described in the following the assembler provides much more flexibility in writing C166 Family programs e g by generic instructions and by automatically selecting appropriate addressing modes whenever possible and thus it eases the use of the instruction set For mor...

Page 27: ...stem Configuration register C Carry condition flag in the PSW register V Overflow condition flag in the PSW register SGTDIS Segmentation Disable bit in the SYSCON register count Temporary variable for an intermediate storage of the number of shift or rotate cycles which remain to complete the shift or rotate operation tmp Temporary variable for an intermediate result 0 1 2 Constant values due to t...

Page 28: ...at is executed for a specific condition and the internal representation by a 4 bit number Condition Code Mnemonic cc Test Description Condition Code Number c cc_UC 1 1 Unconditional 0H cc_Z Z 1 Zero 2H cc_NZ Z 0 Not zero 3H cc_V V 1 Overflow 4H cc_NV V 0 No overflow 5H cc_N N 1 Negative 6H cc_NN N 0 Not negative 7H cc_C C 1 Carry 8H cc_NC C 0 No carry 9H cc_EQ Z 1 Equal 2H cc_NE Z 0 Not equal 3H c...

Page 29: ...gs description The flag is not affected by the operation 0 The flag is cleared by the operation NOR The flag contains the logical NORing of the two specified bit operands AND The flag contains the logical ANDing of the two specified bit operands OR The flag contains the logical ORing of the two specified bit operands XOR The flag contains the logical XORing of the two specified bit operands B The ...

Page 30: ...nstruction Opcodes 0 1 Constant Values Each of the 4 characters immediately following a colon represents a single bit ii 2 bit short GPR address Rwi SS Code segment number seg 8 bit for C165 7 2 bit ss for SAB8xC166 2 bit immediate constant irang2 3 bit immediate constant data3 c 4 bit condition code specification cc n 4 bit short GPR address Rwn or Rbn m 4 bit short GPR address Rwm or Rbm q 4 bit...

Page 31: ...pts an ATOMIC or EXTended sequence this sequence is terminated the interrupt lock is removed and the standard condition is restored before the trap routine is executed The remaining instructions of the terminated sequence that are executed after returning from the trap routine will run under standard conditions CAUTION Be careful when using the ATOMIC and EXTended instructions with other system co...

Page 32: ...r Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred ie the result cannot be repre sented in the specified data type Cleared otherwise C Set if a carry is generated from the most significant bit of the specified data type Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise...

Page 33: ...leared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred ie the result cannot be repre sented in the specified data type Cleared otherwise C Set if a carry is generated from the most significant bit of the specified data type Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Ad...

Page 34: ...resents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and previous Z flag was set Cleared other wise V Set if an arithmetic overflow occurred ie the result cannot be repre sented in the specified data type Cleared otherwise C Set if a carry is generated from the most significant bit of the specified data type Cleared otherwise N...

Page 35: ...nts the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and previous Z flag was set Cleared other wise V Set if an arithmetic overflow occurred ie the result cannot be repre sented in the specified data type Cleared otherwise C Set if a carry is generated from the most significant bit of the specified data type Cleared otherwise N Set...

Page 36: ...en stored in op1 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes AND Rwn Rwm 60 nm 2 AND Rwn Rwi 68 n 10ii 2 AND Rwn Rwi 68 n 11ii ...

Page 37: ...stored in op1 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes ANDB Rbn Rbm 61 nm 2 ANDB Rbn Rwi 69 n 10ii 2 ANDB Rbn Rwi 69 n 11ii ...

Page 38: ...nal MSB was a 0 or with ones if the original MSB was a 1 The Overflow flag is used as a Rounding flag The LSB is shifted into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used E Always cleared Z Set if result equals zero Cleared otherwise V Set if in any cycle of the shift operation a 1 is shifted out of the ca...

Page 39: ...iately active such that no additional NOPs are required Depending on the value of op1 the period of validity of the ATOMIC sequence extends over the sequence of the next 1 to 4 instructions being executed after the ATOMIC instruction All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense Any instruction type can be used with the ATOMI...

Page 40: ...rce bit specified by op2 and the destination bit specified by op1 The result is then stored in op1 E Always cleared Z Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Contains the logical XOR of the two specified bits Addressing Modes Mnemonic Format Bytes BAND bitaddrZ z bitaddrQ q 6A QQ Z...

Page 41: ...ption CLears the bit specified by op1 This instruction is primarily used for peripheral and system control E Always cleared Z Contains the logical negation of the previous state of the specified bit V Always cleared C Always cleared N Contains the previous state of the specified bit Addressing Modes Mnemonic Format Bytes BCLR bitaddrQ q qE QQ 2 Condition Flags E Z V C N 0 B 0 0 B ...

Page 42: ...this instruction Only the condition codes are updated Note The meaning of the condition flags for the BCMP instruction is different from the meaning of the flags for the other compare instructions E Always cleared Z Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Contains the logical XOR o...

Page 43: ...sk op2 with the bits at the corre sponding positions in the OR mask specified by op3 Note op1 bits which shall remain unchanged must have a 0 in the respective bit of both the AND mask op2 and the OR mask op3 Otherwise a 1 in op3 will set the corresponding op1 bit see Operation E Always cleared Z Set if the word result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the mo...

Page 44: ... op2 with the bits at the corre sponding positions in the OR mask specified by op3 Note op1 bits which shall remain unchanged must have a 0 in the respective bit of both the AND mask op2 and the OR mask op3 Otherwise a 1 in op3 will set the corresponding op1 bit see Operation E Always cleared Z Set if the word result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most...

Page 45: ...ource operand specified by op2 into the des tination operand specified by op1 The source bit is examined and the flags are updated accordingly E Always cleared Z Contains the logical negation of the previous state of the source bit V Always cleared C Always cleared N Contains the previous state of the source bit Addressing Modes Mnemonic Format Bytes BMOV bitaddrZ z bitaddrQ q 4A QQ ZZ qz 4 Condit...

Page 46: ...e bit from the source operand specified by op2 into the destination operand specified by op1 The source bit is examined and the flags are updated accordingly E Always cleared Z Contains the logical negation of the previous state of the source bit V Always cleared C Always cleared N Contains the previous state of the source bit Addressing Modes Mnemonic Format Bytes BMOVN bitaddrZ z bitaddrQ q 3A Q...

Page 47: ...fied by operand op2 with the destination bit specified by operand op1 The ORed result is then stored in op1 E Always cleared Z Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Contains the logical XOR of the two specified bits Addressing Modes Mnemonic Format Bytes BOR bitaddrZ z bitaddrQ q...

Page 48: ...ption Sets the bit specified by op1 This instruction is primarily used for periph eral and system control E Always cleared Z Contains the logical negation of the previous state of the specified bit V Always cleared C Always cleared N Contains the previous state of the specified bit Addressing Modes Mnemonic Format Bytes BSET bitaddrQ q qF QQ 2 Condition Flags E Z V C N 0 B 0 0 B ...

Page 49: ... specified by operand op2 with the destination bit specified by operand op1 The XORed result is then stored in op1 E Always cleared Z Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Contains the logical XOR of the two specified bits Addressing Modes Mnemonic Format Bytes BXOR bitaddrZ z bi...

Page 50: ...nd op2 is taken The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine If the condition is not met no action is taken and the next instruc tion is executed normally Condition Codes See condition code table E Not ...

Page 51: ...rand op2 is taken The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine If the condition is not met no action is taken and the next instruction is executed normally Condition Codes See condition code table E Not...

Page 52: ...counts the relative distance in words The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine The value of the IP used in the target address calculation is the address of the instruction following the CALLR instru...

Page 53: ...instruction pointer IP is placed onto the system stack Because the IP always points to the instruction fol lowing the branch instruction the value stored on the system stack repre sents the return address to the calling routine The previous value of the CSP is also placed on the system stack to insure correct return to the call ing segment Condition Codes See condition code table E Not affected Z ...

Page 54: ...hanged E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred ie the result cannot be repre sented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result i...

Page 55: ...ged E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred ie the result cannot be repre sented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is s...

Page 56: ...operand op1 is decremented by one Using the set flags a branch instruction can then be used in conjunc tion with this instruction to form common high level language FOR loops of any range E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred...

Page 57: ...operand op1 is decremented by two Using the set flags a branch instruction can then be used in conjunc tion with this instruction to form common high level language FOR loops of any range E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred...

Page 58: ...operand op1 is incremented by one Using the set flags a branch instruction can then be used in conjunc tion with this instruction to form common high level language FOR loops of any range E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred...

Page 59: ...operand op1 is incremented by two Using the set flags a branch instruction can then be used in conjunc tion with this instruction to form common high level language FOR loops of any range E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred...

Page 60: ...the source operand specified by op1 The result is stored back into op1 E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes CPL Rwn 91 n...

Page 61: ...the source operand specified by op1 The result is stored back into op1 E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes CPLB Rbn B1 ...

Page 62: ...hich do not require a watchdog function Fol lowing a reset this instruction can be executed at any time until either a Service Watchdog Timer instruction SRVWDT or an End of Initialization instruction EINIT are executed Once one of these instructions has been executed the DISWDT instruction will have no effect To insure that this instruction is not accidentally executed it is implemented as a prot...

Page 63: ...p1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH E Always cleared Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred ie the result cannot be repre sented in a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Set if the mos...

Page 64: ...perand op1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH E Always cleared Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred ie the result cannot be repre sented in a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Set if...

Page 65: ... operand op1 The unsigned quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH E Always cleared Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred ie the result cannot be repre sented in a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Se...

Page 66: ...nd op1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH E Always cleared Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred ie the result cannot be repre sented in a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Set if the...

Page 67: ...he EINIT instruction has been executed at which time it goes high This enables the program to signal the external circuitry that it has successfully initialized the microcontroller After the EINIT instruction has been executed execution of the Disable Watchdog Timer instruction DISWDT has no effect To insure that this instruction is not accidentally executed it is implemented as a protected instru...

Page 68: ...all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The value of op1 defines the length of the effected instruction sequence Note The EXTR instruction must be used carefully see introductory note The EXTR in...

Page 69: ... are locked The EXTP instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in the EXTP instruction sequence the 10 bit page number address bits A23 A14 is not deter mined by the contents of a DPP register but by the value of op1 itself The 14 bit page offset address bits A13 A0 is derived from the long or indi rect address as usual Th...

Page 70: ...ded SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked For any long mem or indirect address in the EXTP instruction sequence the 10 bit page number address bits A23 A14 is not deter mined by the contents of a DPP register but by the value of op1 itself The 14 bit page offset address bits A13 A0 is derived f...

Page 71: ...ss A hardware traps are locked The EXTS instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in an EXTS instruction sequence the value of op1 determines the 8 bit segment address bits A23 A16 valid for the corresponding data access The long or indirect address itself represents the 16 bit segment offset address bits A15 A0 The value ...

Page 72: ...d number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTSR instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in an EXTSR instruction sequence the value of op1 determines the 8 bit segment address bits A23 A16 valid for the corresponding data access The long or i...

Page 73: ... idle mode In this mode the CPU is powered down while the peripherals remain running It remains powered down until a peripheral interrupt or external interrupt occurs To insure that this instruction is not accidentally executed it is implemented as a protected instruction E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes IDLE 87 78 87...

Page 74: ...nstruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JB instruction If the specified bit is clear the instruction following the JB instruction is executed E Not affected Z Not a...

Page 75: ...eared allowing implementation of semaphore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction fol lowing the JBC instruction If the specified bit was clear the instruction fol lowing the JBC instruction is executed E Always cleared Z Co...

Page 76: ...tion If the condition specified by op1 is met a branch to the absolute address specified by op2 is taken If the condition is not met no action is taken and the instruction following the JMPA instruction is executed normally Condition Codes See condition code table E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes JMPA cc caddr EA c0 M...

Page 77: ...cription If the condition specified by op1 is met a branch to the absolute address specified by op2 is taken If the condition is not met no action is taken and the instruction following the JMPI instruction is executed normally Condition Codes See condition code table E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes JMPI cc Rwn 9C cn...

Page 78: ...ed displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction fol lowing the JMPR instruction If the specified condition is not met program execution continues normally with the instruction following the JMPR instruction Condition Codes S...

Page 79: ...Jump JMPS Syntax JMPS op1 op2 Operation CSP op1 IP op2 Description Branches unconditionally to the absolute address specified by op2 within the segment specified by op1 E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes JMPS seg caddr FA SS MM MM 4 Condition Flags E Z V C N ...

Page 80: ... instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JNB instruction If the specified bit is set the instruction following the JNB instruction is executed E Not affected Z Not...

Page 81: ...s set allowing implementation of semaphore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction fol lowing the JNBS instruction If the specified bit was set the instruction fol lowing the JNBS instruction is executed E Always cleared Z Co...

Page 82: ... Cleared otherwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared other wise V Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise Addressing Modes Mnemonic Format Bytes MOV Rwn Rwm F0 nm 2 MOV Rwn data4 E0 n 2 MOV reg data16 E6 RR 4 MOV Rwn Rwm A8 nm 2 MOV Rwn Rwm 98 nm 2 MOV Rwm Rwn B...

Page 83: ...d otherwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared other wise V Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise Addressing Modes Mnemonic Format Bytes MOVB Rbn Rbm F1 nm 2 MOVB Rbn data4 E1 n 2 MOVB reg data8 E7 RR xx 4 MOVB Rbn Rwm A9 nm 2 MOVB Rbn Rwm 99 nm 2 MOVB Rwm Rbn ...

Page 84: ...urce byte specified by op2 to the word location specified by the destination operand op1 The con tents of the moved data is examined and the condition codes are updated accordingly E Always cleared Z Set if the value of the source operand op2 equals zero Cleared other wise V Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise Addressing ...

Page 85: ... of the source byte specified by op2 to the word location specified by the destination operand op1 The con tents of the moved data is examined and the condition codes are updated accordingly E Always cleared Z Set if the value of the source operand op2 equals zero Cleared other wise V Not affected C Not affected N Always cleared Addressing Modes Mnemonic Format Bytes MOVBZ Rwn Rbm C0 mn 2 MOVBZ re...

Page 86: ...sing the two words specified by operands op1 and op2 respectively The signed 32 bit result is placed in the MD register E Always cleared Z Set if the result equals zero Cleared otherwise V This bit is set if the result cannot be represented in a word data type Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Forma...

Page 87: ... using the two words specified by operands op1 and op2 respectively The unsigned 32 bit result is placed in the MD register E Always cleared Z Set if the result equals zero Cleared otherwise V This bit is set if the result cannot be represented in a word data type Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic F...

Page 88: ...n op1 E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred ie the result cannot be repre sented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is...

Page 89: ...in op1 E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred ie the result cannot be repre sented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result i...

Page 90: ...ion NOP Syntax NOP Operation No Operation Description This instruction causes a null operation to be performed A null operation causes no change in the status of the flags E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes NOP CC 00 2 Condition Flags E Z V C N ...

Page 91: ...hen stored in op1 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes OR Rwn Rwm 70 nm 2 OR Rwn Rwi 78 n 10ii 2 OR Rwn Rwi 78 n 11ii 2 ...

Page 92: ... stored in op1 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes ORB Rbn Rbm 71 nm 2 ORB Rbn Rwi 79 n 10ii 2 ORB Rbn Rwi 79 n 11ii 2 ...

Page 93: ... by the second operand op2 Because IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine E Set if the value of the pushed operand op1 represents the lowest pos sible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the pushed operand op1 equals zero Clea...

Page 94: ...ointer into the operand specified by op1 The Stack Pointer is then incremented by two E Set if the value of the popped word represents the lowest possible neg ative number Cleared otherwise Used to signal the end of a table Z Set if the value of the popped word equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the popped word is set Cleared other wise...

Page 95: ...res a count value in the word operand specified by op1 indicating the number of single bit shifts required to normalize the operand op2 so that its MSB is equal to one If the source operand op2 equals zero a zero is written to operand op1 and the zero flag is set Otherwise the zero flag is cleared E Always cleared Z Set if the source operand op2 equals zero Cleared otherwise V Always cleared C Alw...

Page 96: ... system stack specified by the Stack Pointer after the Stack Pointer has been decremented by two E Set if the value of the pushed word represents the lowest possible neg ative number Cleared otherwise Used to signal the end of a table Z Set if the value of the pushed word equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the pushed word is set Cleared...

Page 97: ...e powered down until the part is externally reset To insure that this instruction is not accidentally exe cuted it is implemented as a protected instruction To further control the action of this instruction the PWRDN instruction is only enabled when the non maskable interrupt pin NMI is in the low state Otherwise this instruction has no effect E Not affected Z Not affected V Not affected C Not aff...

Page 98: ...ET Operation IP SP SP SP 2 Description Returns from a subroutine The IP is popped from the system stack Exe cution resumes at the instruction following the CALL instruction in the call ing routine E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes RET CB 00 2 Condition Flags E Z V C N ...

Page 99: ...k Execution resumes at the instruction which had been interrupted The previous system state is restored after the PSW has been popped The CSP is only popped if segmentation is enabled This is indi cated by the SGTDIS bit in the SYSCON register E Restored from the PSW popped from stack Z Restored from the PSW popped from stack V Restored from the PSW popped from stack C Restored from the PSW popped...

Page 100: ...k into the operand specified by op1 Execution resumes at the instruction following the CALL instruction in the calling routine E Set if the value of the word popped into operand op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the word popped into operand op1 equals zero Cleared otherwise V Not affected C Not affected N Se...

Page 101: ...on IP SP SP SP 2 CSP SP SP SP 2 Description Returns from an inter segment subroutine The IP and CSP are popped from the system stack Execution resumes at the instruction following the CALLS instruction in the calling routine E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes RETS DB 00 2 Condition Flags E Z V C N ...

Page 102: ...ource operand op2 Bit 15 is rotated into Bit 0 and into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used E Always cleared Z Set if result equals zero Cleared otherwise V Always cleared C The carry flag is set according to the last MSB shifted out of op1 Cleared for a rotate count of zero N Set if the most sign...

Page 103: ...5 and into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used E Always cleared Z Set if result equals zero Cleared otherwise V Set if in any cycle of the rotate operation a 1 is shifted out of the carry flag Cleared for a rotate count of zero C The carry flag is set according to the last LSB shifted out of op1 C...

Page 104: ...o switch contexts for any register Switching context is a push and load operation The contents of the register specified by the first operand op1 are pushed onto the stack That register is then loaded with the value specified by the second operand op2 E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes SCXT reg data16 C6 RR 4 SCXT reg m...

Page 105: ...ficant bits of the result are filled with zeros accordingly The MSB is shifted into the Carry Only shift val ues between 0 and 15 are allowed When using a GPR as the count con trol only the least significant 4 bits are used E Always cleared Z Set if result equals zero Cleared otherwise V Always cleared C The carry flag is set according to the last MSB shifted out of op1 Cleared for a shift count o...

Page 106: ... Rounding flag This flag together with the Carry flag helps the user to determine whether the remainder bits lost were greater than less than or equal to one half an LSB Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used E Always cleared Z Set if result equals zero Cleared otherwise V Set if in any cycle of the shift oper...

Page 107: ...o perform a software reset A software reset has the same effect on the microcontroller as an externally applied hardware reset To insure that this instruction is not accidentally executed it is implemented as a protected instruction E Always cleared Z Always cleared V Always cleared C Always cleared N Always cleared Addressing Modes Mnemonic Format Bytes SRST B7 48 B7 B7 4 Condition Flags E Z V C ...

Page 108: ...loads the high order byte of the Watchdog Timer with a preset value and clears the low byte on every occurrence Once this instruction has been executed the watchdog timer cannot be disabled To insure that this instruction is not accidentally executed it is implemented as a protected instruction E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic For...

Page 109: ...e lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred ie the result cannot be repre sented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemo...

Page 110: ...west possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred ie the result cannot be repre sented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic ...

Page 111: ...ic E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and the previous Z flag was set Cleared other wise V Set if an arithmetic underflow occurred ie the result cannot be repre sented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most si...

Page 112: ...ision arithmetic E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred ie the result cannot be repre sented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of th...

Page 113: ...vector table entry point This routine has no indication of whether it was called by software or hardware System state is preserved identically to hardware interrupt entry except that the CPU priority level is not affected The RETI return from interrupt instruction is used to resume execution after the trap or interrupt routine has completed The CSP is pushed if segmentation is enabled This is indi...

Page 114: ...sult is then stored in op1 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes XOR Rwn Rwm 50 nm 2 XOR Rwn Rwi 58 n 10ii 2 XOR Rwn Rwi ...

Page 115: ...t is then stored in op1 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes XORB Rbn Rbm 51 nm 2 XORB Rbn Rwi 59 n 10ii 2 XORB Rbn Rwi ...

Page 116: ...ddressing modes allow to access the GPR SFR or bit addressable memory space Physical Address Base Address Short Address Note is 1 for byte GPRs is 2 for word GPRs The Extended Special Function Register ESFR area is not available in the SAB 8XC166 W devices Mnemonic Physical Address Short Address Range Scope of Access Rw CP 2 Rw Rw 0 15 GPRs Word Rb CP 1 Rb Rb 0 15 GPRs Byte reg 00 FE00H 2 reg 00 F...

Page 117: ...om F0H to FFH always specify GPRs In that case only the lower four bits of reg are significant for physical address generation and thus it can be regarded as being identical to the address generation described for the Rb and Rw addressing modes bitoff Specifies direct access to any word in the bit addressable memory space bitoff requires eight bits in the instruction format Depending on the specif...

Page 118: ...e offset while bits 15 14 specify the Data Page Pointer 1 of 4 which is to be used to generate the physical 18 bit or 24 bit address see figure below Figure 6 1 Interpretation of a 16 bit Long Address The SAB 8XC166 W devices support an address space of up to 256 KByte while the C167 5 devices support an address space of up to 16 MByte so only the lower two or ten bits respectively of the selected...

Page 119: ...addresses are specified indirectly by the contents of a word GPR which is specified directly by a short 4 bit address Rw 0 to 15 There are indirect addressing modes which add a constant value to the GPR contents before the long 16 bit address is calculated Other indirect addressing modes allow decrementing or incrementing the indirect address pointers GPR content by 2 or 1 referring to words or by...

Page 120: ...s by adding a constant value if selected to the content of the indirect address pointer Long Address GPR Pointer Constant 4 Calculate the physical 18 bit or 24 bit address using the resulting long address and the cor responding DPP register content see long mem addressing modes Physical Address DPPi Page offset 5 Post Incremented indirect address pointers Rw are incremented by a data type dependen...

Page 121: ...nge 1 4 is coded in the 2 bit constant irang2 and is represented by the values 0 3 Branch Target Addressing Modes Different addressing modes are provided to specify the target address and segment of jump or call instructions Relative absolute and indirect modes can be used to update the Instruction Pointer register IP while the Code Segment Pointer register CSP can only be updated with an absolute...

Page 122: ...PR In contrast to indirect data addresses indirectly specified code addresses are NOT calculated via additional pointer registers eg DPP registers Branches MAY NOT be taken to odd code addresses Therefore the least significant bit of the address pointer GPR must always contain a 0 otherwise a hardware trap would occur seg Specifies an absolute code segment number The devices of the SAB 80C166 grou...

Page 123: ... via the bootstrap loader The following description allows evaluating the minimum and maximum program execution times This will be sufficient for most requirements For an exact determination of the instructions state times it is recommended to use the facilities provided by simulators or emulators This section defines the subsequently used time units summarizes the minimum standard state times of ...

Page 124: ... of this table Most of the 16 bit microcontroller instructions except some of the branches the multiplication the division and a special move instruction require a minimum of two state times In case of internal ROM program execution there is no execution time dependency on the instruction length except for some special branch situations The injected target instruction of a cache jump instruction c...

Page 125: ...e number for a 16 bit wide bus Additional State Times Some operand accesses can extend the execution time of an instruction TIn Since the additional time TIadd is mostly caused by internal instruction pipelining it often will be possible to evade these timing effects in time critical program modules by means of a suitable rearrangement of the corresponding instruction sequences Simulators and emul...

Page 126: ...te of the stack pointer In 1 SCXT R1 1000h implicit decrement of the stack pointer TIadd 2 States In these cases the extra state times can be avoided by putting other suitable instructions before the instruction In 1 reading the SFR External operand reads TIadd 1 ACT Any external operand reading via a 16 bit wide data bus requires one additional ALE Cycle Time Reading word operands via an 8 bit wi...

Page 127: ... aligned double word instructions as shown in the following example label any non aligned double word instruction eg at location 12FAH It 1 any non aligned double word instruction eg at location 12FEH In 1 JMPR cc_ UC label provided that a cache jump is taken TIadd 2 States TIn 4 States If required these extra state times can be avoided by allocating double word jump target instructions to aligned...

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