A30808-X3247-L14-2-7618
17
Information
Base Station System
Technical Description (TED:BSS)
BS-240/241
2.1
Board Redundancy
Redundancy in the SBS ensures survival of the system even in the event of multiple fail-
ures. Modular architecture, in conjunction with the concept of split functions, guarantees
maximum survivability with a minimum of additional hardware.
2.1.1
AC/DC
Up to 6 AC/DC converters can be equipped in the service1 Rack which provide N+1
redundancy. AC/DC converters work in load sharing, but n AC/DC are able to supply the
whole BS-240/241.
2.1.2
Core
The Core can consist of up to 2 (without redundancy) or up to 4 (with redundancy)
boards, which have a common backplane. The block diagram depicts the 2n CORE
redundancy and the embedding of the active and the passive CORE into the BTS, and
the interrelation of both COREs.
Fig. 2.3
Redundant COREs and their Interfaces
Both COREs (COBA0/COSA0 and COBA1/COSA1) have link interfaces to the ABIS
lines, but only one (the active CORE) can be connected.
On the backplane of the BTS, one connector provides a link of the LMT to the current
active CORE. In the case of a CORE switch over, the switch logic switches that
connector to the new active CORE. The same holds for the CAN bus (alarm bus), i.e.,
both COREs have the same CAN bus address where at any time at most one CORE is
an active CAN bus node.
Both the active and the passive CORE have links to the carrier units (CU); in reverse,
each CU is linked with both COREs. The traffic data are transmitted transparently
through the active CORE. Signal processing takes place only within the CUs.
The endpoints of each link are built up by SELIC ASICs (note: one SELIC contains
double functionality), where on the CU, one SELIC serves two COREs. In the case of a
CU
SELIC
SELIC
BISON
RD
Interf.
Switch
Logic
FALC
CORE 0
CLK
Route Clock
Redundancy Link
Switch Logic Link
Route Clock
(Frame Sync)
ABIS
CAN
LMT
µ
P
CU
SELIC
CU
SELIC
SELIC
SELIC
SELIC
BISON
RD
Interf.
Switch
Logic
FALC
CORE 1
CLK
Route Clock
µ
P
SELIC
SELIC
