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Bank Interleave
The interleave number of internal banks, can be set to 2 way, 4 way
interleave or disabled. For VCM and 16Mb type dram chips, the bank
interleave is fixed at 2 way interleave.
When the dram timing is selected by SPD, it will be set by the value on
SPD of the RAM module(DDR or SDR).
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The Choice: Disabled, 2 Bank, or 4 Bank.
Memory Hole
In order to improve performance, some space in memory can be
reserved for ISA cards.
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The Choice: Disabled or 15M-16M.
PCI Master Pipeline Req
Enable this item to enhance PCI bus for better performance.
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The choice: Enabled, Disabled.
P2C/C2P Concurrency
This item allows you to enable/disable the PCI to CPU and CPU to PCI
concurrently.
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The Choice: Enabled or Disabled.
Fast R-W Turn Around
This item controls the DRAM Timing. It allows you to enable/disable
the fast read/write turn-around.
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The Choice: Enabled or Disabled.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any pro-
gram is written to this memory area, a system error may result.
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The choice: Enabled or Disabled.
Video RAM Cacheable
Selecting Enabled allows caching of the video RAM , resulting in better
system performance. However, if any program is written to this memory
area, a system error may result.
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The Choice: Enabled or Disabled.
Frame Buffer Size
This item allows you to control the VGA frame buffer size.
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The choice: 2M, 4M, or 8M.
