SD-EX220H
8 – 5
IC101 VHiCS4340KS-1: DAC IC (CS4340KS) (2/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal whitch is not connected to the outside.
Pin No.
Port Name
Input/Output
Function
6, 7
DIF1, DIF0
Input
Digital Interface Format
The required relationship between the Left/Right clock, serial clock and serial data is defined.
8
DEM0
Input
De-emphasis Control
Implementation of the standard 15
µ
s/50
µ
s digital de-enphasis filter response, required
reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz
sample rates.
When using Internal Serial Clock Mode, as described above, Pin 3 is available for de-emphasis
control, DEM1, and all de-enphasis filters are available.
When using External Serial Clock Mode, as described above, Pin 3 is not available for
de-emphasis use and only the 44.1 kHz de-emphasis filter is available.
Note:
De-emphasis is not available in High-Rate Mode.
9
FILT+
Output
Positive Voltage Reference
Positive reference for internal sampling circuits.
An external capacitor is required from FILT+ to analog ground.
The recommended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 kHz.
FILT+ is not intended to supply external circuit. FILT+ has a typical source impedance of 250
kohms and any current drawn from this pin will alter device performance.
10
VQ
Output
Quiescent Voltage
Filter connection for internal quiescent reference voltage, typically 50 % of VA.
Capacitors must be connected from VQ to analog ground.
VQ is not intended to supply external current.
VQ has a typical source impedance of 250 kohms and any current drawn from this pin will
alter device performance.
11
REF_GND
Input
Reference Ground
Ground reference for the internal sampling circuits. Must be connected to analog ground.
12
AOUTR
Output
Analog Output
The full scale analog output level is specified in the Analog Characteristics specifications table.
13
AGND
Input
Ground
Ground Reference.
14
VA
Input
Analog Power
Analog power supply. Typically 3 to 5 VDC.
15
AOUTL
Output
Analog Output
The full scale analog output level is specified in the Analog Characteristics specifications table.
16*
MUTEC
Output
Mute Control
The Mute Control pin goes high during power-up initialization, reset, muting, master clock to
left/right clock frequency ratio is incorrect or power-down this pin is intended to be used as a
control for an external mute circuit to prevent the clicks and pops that can occur in any single
supply system. Use of Mute Control is not mandatory but recommended for designs requiring
the absolute minimum in extraneous clicks and pops.
DIF1
DIF0
DESCRIPTION
FORMAT
0
0
I
2
S, up to 24-bit data
0
0
1
Left Justified, 24-bit Data
1
1
0
Right Justified, 24-bit Data
2
1
1
Right Justified, 16-bit Data
3
Digital Interface Format
DEM0
DESCRIPTION
0
Disabled
1
44.1 kHz
External Serial Clock Mode
DEM0
DESCRIPTION
0
Disabled
1
44.1 kHz
0
48 kHz
1
32 kHz
Internal Serial Clock Mode
