24
R - 5 2 0 D K
R -520DW
R - 5 3 0 D K
R -530DW
50
P37
IN
To input signal which communicates the door open/close information to LSI.
Door close "H" level signal (0V). Door open "L" level signal (-5V).
51
COM0
OUT
Common data signal: COM2.
Connected to LCD signal COM2.
52
COM1
OUT
Common data signal: COM1.
Connected to LCD signal COM1.
53
COM2
OUT
Common data signal: COM0.
Connected to LCD signal COM0.
54
COM3
OUT
Terminal not used.
55
BIAS
IN
Power source voltage : GND(0V).
56
VLC0
IN
Power source voltage input terminal.
Standard voltage for LCD. Connected to GND.
57-58
VLC1-VLC2
IN
Power source voltage input terminal.
Standard voltage for LCD.
59
VSS0
IN
Power source voltage: -5.0V.
The power source voltage to the LSI is input to VSS0 terminal. Connected toVC.
60-95
S0-S35
OUT
Segment data signal.
Connected to LCD.
The relation between signals are as follows:
LSI signal (Pin No.)
LCD (Pin No.)
LSI signal (Pin No.)
LCD (Pin No.)
S0 (60) ................................... SEG 0
S18 (78) ................................. SEG 18
S1 (61) ................................... SEG 1
S19 (79) ................................. SEG 19
S2 (62) ................................... SEG 2
S20 (80) ................................. SEG 20
S3 (63) ................................... SEG 3
S21 (81) ................................. SEG 21
S4 (64) ................................... SEG 4
S22 (82) ................................. SEG 22
S5 (65) ................................... SEG 5
S23 (83) ................................. SEG 23
S6 (66) ................................... SEG 6
S24 (84) ................................. SEG 24
S7 (67) ................................... SEG 7
S25 (85) ................................. SEG 25
S8 (68) ................................... SEG 8
S26 (86) ................................. SEG 26
S9 (69) ................................... SEG 9
S27 (87) ................................. SEG 27
S10 (70) .................................. SEG 10
S28 (88) ................................. SEG 28
S11 (71) .................................. SEG 11
S29 (89) ................................. SEG 29
S12 (72) .................................. SEG 12
S30 (90) ................................. SEG 30
S13 (73) .................................. SEG 13
S31 (91) ................................. SEG 31
S14 (74) .................................. SEG 14
S32 (92) ................................. SEG 32
S15 (75) .................................. SEG 15
S33 (93) ................................. SEG 33
S16 (76) .................................. SEG 16
S34 (94) ................................. SEG 34
S17 (77) .................................. SEG 17
S35 (95) ................................. SEG 35
96-99
P83-P80
OUT
Terminal not used.
Pin No.
Signal
I/O
Description
LSI(IXA037DR) : R-530DK/DW
The I/O signal of the LSI(IXA037DR) is detailed in the following table.
Pin No.
Signal
I/O
Description
1-2
P26-P27
OUT
Terminal not used.
3-5
P70-P72
OUT
Terminal not used.
6
IC
IN
Connected to VC.
7
X2
OUT
Internal clock oscillation output.
Output to control oscillation input to X2.
8
X1
IN
Internal clock oscillation frequency control input setting.
The internal clock frequency is set by inserting the ceramic filter oscillation circuit with
respect to X1.
9
VDD1
IN
Power source voltage: GND(0V).
The power source voltage to drive LSI is input to VDD1 terminal.
10
XT1
IN
Connected to GND.