MD-R3H
– 35 –
Figure 35 BLOCK DIAGRAM (2/4)
1
2
6
5
4
3
4
9
8
39
15
21
38
10
11
12
13
14
35
34
29
28
30
25
24
26
27
31
33
36
23
22
32
37
41
18
16
40
42
17
19
20
7
6
2
5
3
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
1
2
3
4
1
2
6
5
4
3
M
M
GND
CH4-OUTA
CH4-OUTB
CH4-INA
CH4-INB
BIAS IN
OP OUT
GND
CH2-OUTA
CH2-OUTB
CH2-INA
CH2-INB
MUTE
VREG OUT
GND
TR-B
CH1-INB
CH1-INA
CH1-OUTB
CH1-OUTA
CH3-OUTB
CH3-OUTA
OP IN (+)
OP IN (–)
VCC
VCC
D. BUF
D. BUF
D. BUF
D. BUF
LEVEL
SHIFT
LEVEL
SHIFT
50K
50K
VCC
VCC
6.65K
10K
10K
6.65K
6.65K
10K
– +
+ –
+
–
+ –
LEVEL
SHIFT
LEVEL
SHIFT
D. BUF
D. BUF
6.65K
10K
D. BUF
D. BUF
–
+
+
–
+
–
+
–
–
+
+
–
PWM MOD.
SYNC DET.
PROTECT
EFM
DEMOD.
EFM TIMING GEN.
PHASE DET.
FREQ. DET.
VCO
18K SRAM
MEMORY CONTROL
CIRC DECODER
ERROR MONITOR
(8BITX2400WORD)
CONTROL
CLV SERVO CONTROL
PHASE
FREQ.
CONTROL
4FS DIGITAL
FILTER
FILTER
DC-EMPHASIS
2/3 DET.
CLV SERVO CONTROL
STATUS CONTROL
ATT CONTROL
RESERVED
SLP CONTROL
SUBCODE Q CONTROL
RESERVED
TEST CONTROL
MCU INTERFACE
DAC
INTERFACE
GENERATOR
X'TAL TIMING
GENERATOR
CLOCK
SEL
RESET
ANALOG
VDD
ANALOG
GND
SUBCODE Q CRC
SUBCODE Q REGISTER
SUBCODE DEMOD.
HF COMPARATOR
DIGITAL
DIGITAL
VDD
GND
INTERPOLATION
MUTE CONTROL
DIGITAL AUDIO
INTERFACE
LRCK3
C432
C846
CKSEL
EST1
EST2
XO
DO2
LOCK/
DRD
ALCR
MOD2
MOD1
MOD0
MLA
MCK
MSD
PWM1
PWM2
VSS2
VDD2
VDD1
VSS1
SBQS
EMP
SCAND
SBCO
SCCK
TLC
HF
HFD
LPF
EFFK
SYCLK
IREF
CRCF
DO1
LRCK1
DSCK
WDCK
LRCK2
DOTX
1
CH3-INA
CH3-INB
POWER+7V
VOLTAGE
REGULATOR
5V
CD+5V
CD+5V
CD+5V
GND
CD +5V
CD +7V
DIGITAL OUT
GND
GND
BI851
CNS502
XI
M701
SLED
MOTOR
M702
PICKUP IN
SW702
SPINDLE
MOTOR
FOCUS/TRACKING/
SPIN/SLIDE DRIVER
BA5914FP
IC700
SERVO/SIGNAL
CONTROL
M65821FP
IC800
X801
8.46MHz
1
2