48
LC-60LE651 MK2
LC-60LE652 MK2
IC 3800:
STANDBY CONTROLLER
Part number: STM8S105K4T6CTR (ST MICRO)
Sharp code: RH-IXD550WJZZY
http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00200092.pdf
Features
Core.
o
16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline.
o
Extended instruction set.
Memories.
o
Medium-density Flash/EEPROM:
Program memory up to 32 Kbytes (data retention: 20 years at 55°C after 10k cycles).
Data memory up to 1 Kbytes true data EEPROM (endurance 300k cycles).
o
RAM: Up to 2 Kbytes.
Clock, reset and supply management.
o
2.95 V to 5.5 V operating voltage.
o
Flexible clock control, 4 master clock sources:
Low power crystal resonator oscillator.
External clock input.
Internal, user-trimmable 16 MHz RC.
Internal low power 128 kHz RC.
Clock security system with clock monitor.
Power management:
o
Low power modes (wait, active-halt, halt).
o
Switch-off peripheral clocks individually.
Permanently active, low consumption power-on and
power-down reset.
Interrupt management
o
Nested interrupt controller with 32 interrupts.
o
Up to 37 external interrupt on 6 vectors.
Timers.
o
2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM).
o
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-
time insertion and flexible synchronization.
o
8-bit basic timer with 8-bit prescaler.
o
Auto wake-up timer.
o
Window and independent watchdog timers.
Communications interfaces.
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UART with clock output for synchronous
operation, Smartcard, IrDA, LIN.
o
SPI interface up to 8 Mbit/s.
o
I2C interface up to 400 Kbit/s.
Analog-to-digital converter (ADC).
o
10-bit, ±1 LSB ADC with up to 10
multiplexed channels, scan mode and analog
watchdog.
I/Os.
o
Up to 38 I/Os on a 48-pin package including
16 high sink outputs.
o
Highly robust I/O design, immune against
current injection
Unique ID.
o
96-bit unique key for each device.
MAJOR ICs INFORMATION ( continued )
