Sharp LC-32LE140E, Service Manual

Page: 34 / 88

34
LC-32LE140
Output Interface
 Single/dual link 8/10-bit LVDS output
 Supports panel resolution up to Full-HD (1920x1080) @ 60Hz
 Supports TH/TI format
 Supports dithering options to 6/8-bit output
 Spread spectrum output for EMI suppression
CVBS Video Encoder
 Supports all NTSC/PAL TV Standard
 Stand-alone scaling engine
 Programmable Hue, Contract, Brightness
 Supports TTX/CC/WSS output
CVBS Video Output
 Allows CVBS output of all source inputs
2D Graphics Engine
 Hardware Graphics Engine for responsive
 Interactive applications
 Supports point draw, line draw, rectangle draw/fill, text draw and trapezoid draw
 BitBlt, stretch BitBlt, trapezoid BitBlt, mirror BitBlt and rotate BitBlt
 Raster Operation (ROP)
 Support Porter-Duff
VIF Demodulator
 Compliant with NTSC M/N, PAL B, G/H, I, D/K,
 SECAM L/L' standards
 Audio/Video dual-path processor
 Stepped-gain PGA with 25 dB tuning range and 1 dB tuning resolution
 Maximum IF gain of 37 dB
 Programmable TOP to accommodate different tuner gain and SAW filter insertion
loss to
optimize noise and linearity performance
 Multi-standard processing with single SAW
 Supports silicon tuner low IF output architecture
DVB-T Demodulator
 Digital carrier frequency offset correction: ±500KHz
 Optimised for SFN channels with pre/post-cursive echoes inside/outside the guard
 Acquisition range ±857kHz includes up to 3x ±1/6 MHz transmitter offset
 Meets Nordig Unified 1.0.3, D-Book 5.0, EICTA E-Book/C-Book test requirement
 ±400kHz internal carrier offset recovery range
 6.8 usecs echo cancellation at 7 Msym/s
 Supports IF, low-IF, zero-IF inputs
 Ultra-fast automatic blind UHF/VHF channel scan (constellations and symbol rate)
Connectivity
 Two USB 2.0 host ports
Output Interface
 Single/dual link 8/10-bit LVDS output

Supports panel resolution up to Full-HD (1920x1080) @ 60Hz
 Supports TH/TI format
 Supports dithering options to 6/8-bit output
 Spread spectrum output for EMI suppression
CVBS Video Encoder
 Supports all NTSC/PAL TV Standard
 Stand-alone scaling engine
 Programmable Hue, Contract, Brightness
 Supports TTX/CC/WSS output
CVBS Video Output
 Allows CVBS output of all source inputs
2D Graphics Engine
 Hardware Graphics Engine for responsive
 Interactive applications
 Supports point draw, line draw, rectangle draw/fill, text draw and trapezoid draw
 BitBlt, stretch BitBlt, trapezoid BitBlt, mirror BitBlt and rotate BitBlt
 Raster Operation (ROP)
 Support Porter-Duff
VIF Demodulator
 Compliant with NTSC M/N, PAL B, G/H, I, D/K,
 SECAM L/L' standards
 Audio/Video dual-path processor
 Stepped-gain PGA with 25 dB tuning range and 1 dB tuning resolution
 Maximum IF gain of 37 dB
 Programmable TOP to accommodate different tuner gain and SAW filter insertion
loss to
optimize noise and linearity performance
 Multi-standard processing with single SAW
 Supports silicon tuner low IF output architecture
DVB-T Demodulator
 Digital carrier frequency offset correction: ±500KHz
 Optimised for SFN channels with pre/post-cursive echoes inside/outside the guard
 Acquisition range ±857kHz includes up to 3x ±1/6 MHz transmitter offset
 Meets Nordig Unified 1.0.3, D-Book 5.0, EICTA E-Book/C-Book test requirement
 ±400kHz internal carrier offset recovery range
 6.8 usecs echo cancellation at 7 Msym/s
 Supports IF, low-IF, zero-IF inputs
 Ultra-fast automatic blind UHF/VHF channel scan (constellations and symbol rate)
Connectivity
 Two USB 2.0 host ports
 USB architecture designed for efficient support of external storage devices in
conjunction with
off air broadcasting
Miscellaneous
 DRAM interface supporting one 16-bit DDR2 @1066MHz
 Supports PVR
 Supports Common Interface for conditional access support
 Bootable SPI interface with serial flash support
 Parallel interface for external NAND flash support
 Power control module with ultra low power MCU available in standby mode
 380-ball LFBGA package
 Operating Voltages: 1.26V (core), 1.8V (DDR2), 2.5V and 3.3V (I/O and analog)
5.2. MSTAR Block Diagram