Sharp LC-30HV2E, Service Manual

Page: 52 / 173

52
LC-30HV2E
Pin Name Pin No. Type Description
In DVI mode, a HIGH level indicates that the link from the transmitter to the SiI861 is active. A
LOW level indicates a “Loss of Sync” condition between the transmitter and the SiI861.
Please refer to the Section 8. PD does not affect this output when operating in pull-down mode
STDBY/ 5 Out Standby. In non-DVI mode, a HIGH level indicates a standby condition. A LOW level indicates a
normal active condition.
In DVI mode, this pin is PWM0.
Please refer to the Section 8. PD does not affect this output when operating in pull-down mode
SUSPD / 6 Out Suspend / Out of Range. In non-DVI mode, a HIGH level indicates a suspend condition. A LOW
level indicates a normal active condition.
In DVI mode, a HIGH level indicates an “Out of Range” condition. A LOW level indicates normal
operation.
Please refer to Section 7. PD does not affect this output.
PWM0 107 Out Pulse Width Modulation. These pins can be used as the pulse width modulation signal to control
the backlight brightness or volume.
Please refer to the Section 13 for more information. PD# does not affect this output when in pull-
down mode
BUT0+ 108 In These pins are used to monitor pushbuttons, which can directly control the PWM0 and PWM1
outputs. BUT0+/- are used for PWM0 control, and BUT1+/- are used for PWM1 control. These
pins have internal 100K pull-down resistors.
XCLK 161 In External clock input. See Section 6 External Clock Rate and Input Frame Rate
XTAL1 154 In External crystal input to the inverting oscillator amplifier or clock oscillator input.
This sets the output clock frequency to the panel, which will equal this frequency or be 5 times this
frequency if the clock multiplier is used. This pin is 5V tolerant.
See Section 6 External Clock Rate and Input Frame Rate.
XTAL2 155 Out Output from inverting oscillator amplifier when using on-chip crystal oscillator.
No-connect when using external clock.
RESET# 3 In R eset (active LOW). When this pin is pulled LOW, the SiI861 will enter a reset state. When RESET
goes HIGH, the SiI861 begins loading the internal I2C registers automatically from the external
configuration EEPROM.
RX0+ 196 Analog TMDS TM Low Voltage Differential Signal input data pairs.
RX0- 197 Analog Maximum input pixel clock on TMDS input is 112 MHz.
RX1+ 191 Analog
RX1- 192 Analog
RX2+ 186 Analog
RX2- 187 Analog
RXC+ 199 Analog TMDS TM Low Voltage Differential Signal input clock pairs.
RXC- 200 Analog
X_RES 202 Analog Impedance Matching Control. Resistor value should be ten times the characteristic single-ended
impedance of the cable. In the common case of 50 transmission line, an external 400 resistor
must be connected between AVCC and this pin.
TMDS_SEL 112 In Selects PanelLink or Parallel as input source. Default active high: High = PanelLink, Low = Paral-
lel. This pin has an internal 100K pull-up resistor. Polarity control can be changed in register
ADD1, see page 94 for more detail.
PD[23-0] 37-60 In Corresponds to 24-bit pixel data for 1-pixel/clock input mode. These pins have internal 100K pull-
down resistors.
PCLK 64 In Input data clock for parallel input. This pin has an internal 100K pull-down resistor.
PDE 61 In Input Data Enable for parallel input. This signal qualifies the active data area. A HIGH level signi-
fies valid display time. A LOW level signifies a valid blanking time. This pin has an internal 100K
pull-down resistor.
PHS 62 In Horizontal Sync control signal input on parallel input.
PVS 63 In Vertical Sync control signal input on parallel input.
These pins have internal 100K pull-down resistors.
ADE 70 Out An external DE signal is generated based on the parallel input IN_HSYNC and IN_VSYNC pins. If
using an external component that does not generate DE, such as a TV decoder, this signal should
be connected externally to IN_DE. The timing of this signal is controlled by the “DE Generation”
registers explained on page 94.
TSTMD 8 In For TEST purposes only. Should be tied LOW.
TSTEN 9 In For TEST purposes only. Should be tied LOW.
DVCC 2,11,27, Power Digital Core VCC, must be set to 2.5V.
75,87,
104,113,
137,
147,163,
208
GND 1,10,26, Ground Digital GND.
76,88,
103,114,
138,
148,153,
PWM0
O_RNG
PWM1 106
BUT0- 109
BUT1+ 110
BUT1- 111
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Pin Function