A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
2
1
3
4
5
6
7
8
2
1
3
4
5
6
7
8
C2583
100
16V
V-S
IC2404
NJM4580V(TE1)
AUDIO_AMP IC
1
2
3
4
5
6
7
8
OF PRINTING AND SUBJECT TO CHANGE WITHOUT NOTICE
NOTE: THIS SCHEMATIC DIAGRAM IS THE LATEST AT THE TIME
WAS RECEIVED IN GOOD CONDITION AND PICTURE IS NORMAL.
WITH THE DIGITAL TESTER WHEN THE COLOR BROADCAST
NOTE:THE DC VOLTAGE AT EACH PART WAS MEASURED
JG2454
JG2453
JG2469
JG2460
JG2461
JG2459
W901
W900
B2422
FCM1608KF-151T06
B2421
FCM1608KF-151T06
B2418
FCM1608KF-151T06
B2419
FCM1608KF-151T06
B2420
FCM1608KF-151T06
B2430
FCM1608KF-151T06
B2423
FCM1608KF-151T06
R2500
6.8K
R2498
43K
R2499
43K
R2501
6.8K
R2497
43K
R2496
43K
R2486
27K
R2487
27K
R2489
27K
R2488
27K
R2479
4.7K
R2478
4.7K
R2481
4.7K
R2482
4.7K
R2490
33
R2491
33
R2493
33
R2492
33
R2494
33
R2483
33
R2484
33
R2480
680
R2477
680
C2557
10
C
C2559
1B
C2567
0.1
B
C2566
0.1
B
C2565
0.1
B
C2564
0.1
B
C2563
0.1
B
C2562
0.1
B
C2561
0.1
B
C2560
0.1
B
C2558
10
C
C2584
10 C
C2575
68P
CH
C2579
68P CH
C2586
0.001
B
C2585
10 C
C2582
0.1
B
C2555
10
C
C2554
10
C
C2556
10
C
C2577
10
C
C2580
0.1
B
C2587
0.001
B
C2581
68P CH
C2574
68P
CH
C2572
470P
CH
C2571
470P
CH
B22
A22
AA1
V2
V1
AA2
Y1
Y2
AC1
AC2
AB1
AF2
AE2
AD3
AE1
AD1
AD2
B23
C23
B21
C21
C24
B24
A23
A24
C22
AE3
A21
AC3
AB2
W1
W2
AA4
AA3
W3
W4
AB3
AB4
Y3
IC2401 X242
ATSC/CLEAR CABLE ASIC IC
Y4
R[PR]_OUT
G[Y]_OUT
B[PB]_OUT
X242_SPDIF
X242_SPDIF
I2SSCK_IND
I2SSD_IND
I2SWS_IND
AUDIO_R_OUT
P.CON+9V
AUDIO_L_OUT
P.CON+9V
GND
+3.3V
+2.5V_IO
H-10
H-9
PCBDH0
CEF276
(DIGITAL PCB)
AV OUT SCHEMATIC DIAGRAM
9.0
FROM/TO POWER3
FROM/TO AV SWITCH/JACK
NC
NC
NC
6.0
6.0
6.0
6.0
6.0
5.9
0
+
-
VCC
A_GND
-
+
FROM/TO INTERFACE HDMI IC
FROM/TO SOUND
(13/14 VIDEO ENCODER)
Y/CBVS
C
(I2SSD_OUTB)
(I2SOSCK_OUTB)
(I2SCLK_OUTB)
(I2SWS_OUTB)
(I2SSD_OUTA)
(I2SOSCK_OUTA)
(I2SCLK_OUTA)
(I2SWS_OUTA)
AUDA_01P
I2SWS_IND
I2SSD_IND
I2SSCK_IND
VSSR_AUDB
VDDR_AUDB
VSSR_AUDA
VDDR_AUDA
I2SWS_INC
I2SSCK_INC
I2SSD_INC
AUDB_02N
AUDB_02P
AUDB_01N
AUDA_02N
AUDA_02P
AUDA_01N
AUDB_01P
3.4
3.4
3.4
3.4
SPDIF_OUTA
3.3
VSS2DI
VDD2DI
VSS1DI
VDD1DI
A2VSSQ
A2VDDQ
A1VSSQ
A1VDDQ
A2VSSN
A1VSSN
A2VDD
A1VDD
RSET
R2SET
R
B
G
VSYNC_OUT
HSYNC_OUT
2.5
0
2.5
0
2.5
0
2.5
0
2.5
0
2.5
0
0
0
0
0
0
0
0
0
0
0
0
0
3.3
3.3
3.3
3.3
0
3.3
0
0
0
0
0