Sharp ER-A570 Service Manual Download Page 59

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12. Circuit diagram

RCS

MAC

AB8

AB7

AB0

AB1

AB4

AB5

AB2

DH6

DH5

DH3

DH0

RCV

RDY

EMP

100

AB9

BREQ

AB11

AB12

AB17

AB13

AB14

AB15

AB16

DCD

DAK

AH1

RDH

AH0

UCS

WRH

SIN

AEN

SRE

AB10

HRQ

IOR

IOW

AB18

RTS

HLDA

C24

AST

GND

VCC

TRR

TRV

CS0

VCC

GND

AEN

TXE

HLDR

RCS

DAC

R12

+5V

103 x

R48

EAD

R46

R11

DAK

AH1

RDH

AH0

WRH

SIN

SRE

R39

10K

R49

R41

R44

10K

)

103

R10

DH0~

DH7

10K

R22

10K

R42

BAC

-A

4  16

Summary of Contents for ER-A570

Page 1: ...I TEST FUNCTION FOR ER A6IN AND ER A5RS 3 1 IV HARDWARE DESCRIPTION FOR ER A6IN AND ER A5RS 4 1 PARTS GUIDE CONTENTS SHARP CORPORATION This document has been published to be used for after sales service only The contents are subject to change without notice Parts marked with is important for maintaining the safety of the set Be sure to replace these parts with specified ones for maintaining the sa...

Page 2: ...erved 1 Download the data from the ER 02FD onto the ECR using the SRV 998 2 Execute the SRV RESET operation 3 Execute either the INLINE RAM CLEAR operation 899 or the INLINE SET UP 1 JOB operation 895 4 Check the SRV 970 to see if the ECR memory capacity exceeds the packaged RAM memory capacity If it does add an optional RAM and follow the same procedure all over again from step 1 ...

Page 3: ...e on virheellisesti asennettu Vaihda paristo ainoastaan laitevalmistajan suosittelemaan tyyppiin Hävitä käytetty paristo valmistajan ohjeiden mukaisesti French ATTENTION Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du même type ou d un type recommandé par le constructeur Mettre au rébut les batteries usagées conformément aux instru...

Page 4: ... CHAPTER 3 TRANSMISSION SYSTEM SPECIFICATIONS 1 3 CHAPTER 4 FILE DATA ALLOCATION IN THE IN LINE SYSTEM 1 6 CHAPTER 5 PROGRAM DATA UPDATING 1 6 CHAPTER 6 SRV MODE PROGRAMMING 1 8 CHAPTER 7 PGM2 MODE PROGRAMMING 1 14 CHAPTER 8 TROUBLESHOOTING JOBS 1 16 CHAPTER 9 READING X AND RESETTING Z REPORTS 1 17 CHAPTER 10 SOFTWARE INSTALLATION PROCEDURE FOR IN LINE SYSTEM 1 19 CONTENTS 1 1 ...

Page 5: ...nits are required to complete the master system configuration The master may require additional RAM for allocating the IRC files 1 ER A6IN SRN I F control board 2 ER 01RA Option RAM chip 32KB ER 02RA Option RAM chip 128KB ER 01MB Option RAM board Max 512K bytes ER 02MB Option RAM board 1M bytes 3 ER A57R1 Option device control ROM 1 chip The ROM chip ER A57R1 is installed on the main PWB of ER A57...

Page 6: ... 1 Topology Common Bus System 2 Coaxial cable RG 58 u 3 Transmission Speed 480KBPS 1MBPS Selectable SRV mode JOB 922 4 Data Transfer Method Packet data transfer method Data side of 1 paket is MAX 270 Byte 5 Maximum Length of Transmission Cable 1000m 3281 ft trunk cables branch cables however branch cable length is 10m 5m 2 for each terminal 6 Max Terminals 16 Terminals max 15 satellites 1 master 7...

Page 7: ... is not ready to receive data 5 Channel No Indicates that channel of the packet Channel 1 or Channel 2 6 Circuit status In the case of the NRDY packet it indicates why the NRDY packet was issued 1 Unable to handle received data because the receiving side is in the BUSY state 2 Unable to handle received data because the receiving buffer is full 7 Number of data bytes Indicates the number of bytes o...

Page 8: ...e range of 1 to 254 The number is specified in the PGM 2 mode at installation time It is necessary to specify an number for each device connected to the IRC including the master It should be noted that the IRC terminal number and the register number are not related Section 10 of this manual indicates how this number is specified IRC terminal number 3 digits max 000 254 000 OFF line machine Registe...

Page 9: ...ing file in the satellite is zero cleared before saving the data received from the master b When a preset file whose job number is 5000s is downloaded the contents of the corresponding file in the satellite is replaced by the preset file sent from the master Preset data Preset data Master Satellite SRN DEPT Preset totalizer consolidation receive save TRAN SACTION Preset totalizer consolidation rec...

Page 10: ...ram data on DEPT PLU a Down loading to all the satellites in the system NK2 Register No b Down loading to the satellite specified NK1 Register No NK2 Start code NK3 End code 2 Down loading of other program data a Down loading to all the satellites in the system b Down loading to the satellite specified NK1 Register No 4 Others 1 If a transmission error occurs the machine number of a satellite in w...

Page 11: ...izer on the clerk report 1 Inline 902 A No 0 Yes 1 1 Printing of text of a tied PLU in set PLU 2 Direct non tendering finalization after previous tender entry 3 Output of set PLU to KP 918 A Yes Disable By tied PLU 0 Set PLU s KP 1 Enable By tied PLU 2 Set PLU s KP 3 No Disable By tied PLU 4 Set PLU s KP 5 Enable By tied PLU 6 Set PLU s KP 7 1 Red color printing on KP when PLU s unit price is zero...

Page 12: ...ted in the back up master 2 The GLU finalization is executed in the satellite 3 The clerk system 920B Disable Enable Centralized 0 Individual 1 Disable Centralized 2 Individual 3 Enable Enable Centralized 4 Individual 5 Disable Centralized 6 Individual 7 1 Broadcast communication 2 PGM mode programming at the satellite 920 C Exist Disable 0 Enable 1 Nothing Disable 4 Enable 5 1 Machine assignment ...

Page 13: ...99 when consolidation daily total general resetting has not been taken 925 B 1 Any entry operation is inhibited until Job 199 is executed after consolida tion daily total general resetting has been taken 2 Various individal resetting 925 C 1 Report printing when consolidation daily and periodic total general reading or resetting is taken 1 Save file except for PLU 2 Locking after clerk resetting 3...

Page 14: ...al resetting Enable Disable The master alone can be made capable of resetting by selecting Disable When selecting Enable or Disable however the selection of the resetting method mentioned 1 above should well be noted 925 C 6 Type of printing of daily total and periodic total general X Z reports The following three types are available a Printing of only X Z reports on individual machines b Printing...

Page 15: ...l number of the master K P preset file and K P edit buffer is created The above jobs etc are performed c The above system requires the following se lection in programming JOB 920 D Register is standalone 0 11 898 M S Inline resetting Function This operation clears only the work memory for inline operations The program memory for inline operations re mained uncharged even after the resetting here i...

Page 16: ...eated When clerk file is centraized SIGN ON OFF CLERK file is created BACKUP MASTER MACHINE SRV 920 D 3 RECEIVE GLU BUFFER is created When clerk file is centraized SIGN ON OFF CLERK file is created When system report downloading job is possible on backup master consolidation file and the receive file is created All machine When the system has the save file the save file is created File area is shi...

Page 17: ...er to enable or disable the manager retry function when a transmission error occurs NK 0 Manager retry function ENABLE 1 Manager retry function DISABLE MRS 0 6 3650 M S Terminal number of K P K P Kitchine printer NK1 K P No 1 9 NK2 Terminal No 0 254 NK2 0 When the K P deletion 7 3651 M S Data transmission of K P NK1 K P No 1 9 NK2 8 3653 M S Second K P No NK1 K P No 1 9 NK2 Second K P No 1 9 NK2 0...

Page 18: ...aracter 10 3655 M S Print format for K P 11 3610 M S Inline preset reading 12 3650 M S Kitchen printer preset reading 3654 ST NK1 X TEXT X TL Space 3655 ABC X TL 0000 3610 X TL 3650 X TL A PLU DEPT code A C Amount C Print 0 Print 0 Skip 1 Skip 1 B Unit price B Print 0 Skip 1 1 15 ...

Page 19: ... file in use flag foreed to clear PGM2 M 4 5990 All item sales data memory manual clear PGM2 M S 5 5994 Clerk sales data memory manual clear PGM2 M S NK Clerk No 6 5996 Hourly sales data memory manual clear PGM2 M S 7 5997 Daily net sales data memory manual clear PGM2 M S 8 5700 Sign on clerk report PGM2 M S 5810 X TL 5820 X TL 5940 X TL 5990 X TL 5994 X TL NK 5996 X TL 5997 X TL 5700 X TL 1 16 ...

Page 20: ...ID Φ 1 x 31 COMMISSION SALES Φ Φ 1 x 32 TAX Φ Φ 1 x 32 CHIFF Φ 1 x 34 ALL CLERK Φ Φ Φ Φ 1 x 40 IND CLERK Φ Φ Φ Φ Φ Φ 1 x 41 4 HOURLY ALL Φ Φ 1 x 60 HOURLY RANGE Φ 1 x 60 2 DAILY NET Φ Φ 1 x 70 GLU Φ Φ 1 x 80 2 GLU BY CLERK Φ Φ 1 x 81 BALANCE Φ Φ 1 x 82 STACKED REP Φ Φ Φ Φ 1 x 90 1 x 91 Reset clear Φ Φ 1 x 99 1 X1 Daily X report Z1 Daily Z report X2 Preriodic X report Z2 Periodic Z report 2 The tim...

Page 21: ...40 4 IND CLERK Φ Φ Φ Φ Φ Φ 41 4 HOURLY ALL Φ Φ 60 HOURLY RANGE Φ 60 2 DAILY NET Φ Φ 70 GLU Φ Φ 80 2 GLU BY CLERK Φ Φ 81 BALANCE Φ Φ 82 STACKED REP Φ Φ Φ Φ 90 91 1 X1 Daily X report Z1 Daily Z report X2 Preriodic X report Z2 Periodic Z report 2 The time interval range or PLU code range can be specified by entering the start and end numbers according to the following procedure When specifying a sing...

Page 22: ...ETER DATA ALL PRESET DATA SRV 15 800 TL DOWN LOADING SRV PARAMETER 16 850 TL DOWN LOADING KEYBOARD PGM 17 4999 TL DOWN LOADING ALL PGM PRESETS 3 Set up 1 job operation 1 Satellite Jobs 902 920 899 and 3610 are auto matically programmed must do PGM JOB 2612 2 Master Jobs 902 920 899 3610 3611 and 4900 are automatically programmed must do PGM JOB 2612 3 Back up master Jobs 902 920 899 and 3610 are a...

Page 23: ...TER 2 COMPONENTS 2 2 CHAPTER 3 SPECIFICATIONS OF RS 232 INTERFACE 2 2 CHAPTER 4 BLOCK DIAGRAM AND SYSTEM CONFIGURATION 2 3 CHAPTER 5 SIGNAL CONNECTION DIAGRAM 2 3 CHAPTER 6 RS 232 PROTOCOL 2 5 CHAPTER 7 CONTROL SIGNAL SEQUENCE 2 12 CHAPTER 8 DATA BLOCK FORMAT 2 15 CHAPTER 9 RS 232 APPLICATION 2 15 CONTENTS 2 1 ...

Page 24: ...red in the market it allows the host computer to be connected to more than one ER A570 CHAPTER 2 COMPONENTS ER A5RS NO NAME PARTS CODE Q ty 1 PWB UNIT C PWB S 7 2 9 2 R C 0 1 1 2 BRACKET L A NG T 7 4 6 6 R C Z Z 1 3 SCREW FOR PWB AND BRACKET L X B Z 6 6 6 5 R C Z Z 2 4 SCREW FOR HOLDING OF THE PWB BRACKET AND BRACKET TO BRACKET L X B Z 6 7 7 4 R C Z Z 3 5 SCREW FOR HOLDING OF THE RS 232 CABLE CORE...

Page 25: ...e connection 2 Connection via modems a One to one connection 2 On line data communication and in line system connection The ER A6IN is required for the inline SRN system Satellite Host computer ER A570 The ER A57R1 and ER A5RS are Installed in ER A570 The same applies to the sample connections shown below MODEM NCU Satellite Host computer NCU MODEM To be procured in the market ER A570 MODEM NCU MO...

Page 26: ...CLEAR TO SEND FG FRAME GROUND SD 2 SD RD CTS RD 3 6 5 3 2 6 8 HOST 7 5 SG RTS 4 DCD 8 DTR 20 DSR 7 1 4 SATELLITE CTS SG RTS DCD DTR DSR 1 FG FRAME GROUND is connected to the shield of the cable 25PIN D SUB 9PIN D SUB SD SD RD SG RD 3 2 4 6 7 1 8 5 2 3 20 6 4 8 5 7 RTS DCD DTR DSR CTS CI 22 9 SG RTS DCD DTR DSR CTS CI FG 1 FRAME GROUND is connected to the shield of the cable MODEM TERMINAL 25PIN D ...

Page 27: ...tion with error if NAK is still received after the second resending of text block 9 Sends the next text if ACK is received and sends EOT and terminates the operation if data transfer is finaiized 2 Receives ENQ Check the terminal No to see if it is its own 3 Sends ACK 6 Receives text Checks the check sum text data etc And goes to 8 if there is no error in them 8 Sends ACK 10 Terminates the operati...

Page 28: ...ll received after the second resending of text block 9 Sends the next text if ACK is received and sends EOT and waits for ENQ 2 Receives ENQ Checks the terminal No to see if it is its own 3 Sends ACK 6 Receives text Checks the check sum text data etc And goes to 8 if there is no error in them 8 Sends ACK 10 Terminates the operation if EOT is received ENQ Host Satellite Dummy 3bytes Terminal No 6by...

Page 29: ... if NAK is received Resends text up to two times and performs error handling if NAK is still received after the second resending of text block 16 Sinds the next text if ACK is received and sends EOT and terminates the operation if data transfer is finalized Host Satellite EOT Continued from the preceding page Start code Text parameter End code Text DATA Two types of text block formats are availabl...

Page 30: ...es to 2 If the host has resent the text two times it sends EOT and goes to 0 ERROR END EOT The host goes to 0 ERROR END TEXT TIME UP Resends ID ENQ and then goes to 1 If the host has resent ID ENQ two times it sends EOT and goes to 0 ERROR END Resends the text and then goes to 2 If the host has resent the text two times it sends EOT and goes to 0 ERROR END KEY ENTRY Sends ID ENQ and goes to 1 Time...

Page 31: ...ENQ resends ACK and goes to 4 After the host has received TEXT ignores the ENQ ACK NAK EOT The host goes to 0 ERROR END After the host has received TEXT goes to 0 Normal end After the host has received ENQ goes to 0 ERROR END The host goes to 0 ERROR END TEXT The host checks the text block if the block is correct the host sends ACK and goes to 4 If it is not correct the host sends NAK and goes to ...

Page 32: ...e has received TEXT ignores the EOT Satellite goes to 0 ERROR END TEXT Satellite checks the text block if the block is correct Satellite sends ACK and goes to 1 If it is not correct satellite sends NAK and goes to 2 If transmission cannot be continued satellite sends EOT and goes to 0 ERROR END Satellite checks the text block if the block is correct Satellite sends ACK and goes to 1 If it is not c...

Page 33: ...atellite goes to 0 ERROR END Time up is 7 seconds STATE After receiving text and sending ACK After sending ENQ After sending TEXT EVENT 3 4 5 ID ENQ ACK Satellite sends the text and goes to 5 Satellite sends the text and goes to 5 or sends the EOT and goes to 0 Normal END NAK Resends the text and then goes to 5 If satellite has resent the text two times sends EOT and goes to 0 ERROR END EOT Satell...

Page 34: ...D RTS CTS DSR DCD DTR CI 100ms 500ms DATA SD DTE DCE DATA RD RTS CTS DSR DCD DTR CI 100ms 500ms Note In the direct connect mode same as full duplex control but the CI signal is not controlled STARTED BY P C INITIAL CI SENSE CI ON DTR ON DSR ON FULL DUPLEX RTS ON LINE ESTABLISHED NO NO NO NO NO NO YES YES CI SENSE TIME OUT YES YES YES ERROR NO LINE DTR OFF Note The CI signal can be changed over whe...

Page 35: ...N FULL DUPLEX DCD ON CTS ON TIME OUT TIME OUT YES YES YES NO NO 5 sec YES YES YES YES YES NO 30 sec NO YES 7 sec TXRDY SEND 1 CHARACTER MORE TO SEND FULL DUPLEX WAIT 100ms FULL DUPLEX RTS OFF LINE ESTABLISHED DTR OFF RTS OFF TRANSMIT ERROR NO YES YES YES YES LINE ESTABLISHED RTS OFF 2 13 ...

Page 36: ...X TIME OUT TIME OUT SEND TEXT LINE ESTABLISHED DTR OFF RTS OFF RECEIVE ERROR AFTER RECEIVE ER OFF COMMAND NO NO NO NO NO NO NO YES YES YES YES YES NO YES YES YES YES ID ENQ ACK or NAK 4 sec TEXT 7 sec END CODE NAK BUFFER FULL LINE ESTABL DTR OFF RTS OFF DSR OFF INITIAL YES YES YES YES YES NO 30sec 2 14 ...

Page 37: ...preset 1 SRV programming JOB 945 MRS 0000 The assignment of RS 232 channel by each devices 945 A Channel No for ONLINE 0 to 7 945 B Not used Fixed at 0 945 C Not used Fixed at 0 945 D Not used Fixed at 0 When channel No is zero system is nothing Do not select the same channel number with two or more devices Use the switches on the I F board to set the channel No for the I F board connector Refer t...

Page 38: ...lf duplex system 1 JOB 6112 MRS 5 Programming of the transmission bau rate 6112 A Transmission bau rate Transmission bau rate 6112 A 300 bps 0 600 bps 1 1200 bps 2 2400 bps 3 4800 bps 4 9600 bps 5 19200 bps 6 JOB 6113 MRS 002013 Programming of the start and end code XXX Start code 02H STX YYY End code 0DH CR JOB 6110 Online preset reading TL 6111 AB 0 X TL 6112 A 0 X TL 6113 XXXYYY 0 X TL 6110 X 2...

Page 39: ...nel 4 check 505 RS 232 channel 5 check 506 RS 232 channel 6 check 507 RS 232 channel 7 check 2 Inline I F check JOB CODE Contents 600 IRC TEST 1 601 IRC TEST 2 602 IRC TEST 3 603 IRC TEST 4 DATA transmission test SATELLITE setting 604 IRC TEST 5 DATA transmission test MASTER setting CHAPTER 5 Cautions Options should be installed with the power supply turned off When setting the RS232C channels avo...

Page 40: ...er switch on the I F board must be switched to the software control side Check 2 Data transfer check SDn RDn loop check In this check transfer 256 byte loopback data of 00 FF Note The above check should be made with the baud rate set at 9600BPS Check 3 Timer check Before making check 2 set the corresponding timer at 10ms for RCVDT activation and check to see that 1 TRQ1 is not generated during the...

Page 41: ...n error occurs b2 An overrun error occurs b3 Abnormal data number transmitted by DMA b4 Abnormal data number received by DMA b5 Data transmitted by DMA are difference from data re ceived by DMA b6 n unexpected interruption is made b7 An error occurs Always 1 when in error print δ Error print by diag 5 command The table below shows the names of the signals to be checked and their directions Signal ...

Page 42: ...the inline setting in the following proce dure before performing this test To cancel the inline setting XXX Set as required When testing an already configured system cancel the inline set ting of the set which are not to be tested in the above procedure or disconnect their signal lines Disconnect the inner cable and the joint connector If the test is executed without cancelling the inline setting ...

Page 43: ...r The sequence No of the received data is displayed on the 7SEG DISPLAY of the satellite c The master receives the data and then checks the sequence No and 0AAH data If there are two or more satellite machines steps a and b are repeated If all data sent from the satellite are normal the master increments the sequence No The above steps a through c are repeated Test data format 1 packet 256 byte ZZ...

Page 44: ...n Signal name Input Output Description 11 VCC 5V 12 D2 I O Data Bus D2 13 D7 I O Data Bus D7 14 D0 I O Data Bus D0 15 D1 I O Data Bus D1 16 INT In Interrupt 17 NMI In Non Maskable Interrupt 18 HALT Out HALT 19 MREQ Out Memory Request 20 IOREQ Out I O Request 21 RD Out Read 22 WR Out Write 23 BUSAK Out Bus acknowledge 24 WAIT In WAIT 25 BUSRQ In Bus Request 26 RES In Reset 27 M1 Out M1 cycle 28 RFS...

Page 45: ...collision detect unit Fig 6 a Modem circuit The transmission data input from the ADLC are PE modulated phase encoding modulation the circuit to be output to the transmission driver and the reception data input from the trans mission receiver are demodulated and produced at the ADLC b Collision detect circuit The data transmitted from the home station is received and detects a collision on the tran...

Page 46: ...ub 43 DRQWS Sub Out DMA request write to sub 44 RDH Host In Read from Host 45 WRH Host In write from Host 46 INTH Host Out Interrupt to host 47 DAK Host In DMA acknowledge from host 48 TCH Host In Terminal count from host 49 DRQWH Host Out DMA request read to host 50 DRQWH Host Out DMA request write to host 51 CS Host In Chip select from host 52 VSS GND 53 N U 54 DB0 Host I O Data bus 55 DB1 Host ...

Page 47: ...RQWH DMA request write to host Output Pin 50 Not used 9 TCH Terminal count from host Input Pin 48 Not used Φ INTH Interrupt to host Output Pin 46 An active low signal which is used to inform the interrupt signal that the controller has the information to read or write Γ RES Reset Input Pin 35 Asynchronous reset signal from the host which is used to reset registers within the controller HOST read t...

Page 48: ...AK3 and is used for DMA control of transmission data Λ DRQRS DMA request read to sub CPU Output Pin 42 An active low DMA request to the sub CPU to read data which is normally connected to the DMA controller of the sub Μ DRQWS A request to write to sub CPU Outut Pin 43 An active low DMA request to the sub CPU to write data which is normally connected to the DMA controller of the sub CPU Ν TCS Termi...

Page 49: ...gnal input from the link controller ADLC normally COL Collision detect signal Input Pin 65 To avoid collision on the line the data sent from this side are compared with the data on the line In other words when the data sent are equal to the on line no collision is assumed existing If not equal an occurrence of data collision is assumed This line is therefore the input of the data sent from this si...

Page 50: ...rarily stored in the CPU s internal register before being written into an I O device at the next step In contrast the DMA controller allows data to be directly transferred between memory and I O devices without the CPU See Fig 22 Fig 22 The DMAC 8257 permits data transfers only between memory and I O devices Some type of DMACs allow data transfer between memories CLK TC TWH TWL Φ AEN AST D0 D7 A8 ...

Page 51: ... bus and outputs the transfer data address and RD signal to place the transfer data onto the data bus At this point the DMAC issues a DAK DMA Acknowledge to the I O device to let to the I O device read the memory data on the data bus The above sequence is repeated until a single DMA cycle is completed On this board DMA transfer is performed between the ADLC and memory and between memory and MB62H1...

Page 52: ... a strobe which is used to write the upper byte of memory address from the data bus into the µPD8212 9 AEN Address Enable Output This pin is used to set the address and control bus outputs of the Z 80 CPU to high impedance if needed It may also be used to disable the system address bus by using the enable input of the address bus driver within the system This is to disable any response from non DM...

Page 53: ...l Count Output The TC output Indicates to the currently selected I O device that the current DMA cycle is the last cycle of the data block If the TC stop bit of the Mode Set register is set the selected channel will be automatically disabled at the end of the DMA cycle The TC signal is output when bit 14 of the TC register on the selected channel is reset to zero The value n 1 must be loaded in th...

Page 54: ... if this input is Low and the Enable input is High Chip Select Input In 10 11 RS0 RS1 Register Select inputs These inputs are used with the R W input CR1b0 to address a register within the device for read write access Register Select Input In 12 R W Read Write Control input used to indecate tha direction of the data flow The Data I O buffer is placed in the Output mode if this input is High it is ...

Page 55: ...cted causing the hardware to return to the Off Loop If the RESET input is set Low CR3b5 is set to zero Non Loop Mode which sets CR3b7 to zero As a result this pin issues a High level signal Loop On Line Control Data Terminal Ready Output Out 28 CTS Clear to Send input Setting this pin to High disables ST1b6 and related IRQ If SR1b4 is set and this pin is enabled an IRQ is issued Low to High transi...

Page 56: ...w it is turned off When hte RTS is set Low transistor Q1 turned on through an inverter which applies a bese current to Q2 turnit it on When Q2 and pins 10 and 9 of IC7 are turned on the output transistors IC7 pins 6 and 5 are turned on Since the output trasistors are common emitter circuit data 1 is obtained at LINE Fig 28 2 Receiver The receiver provides the following two functions 1 Data recepti...

Page 57: ...wo stages of the dta packet and response packet to prevent the collision of the response packet This permits higher efficiency for heavy loads Collision detect circuit is located within the MB62H149 custom LSI 10 Carrier detect circuit This circuit detects whether data is flowing on the transmission line It consists of a circuit which immediately senses a no data status on the line Fig 30 When dat...

Page 58: ...eceiver terminal the transmitter terminal s output waveform is subject to attenuation and distortion due to the length of the trunk cable this depends on the characteristics of the cable itself Fig 9 Example of distorted signal waveform at the receiver terminal RG58 U 400m With the receiver terminal adjust VR1 5kΩ on the ER A6IN board until the waveform as shown in Fig 10 is obtained at TP pin 1 o...

Page 59: ...8 AB11 97 AB12 96 95 94 AB17 93 AB13 92 91 1M 90 89 88 AB14 87 AB15 86 AB16 85 83 82 CTS 81 DCD 31 32 DAK 33 AH1 34 RDH 35 AH0 36 UCS 37 WRH 38 SINT 39 40 41 AENH 42 SREST 43 AB10 44 HRQ 45 IORD 46 IOWR 47 AB18 48 CI 49 RTS 50 HLDAK D0 D1 D2 D3 D4 D5 D6 D7 NC C26 C25 C24 ASTB X1 X2 GND VCC TRRQ TRV CS0 P0 VCC GND AEN TXE HLDRD OPC1 IC16 RES OPTCS DB0 7 TCH SRCS DACK2 RSRQ POFF TRQ1 WRO TRRQ AB0 23...

Page 60: ...1 19 A4 18 A5 17 A8 16 A9 15 A10 14 A15 3 IOREQ 4 MREQ 5 RDS 6 WRS 7 INTS 24 MWR 80 MSK 79 RS0 78 RS1 76 LCS 75 IRQ 74 E 72 TXD 71 TXC 70 RXD 32 D0 31 D1 30 D2 29 D3 28 D4 27 D5 26 D6 25 D7 11 MRQ 8 Φ 35 RES 37 IO RD 22 DAK01 36 IO WR 13 WATI 21 A0 61 DB7 47 DAK 48 TCH 49 DRQRH 50 DRQWH 46 INTH 64 AB1 62 AB0 65 CDL 66 RDI 67 TDI 1 CLK 9 TM0 10 TM1 68 RTS 69 RXC IC5 M862H149 NC 2PIN 23PIN 63PIN 77P...

Page 61: ... 29 64 24V 24V 30 65 A2 A1 31 66 RES A0 32 67 AS RESET 33 68 NU2 OPTCS 34 69 GND GNDP 35 70 GND GNDP No No SIGNAL SIGNAL 1 36 GND GND 2 37 GND GND 3 38 4 39 φ RDO 5 40 NU1 WRO 6 41 5V BREQ 7 42 5V BACK 8 43 TRQ2 A23 9 44 TRQ1 A22 10 45 EXINT1 A21 11 46 EXINT0 A20 12 47 TRRQ A19 13 48 RSRQ A18 14 49 RFSH A17 15 50 IPLON A16 16 51 D7 A15 17 52 D6 A14 18 53 D5 A13 19 54 D4 A12 20 55 D3 A11 21 56 D2 A...

Page 62: ...13 PWB layout 1 Parts side 4 19 ...

Page 63: ...2 Solder side 4 20 ...

Page 64: ...MP is excluded RSRQ TRRQ Not used For RS 232 For simple IRC 4 Simple IRC send receive control UNIT3 only Not used 2 Pin configuration CS1 CS2 A0 A5 R W RDO WRO DB0 7 OPTCS INT D0 D7 RES RES POFF CLOK RSRQ TRQ1 AB0 1 DCD1 2 CI1 2 RCVDT1 2 CTS1 2 USART DSR1 2 RS 232 Reciever DTR1 2 TRNDT1 2 CD1 2 CI1 2 RD1 2 CS1 2 DR1 2 ER1 2 SD1 2 RS 232 Driver RS1 2 Power supply circuit 12V 12V RTS1 2 OPC1 PX 24V ...

Page 65: ...ol CHSL PX TO FROM USART RXDATA0 TXE X1 X2 XOUT TBCK Inline cont OCS TCR0 Timer0 control Timer0 RCVDT0 TCR1 Timer1 control Timer1 RCVDT1 TCR2 Timer2 control Timer2 RCVDT2 TCR3 Timer3 control Timer3 RCVDT3 RTS CNT RTS1 RTS0 POFF RSRQ TRRQ TRQ1 TRQ2 Power supply cont RCVRDY3 RCVRDY2 RCVRDY1 RCVRDY0 TRNEMP3 TRNEMP2 TRNEMP1 TRNEMP0 Interrupt control CI0 CI1 CI2 CI3 P2I CD0 CD1 CD2 CD3 P0 CTS0 CTS1 CTS...

Page 66: ...l CI input 26 45 CI1 I IS CI2 27 87 CI2 I IS GND 28 99 CI3 P2I I IS GND RS 232 CI INLINE P2I 29 55 BRK0 I ISC BRK1 RS 232 USART BREAK signal 30 70 BRK1 I ISC BRK2 31 27 POFF I IS POFF POFF signal LOW P OFF HIGH P ON 32 4 BRK3 I IS GND RS 232 INLINE USART BREAK signal 33 57 RCVRDY0 I ISC RCVRDY1 RS 232 USART RCVRDY signal 34 72 RCVRDY1 I ISC RCVRDY2 35 74 RCVRDY2 I ISC GND 36 6 RCVRDY3 I IS GND RS ...

Page 67: ...AD signal from MAIN 80 30 WRO I I WRO WRITE signal from MAIN 81 9 RES I IS RES RESET signal from MAIN 82 34 R O O R READ signal To USART 83 37 W O O W WRITE signal To USART 84 51 RES O O RES RESET signal To USART 85 92 X1 O X1 Oscillation circuit 86 91 X2 I X2 87 53 XOUT O O XOUT Clock for USART 88 8 TRCK O O NC T R clock for 1CH USART 89 35 AB0 O O AB0 Address bus for USART 90 33 AB1 O O AB1 91 8...

Page 68: ...ation mode Data bit length 5 8 bits Character synchronization system Internal synchronization external synchronization Number of synchronized characters Single character double characters Parity occurrence and check parity valid invalid even parity odd parity Operations in the synchronization mode Overrun error and parity error detection Transmit receive buffer state acknowledgment Synchronization...

Page 69: ... O TRNRDY1 RS 232 data transmission enable signal 23 17 TRNRDY2 O TRNRDY2 24 29 BRK1 O BRK1 Break code detection signal 25 18 BRK2 O BRK2 26 30 CTS1 I CTS1 GND RS 232 clear to send signal 27 20 CTS2 I CTS2 GND 28 31 TRNEMP1 O TRNEMP1 RS 232 transmission buffer empty signal 29 21 TRNEMP2 O TRNEMP2 30 14 NC NC 31 24 NC NC 32 38 NC NC 33 48 NC NC 34 19 OPEN NC 35 43 OPEN NC 36 32 TRNDT1 O TRNDT1 RS 2...

Page 70: ...V and 12V are shut off It is provided for prevention from malfunction in the logic circuit when the 5V supply from mal function in the logic circuit when the 5V supply from the ER A550 main frame drops IC9 Not used 5 ER A5RS channel setting The ER A5RS ports can be set to channel 1 7 and invalid inhibit with SW1 on the PWB SW1 setting contents SW1 1 3 are used for channel setting of RS 232 connect...

Page 71: ... 17 18 19 20 21 22 23 24 NC NC NC 36 35 34 33 32 31 30 29 28 27 26 25 NC NC RES RTS1 DSR1 RST CLOCK TRNDT1 TRNEMP1 CTS1 BRK1 TRNRDY1 RCVCLK2 DTR2 RTS2 DB4 DB5 DB6 DB7 TRNCLK1 W CS1 RSLCT0 R RCVRDY1 RSLCT1 CS2 RCVDT2 NC TRNCLK2 RCVRDY2 TRNRDY2 DRK2 CTS2 TRNEMP2 TRNDT2 OPEN DSR2 48 47 46 45 44 43 42 40 39 38 37 41 NC GND RCVDT1 DB3 DB2 OPEN DB1 DB0 VCC RCVCLK1 NC DTR1 NC NC NC 5V IC MB89371A 79 80 S...

Page 72: ...3 68 NU2 OPTCS 34 69 GND GNDP 35 70 GND GNDP No No SIGNAL SIGNAL 1 36 GND GND 2 37 GND GND 3 38 4 39 φ RDO 5 40 NU1 WRO 6 41 5V BREQ 7 42 5V BACK 8 43 TRQ2 A23 9 44 TRQ1 A22 10 45 EXINT1 A21 11 46 EXINT0 A20 12 47 TRRQ A19 13 48 RSRQ A18 14 49 RFSH A17 15 50 IPLON A16 16 51 D7 A15 17 52 D6 A14 18 53 D5 A13 19 54 D4 A12 20 55 D3 A11 21 56 D2 A10 22 57 D1 A9 23 58 D0 A8 24 59 POFF A7 25 60 VRAM A6 2...

Page 73: ...7 PWB layout 4 30 ...

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