DV-L70U
9-11
Pin No.
Pin name
Type
I/O
Function
122,123
GPAI/O [1:0]
3-S
I/O
General purpose bidirectional pin for monitor and control with ADP microcode.
After resetting, this pin is defined as the input. If ADP command is used, setting is possible.
2
GPSI
I
I
General purpose input for monitor with DVP microcode.
159
GPSO
O
O
General purpose output for control with DVP microcode.
129
GCLK
I
I
27,000MHz clock or crystal input for main processor
126
GCLK1
I
I
27,000MHz master clock input for audio. It must be connected to GCLK during ordinary
operation.
128
XO
O
O
Output to crystal connected to GCLK. If crystal is not used in GCLK, XO is not connected.
136
PLLCA
Capacitor connection pin for PLL. Connect 47nF capacitor. Connect the other terminal
of the capacitor to PLLGND.
137,135
PLLCFG [1:0]
I
I
PLL configuration input. Change is possible during reset only. In the normal use, both pins
must be connected to (digital) GND.
In the 16-bit video mode (Video8 = 0), the line becomes the luminance output.
92, 94~97,
Y [7:0]
3-S
O
In the 8-bit mode (Video8 = 1), it becomes the luminance/color difference output
99~101
which is timely multiple-processed according to ITU-R656 standard (regardless
whether SAV, EAV sync code is present or not).
102,
C [7:0]
3-S
I/O
In the 16-bit video mode (Video8 = 0), the line becomes the color difference output.
104~107,
In the 8-bit mode (Video8 = 1), the pin 3 (C[7:5]) of m.s. line is not used, and 1.s.5 pin
109~111
(C[4:0]) is specified as the input which is received from the external OSD device.
OSDPEL[3:0]
OSD pixel input. The four signals are used as the entry to on-chip OSD pallet.
(C[3:0])
On-chip OSD pallet selector. OSDPallete0 is selected for the low level, and
OSDPLT (C[4])
OSDpallete1 is selected for the high level.
124
VCLKX2
3-S
I/O
Main video clock input or output. 27,000MHz
84
VCLK
3-S
I/O
VCLKx2 signal is divided into two parts. The signal is used as the qualifier of the data
and sync signal.
90
HSYNC
3-S
I/O
Horizontally sync bidirection signal pin. The polarity and length are programmable.
89
VSYNC
3-S
I/O
Vertically sync bidirectional signal pin. The polarity and length are programmable.
91
FI
3-S
I/O
Field identification bidirectional signal pin. The polarity is programmable.
88
CBLANK
O
O
Composite blank output. The waveform including the polarity is programmable.
Video master/slave selection input. For the high level, the video synchronization of
MD36710X goes into the master mode. (Accordingly, the video SYNC signal and
85
VMASTER
I
I
clock are output.)
For the low level, the video synchronization goes into the slave mode. (Accordingly,
the video SYNC signal and clock are input.)
Only in the reset mode, the setting of the terminal can be changed.
Video enable input (active low). When it is active, MD36710X outputs the video data.
87
VDEN#
I
I
When it is deasserted, the pixel output goes into the 3-state. (However, the sync
signal and clock are kept to be active.)
Though this input can be changed at any time, it is valid at the following VCKx2 time.
132
AMCLK
3-S
O
Audio master clock input/output. The sampling frequencies of 384fs, 256fs, 192fs
and 128fs can be selected (programmable).
117
S/PDIF(AOUT[3])
O
O
S/DDIF transmitter output. Moreover, it can be connected to DAC as the 4th audio
output (AOUT[3]). After resetting, the pin outputs the low level.
116~114
AOUT [2:0]
O
O
Serial output of PCM stereo audio for DAC. After resetting, the pin outputs the low
level. Only for AOUT[0], the sample width of 24 bits is supported.
112
AIN
I
I
Serial input of PCM stereo audio for ADC.
LR clock output of AOUT[3.0] and ATN. For the sampling frequency, it is a rectangular
118
ALRCLK
O
O
wave.
The polarity of LR is programmable.
Bit clock output of AOUT[3.0] and AIN. AOUT is output at the rise/fall edges of the
119
ABCLK
O
O
clock (programmable), and AIN is latched.
GPI/O signal (4-pin)
PLL signal (6-pin)
Digital video port (24-pin)
Digital audio port (8-pin)
