SD-AT1000W
– 32 –
Figure 32 SCHEMATIC DIAGRAM (3/11)
A
B
C
D
E
F
G
H
1
2
3
4
5
6
• NOTES ON SCHEMATIC DIAGRAM can be found on page 11.
+5V(A)
+5V(D)
100P(CH)
100P(CH)
100P(CH)
3.3K
100P(CH)
3.3K
3.3K
1.2K
1.2K
1.2K
4.7/50
DZ5.6BSB
470
0.001
0.01
0.0022
DS1SS133
DS1SS133
0.1
150
150
3.3/16
10/16
4.7
0.1
0.1
47K
KRA107 S
1K
1K
DS1SS133
10/16
SI3050LUS
3
1
1
0.1
DS1SS133
0.001
1
2.2/50
10/16
1
0.1
0.1
1
0.1
100
100
4.7
2.2
15K
18K
1
0.1
0.1
AK4586VQ
44
43
42
41
40
39
38
37
36
35
34
22 21 20 19 18 17 16 15 14 13 12
1
0.1
47K
8
7
6
5
4
3
2
1
47K
2
11
10
9
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
OVF
COD_DO
COD_DI
COD_CLK
COD_CSN
DSP_SCCLK
DSP_CS
DSP_SCDIN
DSP_SCDOUT
DSP_RESET
DSP_INTREQ
DB
NONPCM
COD_CSN
COD_DO
D_+5V
A_GND
A_+9V
LOUT3
ROUT3
LOUT2
ROUT2
LOUT1
ROUT1
LIN
RIN
DGND
PROTECT
NONPCM
COD_CLK
OVF
COD_DI
PROTECT
EX_CLK
MCLK
LRCK
AUDATA0
SCLK
SDATA1
AUDATA2
AUDATA1
GND(A)
GND(D)
GND(A)
VCC
GND
3Y
3A
2Y
2A
1Y
1A
CHASSIS
1
2
ADC/DAC/DIR
CONVERTER
PVDD
R
PVSS
RX4
SLAVE
RX3
TST
RX2
I2C
RX1
CAD0/CSN
SCL/CCLK
SDA/CDTI
CAD1/CDTO
INT1
INT0
MCKO
TX
XTI/EXTCLK
XTO
DZF2/OVF
VCOM
VREFH
AVDD
AVSS
DZF1
LIN
RIN
ROUT1
ROUT2
ROUT3
LOUT3
LOUT2
LOUT1
PDN
DVSS
DVDD
TVDD
SDTO
SDTI3
SDTI2
SDTI1
LRCK
BICK
15
14
12
11
10
9
8
7
6
5
4
3
2
1
13
15
1
CNP702
P35 12 - D
TO DISPLAY PWB
1
3
2
13
12
11
10
9
8
7
6
5
4
3
2
1
P30 1 - C, E, G
TO MAIN SECTION
MAIN PWB-A1 (2/2)
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+
+B
+B
0.0022
DIGITAL IN
MUTE
IC110
VOLTAGE
REGULATOR
R141
C148
C117
C144
D103
R197
R198
R199
C109
C111
C110
IC102
C113
C146
R129
R130
R149
C120
IC109
C132
C153
ZD102
C133
R144
R147
R146
C199
RX101
OPTICAL
DIGITAL IN
R150
C136
R138
Q102
C115
C164
R134
C149
C147
C114
C145
R128
R127
C112
C116
C196
C195
C194
R196
R193
R195
R194
C165
C168
C169
D107
D106
R151
C123
R139
D104
C166
R133
CNP502
FFC702
VOLTAGE
REGULATOR
IC109
TC7WU04U
DUAL2-INPUT
NAND GATE
BUFFER
AMP.
C170
FM SIGNAL
Summary of Contents for CP-AT1000WC
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