-
CE-1600E
9. Description of each block
9-1.
LR38045 gate array
Table-1 describes the gate array internal blocks and port addresses
(see block diagram [Fig.2]).
Block name
Description
Bu
Bidirectional 8- bit 10 buffer.
(8-bit
inputoutput buffer)
Mu
Data i1 FF1, FF2, FF3, or PA Port are sent from
(Multiplexer)
the gate array.
FF1-FF3
FF1: FF1 output
is
used to control the interrupt
(8-bit latch)
circuit. For instance, '1' in a bit
FF2:
FF3:
DC1-3
DC1: 32KB ROM c~
select (CSNO)
(Decoder)
DC2: 2.5' FDD select signal (I07N)
DC3: FF1- - - FF3 and FDD reset latch select
during data write.
FF1- - -FF3 and PA port select during
data read.
INT
Ths signal
is
OOedwi1ha PA POrt (PAOI- - -61)
(Interrupt circuits)
i1put to be sUppliedto IRQas an
nternet
signa,
As PA01---61
correspond wi1h 00---06
of
FF1, the interrupt becomes valid when '1'
is
established for FFI.
(The interrupt equivelent circuit is shown in
[Fig.3J. )
, RO
.
ri
~
~
I~
OO~
PAO
I
0'
~
PA I J
02
PA2 I
OS
V"
PA3t
O'
"""
PA.
I
Q5
PAS I
Q6
A.
PA61
'--
?1",+-tv'J
-t'"
[Fig.3J Interrupt circuit
RST
An input of the reset signal on RSTI resets
(Reset circuit)
FF1- - -3.
At the same time, RSTN is issuedto
the 2.5" FDD reset line and remains issued until
the reset signa is canceled soltwarewise.
It is
possble
to output RSTNsoftwarewiserrespecti
ve of the i1put to RSTI.
Reset eQuivaientcircuit is sOOwnin [Fig,4] andits
timings in [Fig. 5], )
-4-
Block name
Description
{VCC~
Reset line capacitor
/'
RST'
~
.P""'~J~"OO
::.~
RSTN
'RESET
SW
'';TE.
IlI>Il·~'
I ;
t>
1
I
(PC-1600J:1)
:0
.FFI-3RESET'
'----
---
-----
-
-----
------]
[Fig.4] Reset circuit
W-, Tt_
Reset signal, ~
F~'~~
sv ~
'----v-------
FD resets softwarewise
[Fig.5] Reset circuit timings
NOTE: Port PA, PB, PC are all active high inside the gate array,
but converted into active low outside the gate array (see
the figure below).
Gate array
,
Inside , Outside
PA
PB
ACTIVE
HIGH
ACTIVE
LOW
For instance, "1" on 00 of FF2 sets the PBON output low.
