– 33 –
CD-BA160H/1700H
7
8
9
10
11
12
Figure 33 SCHEMATIC DIAGRAM (10/10)
R16
10K
L61
0.82
µ
H
R87
120
C56
330/6.3
C64
0.47/6.3
ZD61
DZ3.9BSB
R94
10K
R95
10K
CNP11
C36
8.2P
C35
8.2P
C83
0.022
R84
10K
C40
0.0015
C43
0.0015
R83
10K
C34
0.022
CNP12
R82
2.2K
R81
2.2K
R17 1K
D21
DS1SS133
R21
470
R22
470
D22
DS1SS133
1
R46 1K
R45 1.2K
R40 1.2K
C80
0.1
R73 1K
R71 1K
C72 0.01
R72 1K
C71 100P
C73 100P
C75 100P
C76 100P
C77 100P
C78 100P
R75 1K
R76 1K
R77 1K
R78 1K
C74 100P
R74 1K
L62
2.2
µ
˙
CNP5
R19
47
C38
10/16
C39
10/16
C47
100/16
CNP4
C41
100/10
R8
330
R10
27K
C26
0.047
C22
100P
R80
1M
R79
1.5M
C24
2.2/50
C21
0.1
C23
0.047
R12
680
R35
1K
R39
470
R38
270
R20
220
XL1
16.934MHz
C45
100/10
C44
0.1
C31
100/10
R14
1.2K
R11
12K
R13
680
C81
0.022
C27
0.1
C28
47/10
2
022
R44
1K
IC2
LC78641E
SERVO/SIGNAL
CONTROL
80 79 78 77 76 75 74
73 72 71 70 69 68 67 66 65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R58
220
C30
0.1
R15
10K
C29
0.1
C42
68P
C25
.1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
O/C
DISC_NO
TDO
DISC_NO
RES
WRQ
CE
DO
CL
DI
DRF
INT
SLDO
SPDO
FDO
INT
DRF
WRQ
CE
DO
DI
CL
RES
O/C
EFBL
O
CD-BA1700H ONLY
DIGITAL OUT
DGND
5V
+5V
DGND
AGND
L-CH
R-CH
DRF
SW3
DISC
NUMBER
SW2
CLAMP
M-
CONT7
CONT6
GND(D)
M-
M+
GND
CD RES
DI
CLK
DO
CE
WRQ
CDINT
CLAMP SW
PCKIST
TEST
DOUT
VDD
C2F
PCK
FG(D_Vref)
SLDO
SPDO
FDO
TDO
TBLO
BHREF
PHREF
ADAVSS
ADAVDD
VREF
TE
FE
PH(RFENV)
BH
JITTC
JITTV
EFMIN
SLCO
SLCIST
HFL
FR
VVDD
VVSS
PDO2
PDO1
EMPH
MUTEL
MUTER
LVDD
LCHO
XVDD
LVSS
RVSS
RCHO
RVDD
XIN
XOUT
XVSS
ASLRCK
ASDACK
ASDFIN
LRSY
DATACK
DATA
16M
SFSY
SBSY
PW
SBCK
CE
CL
DI
DO
WRQ
RES
DEF
VDD5V
VSS
V/P
FSEQ
DEFECT
EFMO
M+
M3
LOADING
MOTOR
SW1
OPEN/
CLOSE
M
+
-
10
9
8
7
1
2
3
4
5
6
3
2
1
1
2
3
4
5
1
2
3
4
5
6
6
5
4
3
2
1
5
4
3
2
1
NC
EFLG
FSX
CONT5
CONT4
CONT3
CONT2
CONT1
LASER
SERIAL
OUT
EXTERNAL
AUDIO IN
FILTER
DIGITAL
DAC
1BIT
LPF
DEEMPHASIS
ATTENUATION
MUTE
INTERPOLATION
OUT
AUDIO
ERROR
CORRECT
EFM
DECODE
DEFECT,
PROTECT
FRAME
SYNC
CONTROL
CLV
GENERATOR
CLOCK
GENERAL
CRC
DECODE
SUBCODE
INTERFACE
COMMAND
GENERAL
SW
PROCESSEROR
SERVO
ADJUST
AUTO
-
+
S/H
CONTROL
DEFECT
JITER
A/D
SW
CONTROL
LEVEL
SLICE
PLL
VCEC
DIGITAL OUT
DIGITAL
OUTPUT
PWB-A4
IC99
TOTX178A
OPTICAL
FIBER
DATA LINK
3
2
1
C98
0.022
C99
100/10
BI99
CNS99
CD-BA1700H ONLY
CNS402
P24 1-A
FROM MAIN PWB
P31 12-B
CNS701
FROM DISPLAY PWB
CD LOADING
MOTOR PWB-F
6
BI4
CNS4
D/A
2
3
Q2
KRC102 M
NC
NC
Q1
2SC3203 Y
CONSTANT
VOLTAGE
2
1
6
7
8
3
10
11
12
9
+B
+B
+B
+B
+B
+B
+B
INT
1
2
3
3
2
1
GND
+5V
13
IC99