Sharp AQUOS LC-37AD1E, Service Manual

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LC-37AD1E
Ë
HISDA5550M-1Y (ASSY:IC1601)
Teletext CPU
»
Block Diagram
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
99,1,3,4,2,100,
D0-D7
I/O
Data bus for external memory or data RAM.
98,96 97,94,93,89,86,84,
A0-A16
O
A
ddress bus for external program memory or data RAM.
82,79,81,83,90,85, 77,78,76,71,69 70,68,67
A17-A19/
I/O
After power-on P4.0,P4.1,P4.4 work as additional address lines A17
···
19.
P4.0,P4.1,P4.4
In port mode, these port lines act as bi-directional I/O port with internal pull-up resistors. Port pins that have '1' written to them are pulled high by the internal pull-up resistors and in that state can be used as inputs.
9,10,11,12,13,14,
P0.0-P0.7
I/O
Port 0 is a 8-bit open drain bi-directional I/O-port. Port 0 pins that have 1
15,16
written to them float: in this state they can be used as high impedance inputs.
41,42,43,44,45,46,
P1.0-P1.7
I/O
Port is a 8-bit bi-directional multifunction I/O port with internal pull-up resistors.
47,62
(PWM)
Port 1 pins that have 1 written to them are pulled high by the internal pull-up resistors and in that state can be used as inputs. The secondary functions of port 1 pins are: Port bits P1.0-P1.5 contain the 6 output channels of the 8-bit pulse width modulation unit. Port bits P1.6-P1.7 contain the two output channels of the 14-bit pulse width modulation unit.
24,25,26,27
P2.0-P2.3
I
Port 2 is a 4-bit input port without pull-up resistors.
(ADC)
Port 2 also works as analog input for the 4-channel-ADC.
31,32,33,34,35,36,
P3.0-P3.7
I/O
Port 3 is an 8-bit bi-directional I/O port with internal pull-up resistors, Port 3 pins
37,38
that have 1 written to them are pulled high by the internal pull-up resistors and in that state can be used as inputs, To use the secondary functions of Port 3, the corresponding output latch must be programmed to a one (1) for that function to operate. The secondary functions are as follows: · Alternate function P3.0: ODD/EVEN indicate output P3.1: external extra interrupt 0(INTX0)/UART(TXD) P3.2: interrupt 0 input/timer 0 gate control input)INT0) P3.3: interrupt 1 input/timer 1 gate control input)INT1) P3.4: counter 0 input(T0) P3.5: counter 1 input(T1) or In master mode HS or VCS output. P3.7: external extra interrupt 0(INTX1)/UART(RXD)
48,49
P4.2-P4.3(P4.7)
I/O
Port 4 is a bi-directional I/O port with internal pull-up resistors. Port 4 pins that have 1 written to them are pulled high by the internal pull-up resistors and in that state can be used as inputs. Secondary functions P4.2: RD, Read line. This signal is same as the to output of the pin RD available in some packages. P4.3: WR write line. This signal is same as the output of the pin WE, which is only available in some package.
5
XROM
I
This pin must be pulled low to access external ROM.
17
ENE
I
Enable Emulation Only if this pin set to zero externally, STOP and OCF are operational. ENE has an internal pull-up resistor which switches automatically to non-emulation mode if ENE is not connected.
18
STOP
I
STOP Emulation control line; Driving a low level during the input phase freezes the real time relevant internal peripherals such as timers and interrupt controller.
19
OCF
O
Opcode Fetch Emulation control line; A high level driven by the controller during output phase indicates the beginning of a new instruction.
20
EXTIF
21
CVBS
I
CVBS input for the acquisition circuit.
29
HS/SC
I
In slave mode Horizontal sync input or sandcastle input for display synchronization .In master mode HS or VCS output.
30
VS/P4.7
I/O
Vertical sync input/output for display synchronization. Can also be used as digital input P4.7. Furthermore this pin can be selected as an ODD/EVEN indicator alternatively to P3.0.
50
RST
I
A
low level on this pin resets the device. An internal pull-up resistor permits
power-on reset using only one external capacitor connected to Vss.