Sharp Aquos LC-30HV4U, Service Manual

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LC-30HV4U
LC-30HV4D
MAJOR IC INFORMATIONS
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IC2501 (MSP4448G)
IC for decoding audio signals.
It serves as an S-IF audio signal decoder and an audio data selector.
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IC2510 (IXA385WJ)
IC for controlling audio delay.
LC-30/37HV4U uses a frame buffer to process video signals. This results in a delay in outputting video signals.
The IC delays output of audio signals to synchronize output of video and audio signals.
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IC1301 (CXA2069Q)
7-input, 3-output selector.
This IC selects all audio and video signals received from input terminals and the tuner, except those signals
that relates to PC and components.
Video signals delivered to the IC are sent to Y/C separation circuits IC7001 (main) and IC402 (sub). Audio
signals are sent to the SR board via IC2501 (sound processor).
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IC1401 (MM1519XQ)
4-input, 3-output video selector for component input.
This IC receives AV1/3 sub component input signals, AV3 DV1 RGB input signals and C.C. (closed caption)
signals. Its output is for main, sub, component and C.C.
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IC1650 (Sil907)
Analog output TMDS receiver incorporating HDCP key.
This IC converts digital DVI-D signals into analog signals and supplies the analog RGB signals to IC1401.
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DVI1.0 compliant
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480P, 720P, 1080I supported
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10-bit DAC output
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Incorporated HDCP key
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IC1602 (Z86129S)
C.C. (Closed Caption) decoder.
This IC process the Vertical Blanking Interval (VBl) data from the image signal field in the data that matches the
transmission format defined per EIA-608.
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IC1601/1603 (Z86230S)
V-CHIP decoder.
This IC processes the extended data service (XDS) data in field 2 of Vertical Blanking Internal (VBl).
The XDS data is processed to define program blocking signals (PB) or restored XDS data packets.
The on-chip XDS filter in this IC allows only the XDS data packets to be restored and programmed.
The IC supports violence blocking and other XDS data service monitors (picture-in-picture).
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IC7001 (µPD64084)
This IC provides 3D processing of NTSC signals and thus high resolution Y/C separation of the main image
signals received from IC1301.
It incorporates a 4M-bit frame delay memory board and features one-chip 3D Y/C separation.
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Two operation modes available; dynamic image 3D Y/C separation mode and 2D Y/C sepa YCNR
mode
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Y coring circuit, vertical contour compensation circuit, peaking filter and noise detection circuit incorporated
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Power down mode available to minimize power consumption when not in operation