72
6
5
4
3
2
1
A
B
C
D
E
F
G
H
PG-M15X
PG-M15S
AN-M15T
BLOCK DIAGRAM-2 / BLOCKSCHALTBILD-2 (PG-M15X)
Ë
FORMATTER Unit / FORMATIERER-Einheit
VCC2,VOFFSET,VBIAS
VERSET
GENERA
TION
RESET ASIC
DMD
0.7î XGA
DATAPATH
FORMATTER
DPF2A
SDRAM B
sht10
SDRAM A
sht9
ALLEGRO
MOTOR
CONTROL
sht5
MICRO
CONTROLLER
sht14
CONTROL
FPGA
sht6
CONFIG/
SEQUENCE
PROM
CUSTOMER INTERFACE CONNECTOR
VCC2 (DMD)
VCC2 (ASIC)
VOFFSET
VBIAS
VRESET
+
5
V
+12V
CLOCK
OSC
sht7
sht1
1-15
sht16
sht18
DPF2A CONTROL
VSYNCZ
HSYNCZ
ACT
DA
T
A
TFIELD
OLACT
SYNCV
A
L
LAMP CONTROL&STATUS
COLOR WHEEL INDEX
FPGA CLK
FLASH
PROGRAMMING
HEADER
IIC BUS
HITACHI
DOWNLOAD
HEADER
CLKIN
sht3
COLOR
WHEEL
CONTROL
COLOR WHEEL
S
T
A
T
U
S
CWRSTZ
VOLTAGE ENABLES
BIAS BIN
BIAS/RESET CONTROL
DMD CONTROL
PBUS2
MENORY CONTROL A
MENORY ADDRESS A(12)
MENORY ADDRESS B(12)
MENORY CONTROL B
DMD CONTROL
sht8
COLOR
WHEEL
DRIVE
U2
DATA (8)
U504
sht7
VSYNCZ, RESETZ
U13
U6
ADDRESS (19)
U12
MBIASRST (16)
INPUTCLK
U9
FPGA CLK
DMD CLK
SDRAM CLK
U10
U8
DA
T
A(0..63)
DMD
DA
T
A(0..63)