Sharp 32LF-94EC, Service Manual, Page: 38 / 82

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AK53 D.O.C. Service Manual 22/03/2004
12.5.SDRAM 64MBIT (IC315)
12.5.1.General Description
Please note that in the following explanation one of the SDRAM alternative is used.
The K4S641632D is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x
1,048,576 words by 16 bits, fabricated with SAMSUNG¢s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
12.5.2.Features
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
12.5.3.Pin Description
PIN NAME INPUT FUNCTION
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select Disables or enables device operation by masking or enabling all
inputs except CLK, CKE and L(U)DQM
CKE Clock enable Masks system clock to freeze operation from the next clock
cycle.
CKE should be enabled at least one cycle prior to new
command.
Disable input buffers for power down in standby.
A0 ~ A11 Address Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA7
BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row address strobe Latches row addresses on the positive going edge of the CLK
with RAS low.
Enables row access & precharge.
CAS Column address strobe Latches column addresses on the positive going edge of the
CLK with CAS low.
Enables column access.
WE Write enable Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
L(U)DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the
output.
Blocks data input when L(U)DQM active.
DQ0 ~ 15 Data input/output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to
provide improved noise immunity.
N.C/RFU No connection
/reserved for future use This pin is recommended to be left No Connection on the device.