ISO 9001 / ISO 14001
01/06/2016
© Productivity Engineering GmbH
Page 8 of 22
EVA4204/4301
User Guide
Evaluation Board for 80W PFC Supply
2.5 Output Bypass Capacitor
PE4201/PE4301
The bypass capacitor on the output of the circuit has to be able to suppress the ripple of the switching
frequency and the residues of the full-wave rectified input frequency (2 * f
in
).
f
1
out
∆
V
1
out
V
out
P
=
out
C
∗
∗
(28)
It is recommended to use 4 * f
in
to suppress the sine wave residues of the input voltage for calculation.
The ripple shall be assumed to be at 5% of the output voltage.
at 40W :
34,2µF
=
50Hz
4
1
405V
0.05
1
405V
40W
2
=
out
C
∗
∗
∗
∗
∗
(29)
at 80W :
68,7µF
=
50Hz
4
1
405V
0.05
1
405V
80W
2
=
out
C
∗
∗
∗
∗
∗
(30)
A capacitor with at least 47µF (C13) should be used. It has to withstand the maximum output voltage.
The equivalent series resistance (ESR) of the capacitor shall not build up a voltage higher than half the
ripple amplitude (2,5% of V
out-max
) at peak-current.
16
Ω
=
0,61A
405V
0,025
=
peak
I
out
∆
V
=
C
R
∗
(31)
To reduce the ESR it is recommend to place a capacitor with small ESR in parallel to the high
capacitance device. For 2% ripple at minimum switching frequencies the parallel capacitance can be
calculated according to equation (23):
0,61µF
=
40kHz
1
405V
0.02
1
405V
80W
=
out2
C
∗
∗
∗
(32)
The capacitor on the board is C12=100n/400V.
