Sel SEL-300 Series, Application Manual

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SEL Application Guide 2020-04 Date Code 20200326
which causes the bottom input of AND 3 to be true. At the same time, Zone 2 at Relay 2 also
asserts and the Zone 3 element remains deasserted. This causes the output of AND 4 to assert,
sending a key to Relay 1 and making the bottom input of AND 2 true. Once each relay receives a
key from the remote end, the outputs of AND 2 and AND 3 assert, causing the relays to trip with
no intentional delay.
Now imagine that the fault did not occur at Point F1 but rather at F2. In this scenario, Zone 2 at
Relay 1 asserts, and Zone 3 deasserts. AND 1 asserts, causing a key to be transmitted and the top
input of AND 2 to assert. At this point, Relay 1 is waiting on a key from Relay 2 to trip. At
Relay 2, the Zone 2 element deasserts while the Zone 3 element asserts. This means that AND 4
does not become true. Therefore, a key is not sent to Relay 1, which prevents a high-speed trip. At
Relay 2, even though a key has been received on the bottom input of AND 3, the top input of
AND 3 deasserts, preventing a high-speed trip.
NOTE:
This section provides an overview of POTT schemes. For a more in-depth discussion, refer to [1].
POTT S
ETUP
To setup a POTT scheme in the SEL-421-5, SEL-311L, or SEL-321-1 relays, you must enable the
logic in the relays. The settings in the relays are similar.
Table 5 , Table 6 , and Table 7 provide a
summary of how to set up the POTT logic in the SEL-421-5, SEL-311C-1, and SEL-321-1, respec-
tively.
Figure 5 M
IRRORED
B
ITS
Communications Via Direct Fiber
Figure 6 Simplified POTT Logic
Optical Fiber
Zone 3
Zone 2 Zone 3
Zone 2
TX
RX
RX
TX
Relay 2 Relay 1
F1 F2
1 2 3 4
Zone 2
Zone 3
AND 1
AND 2 TRIP
Key
Receiver
Zone 2
Zone 3
AND 4
AND 3 TRIP
Relay 1 Relay 2
Key
Receiver
Key
Transmitter
Key
Transmitter